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src/sim/erc32 ChangeLog erc32.c func.c interf. ...
- From: joel at sourceware dot org
- To: gdb-cvs at sourceware dot org
- Date: 11 May 2010 14:18:21 -0000
- Subject: src/sim/erc32 ChangeLog erc32.c func.c interf. ...
CVSROOT: /cvs/src
Module name: src
Changes by: joel@sourceware.org 2010-05-11 14:18:20
Modified files:
sim/erc32 : ChangeLog erc32.c func.c interf.c sis.c sis.h
Log message:
2010-04-20 Tiemen Schut <T.Schut@sron.nl>
* erc32.c (sis_memory_write): Change prototype to const unsigned char *.
* func.c (exec_cmd, event, advance_time, wait_for_irq): Use uint64
for counts.
* interf.c (run_sim): Change icount to uint64_t. Use strtol directly.
(sim_resume): Specify maximum run time as uint64.
* sis.c (run_sim): Change icount to uint64_t.
* sis.h: Define uint64 as uint64_t. Change various fields and
prototypes to uint64 to support longer simulations.
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/ChangeLog.diff?cvsroot=src&r1=1.31&r2=1.32
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/erc32.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/func.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/interf.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/sis.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/erc32/sis.h.diff?cvsroot=src&r1=1.2&r2=1.3