src/sim/mips ChangeLog cp1.c interp.c mips.igen

[ths at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	ths@sourceware.org	2007-02-19 17:31:08

Modified files:
	sim/mips       : ChangeLog cp1.c interp.c mips.igen 

Log message:
	* cp1.c (value_fpr): Don't inherit existing FPR_STATE for
	uninterpreted formats. If fmt is one of the uninterpreted types
	don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
	fmt_word, and fmt_uninterpreted_64 like fmt_long.
	(store_fpr): When writing an invalid odd register, set the
	matching even register to fmt_unknown, not the following register.
	* interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
	the the memory window at offset 0 set by --memory-size command
	line option.
	(sim_store_register): Handle storing 4 bytes to an 8 byte floating
	point register.
	(sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
	register.
	(sim_monitor): When returning the memory size to the MIPS
	application, use the value in STATE_MEM_SIZE, not an arbitrary
	hardcoded value.
	(cop_lw): Don' mess around with FPR_STATE, just pass
	fmt_uninterpreted_32 to StoreFPR.
	(cop_sw): Similarly.
	(cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
	(cop_sd): Similarly.
	* mips.igen (not_word_value): Single version for mips32, mips64
	and mips16.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/ChangeLog.diff?cvsroot=src&r1=1.133&r2=1.134
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/cp1.c.diff?cvsroot=src&r1=1.21&r2=1.22
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/interp.c.diff?cvsroot=src&r1=1.20&r2=1.21
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/mips.igen.diff?cvsroot=src&r1=1.61&r2=1.62