src/sim/sh ChangeLog gencode.c interp.c

[corinna at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	corinna@sourceware.org	2004-09-08 09:11:50

Modified files:
	sim/sh         : ChangeLog gencode.c interp.c 

Log message:
	* gencode.c (movua.l): Compensate for endianness.
	
	* interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro.
	(in_delay_slot): New flag variable.
	(Delay_Slot): Set in_delay_slot.
	(sim_resume): Reset in_delay_slot after leaving code switch.
	* gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all
	instructions not allowed in delay slots.
	
	Commited by Corinna Vinschen <vinschen@redhat.com>
	Introduce SH2a support.
	* interp.c: Change type of jump table to short.  Add various macros.
	(sim_load): Save the bfd machine code.
	(sim_create_inferior): Ditto.
	(union saved_state_type): Add tbr, ibnr and ibcr registers.
	Move bfd_mach to end of struct.  Add regstack pointer.
	(init_dsp): Don't swap contents of sh_dsp_table any more.  Instead
	use it directly in its own switch statement.  Allocate space for 512
	register banks.
	(do_long_move_insn): New function.
	(do_blog_insn): Ditto.
	(trap): Use trap #13 and trap #14 to set ibnr and ibcr.
	* gencode.c: Move movx/movy insns into separate switch statement.
	(op tab): Add sh2a insns.  Reject instructions that are disabled
	on that chip.
	(gensim_caselist): Generate default case here instead of in caller.
	(gensim): Generate two separate switch statements.  Call
	gensim_caselist once for each (for movsxy_tab and for tab).
	Add tokens for r15 and multiple regs.
	(conflict_warn, warn_conflicts): Add for debugging.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/ChangeLog.diff?cvsroot=src&r1=1.37&r2=1.38
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/gencode.c.diff?cvsroot=src&r1=1.29&r2=1.30
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/interp.c.diff?cvsroot=src&r1=1.15&r2=1.16