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src/sim/sh ChangeLog interp.c gencode.c
- From: msnyder at sources dot redhat dot com
- To: gdb-cvs at sources dot redhat dot com
- Date: 9 Jan 2004 19:44:50 -0000
- Subject: src/sim/sh ChangeLog interp.c gencode.c
CVSROOT: /cvs/src
Module name: src
Changes by: msnyder@sourceware.org 2004-01-09 19:44:50
Modified files:
sim/sh : ChangeLog interp.c gencode.c
Log message:
2004-01-07 Michael Snyder <msnyder@redhat.com>
* gencode.c: Replace 'Hitachi' with 'Renesas'.
(op tab): Add new instructions for sh4a, DBR, SBR.
(expand_opcode): Add handling for new movxy combinations.
(gensym_caselist): Ditto.
(expand_ppi_movxy): Remove movx/movy expansions,
now handled in expand_opcode.
(gensym): Add some helpful macros.
(expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
instead of 8-bit table (some insns are ambiguous to 8 bits).
(ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table.
* interp.c: Replace 'Hitachi' with 'Renesas'.
(union saved_state_type): Add dbr, sgr, ldst.
(get_loop_bounds_ext): New function.
(init_dsp): Add bfd_mach_sh4al_dsp.
(sim_resume): Handle extended loop bounds.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/ChangeLog.diff?cvsroot=src&r1=1.30&r2=1.31
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/interp.c.diff?cvsroot=src&r1=1.12&r2=1.13
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/sh/gencode.c.diff?cvsroot=src&r1=1.22&r2=1.23