src/sim/m32r ChangeLog Makefile.in arch.c arch ...

[nickc at sources dot redhat dot com]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	nickc@sourceware.org	2003-12-11 11:33:44

Modified files:
	sim/m32r       : ChangeLog Makefile.in arch.c arch.h cpu.c cpu.h 
	                 cpuall.h cpux.c cpux.h decode.c decode.h 
	                 decodex.c decodex.h m32r-sim.h m32r.c model.c 
	                 modelx.c sem-switch.c sem.c semx-switch.c 
	                 sim-if.c sim-main.h traps.c 
Added files:
	sim/m32r       : cpu2.c cpu2.h decode2.c decode2.h m32r2.c 
	                 model2.c sem2-switch.c 

Log message:
	Add support for the m32r2 processor

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpu2.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpu2.h.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/decode2.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/decode2.h.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/m32r2.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/model2.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sem2-switch.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/ChangeLog.diff?cvsroot=src&r1=1.17&r2=1.18
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/Makefile.in.diff?cvsroot=src&r1=1.8&r2=1.9
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/arch.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/arch.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpu.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpu.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpuall.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpux.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/cpux.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/decode.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/decode.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/decodex.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/decodex.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/m32r-sim.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/m32r.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/model.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/modelx.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sem-switch.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sem.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/semx-switch.c.diff?cvsroot=src&r1=1.6&r2=1.7
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sim-if.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/sim-main.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m32r/traps.c.diff?cvsroot=src&r1=1.4&r2=1.5