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[Bug 1001219] Ethernet driver for STM32 connectivity line with port on MMstm32f107 board.
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: ecos-patches at ecos dot sourceware dot org
- Date: Sat, 22 Oct 2011 13:21:39 +0100
- Subject: [Bug 1001219] Ethernet driver for STM32 connectivity line with port on MMstm32f107 board.
- Auto-submitted: auto-generated
- References: <bug-1001219-104@http.bugs.ecos.sourceware.org/>
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--- Comment #19 from Ilija Kocho <ilijak@siva.com.mk> 2011-10-22 13:21:29 BST ---
(In reply to comment #5)
> Created an attachment (id=1394)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1394) [details]
> Ethernet driver for STM32 CL
>
> Ethernet driver for STM32 Connectivity Line
Some comments on Ethernet driver:
MII and RMII interfaces are mutually exclusive and CDL should reflect this. A
cdl_option with legal values "RMII" "MII" would provide it and in addition make
it visible in configtool.
"Remap pins" could be also visible if it were cdl_option.
Regarding pins, some addition to my statement in Comment #11. Since pins are
being provided by HAL, they should be defined in HAL (unlike other Ethernet
definitions such as registers, etc.). Preferable place is plf_io.h rather than
var_io.h. because other chips (present or future) may have different pin
mapping.
On the other hand, the pin functions - once assigned to Ethernet (although pins
are provided provided by HAL) belong to Ethernet so their naming should reflect
this Here is a plf_io.h snuppet:
plf_io.h snippet --------------------------------
#define CYGHWR_IO_ETH_STM32MAC_MII_COL \
CYGHWR_HAL_STM32_GPIO(A, 3, IN , FLOATING)
...
-------------------------------------------------
Also if_stm32.c
Could CYGHWR_HAL_STM32_GPIO_SET(CYGHWR_...); lines be replaced by a loop?
And in order to avoid specifying HAL specific macros in a device driver, a new
macro can be defined CYGHWR_IO_ETH_STM32MAC_PIN(...).
Note: In macro names above I arbitrarily put "STM32MAC" segment. Probably there
is a more appropriate name for this Ethernet controller.
CYGNUM_DEVS_ETH_CORTEXM_STM32_RX_BUFS: Is there a range of legal values?
BTW other Ethernet devices that I have seen also provide configuration option
for TX_BUFFS.Is this fixed on STM32 Ethernet controller?
TCP/IP Checksum generation and check.
FYI lwIP is aware of such hardware features
http://sourceware.org/ml/ecos-discuss/2011-07/msg00017.html
and it would be good if they are implemented.
Ilija
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