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Re: IO FLASH and caches
Edgar Grimberg <edgar.grimberg@zylin.com> writes:
> Hi,
>
> The attached patch handles the case where the CPU cannot disable
> caches and needs to provide an uncached address instead. The fix was
> tested with a NIOS2 CPU.
I don't think this patch is correct. In general flash should be read
through the cache. Flash devices are slow and using the cache improves
performance. It is the responsibility of the flash driver to ensure
that stale data is evicted from the caches by calling cache control
macros. In general the drivers already do this.
This patch forces uncached access for any architecture that defines
CYGARC_UNCACHED_ADDRESS(). Many platforms (e.g. MIPS, PPC, ARM9)
provide both cached and uncached views of memory. These architectures
also provide mechanisms for flushing and invalidating the caches.
As far as I am aware, the NIOS2 has cache control instructions, so I
am not sure what the actual reason for this patch is.
In any case, I don't think that other architectures should be forced
to operate at lower performance just to accommodate the shortcomings
of one particular architecture.
--
Nick Garnett eCos Kernel Architect
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