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Patch for AT91_FLASH.C supports also the 512kByte devices...
- From: "Oliver Munz @ SNR" <oli at snr dot ch>
- To: ecos-patches at sourceware dot org
- Date: Sat, 16 May 2009 17:00:15 +0200
- Subject: Patch for AT91_FLASH.C supports also the 512kByte devices...
- Reply-to: "oliver munz @ s p e a g" <munz at speag dot ch>, oli at snr dot ch
For the antispam-filter:
------------------------------------------------------------------------
Index: packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl,v
retrieving revision 1.5
diff -u -r1.5 flash_at91.cdl
--- packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl 19 Feb
2006 19:43:01 -0000 1.5
+++ packages/devs/flash/arm/at91/current/cdl/flash_at91.cdl 16 May
2009 00:22:24 -0000
@@ -42,7 +42,7 @@
# Author(s): dmoseley
# Original data: gthomas
# Contributors: Andrew Lunn, Oliver Munz
-# Date: 2000-10-25
+# Date: 2009-05-15
#
#####DESCRIPTIONEND####
#
@@ -74,5 +74,16 @@
WARNING: The errata says that these lock bits only have
a life of 100 cycles for the AT91SAM7S devices."
}
+ + cdl_option CYGBLD_DEV_FLASH_AT91_SUPPORT_EFC1 {
+ display "Support the 512kByte Flash"
+ default_value 1
+ description "
+ This option allows the programming of the 2nd 256kByte-flash
+ device in the AT91SAM7??512 devices. This option has the
+ drawback of more complexity and code and thus, if You only
+ want to use the devices until 256kByte flash, You should
+ desable this..."
+ }
}
Index: packages/devs/flash/arm/at91/current/src/at91_flash.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/flash/arm/at91/current/src/at91_flash.c,v
retrieving revision 1.9
diff -u -r1.9 at91_flash.c
--- packages/devs/flash/arm/at91/current/src/at91_flash.c 3 Nov 2008
08:41:59 -0000 1.9
+++ packages/devs/flash/arm/at91/current/src/at91_flash.c 16 May 2009
00:25:43 -0000
@@ -41,8 +41,8 @@
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
-// Contributors: gthomas, dmoseley, Andrew Lunn, Oliver Munz
-// Date: 2000-07-26
+// Contributors: gthomas, dmoseley, Andrew Lunn, Oliver Munz, Kasim Mala
+// Date: 2009-05-15
// Purpose: // Description: // @@ -62,7 +62,7 @@
#include <string.h>
-#define FLASH_TIMEOUT 100000
+#define FLASH_TIMEOUT 100000 /* Stupid timeout depends of the CPU
clock speed... */
#ifdef CYGBLD_DEV_FLASH_AT91_LOCKING
static cyg_uint32 sector_size;
@@ -70,6 +70,17 @@
// Disable the flash controller from erasing the page before
// programming it
+
+#ifdef CYGBLD_DEV_FLASH_AT91_SUPPORT_EFC1 /* simplest soulution
assuming there will never
+ 1024kByte devices show
up... */
+ #define PAGE_AT_WITCH_WE_USE_THE_EFC1 1024
+ #define SECTOR_AT_WITCH_WE_USE_THE_EFC1 16
+ #define AT91_MC_FMR1 (AT91_MC_FMR + 0x10)
+ #define AT91_MC_FCR1 (AT91_MC_FCR + 0x10)
+ #define AT91_MC_FSR1 (AT91_MC_FSR + 0x10)
+#endif
+
+
static void flash_erase_before_write_disable (void)
{
@@ -78,6 +89,9 @@
HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, fmr);
fmr = fmr | AT91_MC_FMR_NEBP;
HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, fmr);
+#ifdef AT91_MC_FMR1 /* or in other words at91sam7x512 */
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR1, fmr);
+#endif
}
// Enable the flash controller to erase the page before programming
@@ -91,8 +105,117 @@
HAL_READ_UINT32(AT91_MC+AT91_MC_FMR, fmr);
fmr = fmr & ~((cyg_uint32) AT91_MC_FMR_NEBP);
HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, fmr);
+#ifdef AT91_MC_FMR1 /* or in other words at91sam7x512 */
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR1, fmr);
+#endif
}
+#ifdef AT91_MC_FMR1 /* or in other words at91sam7x512 */
+
+// Is the flash controller ready to accept the next command?
+static __inline__ cyg_bool +flash_controller_is_ready(cyg_uint32 page)
+CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command");
+
+static __inline__ cyg_bool +flash_controller_is_ready(cyg_uint32 page) +{
+ cyg_uint32 fsr;
+ + if (page < PAGE_AT_WITCH_WE_USE_THE_EFC1){
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FSR, fsr);
+ } else {
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FSR1, fsr);
+ }
+ return (fsr & AT91_MC_FSR_FRDY ? true : false);
+}
+
+// Busy loop waiting for the controller to finish the command.
+// Wait a maximum of timeout loops and then return an error.
+static __inline__ int +flash_wait_for_controller (cyg_uint32 page,
cyg_uint32 timeout) +CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command");
+
+static __inline__ int +flash_wait_for_controller (cyg_uint32 page,
cyg_uint32 timeout)
+{
+ while (!flash_controller_is_ready(page)){
+ timeout--;
+ if (!timeout) {
+ return FLASH_ERR_DRV_TIMEOUT;
+ }
+ }
+ return FLASH_ERR_OK;
+}
+
+
+// Execute one command on the flash controller. This code should
+// probably not be in flash
+
+static int +flash_run_command(cyg_uint32 address, +
cyg_uint32 command, + cyg_uint32 timeout)
+CYGBLD_ATTRIB_SECTION(".2ram.flash_run_command");
+
+static int +flash_run_command(cyg_uint32 address, +
cyg_uint32 command, + cyg_uint32 timeout) +{
+ cyg_uint32 retcode;
+ cyg_uint32 fsr;
+ cyg_uint32 mask;
+ cyg_uint32 page;
+ + page = ((cyg_uint32) address - (cyg_uint32) flash_info.start) /
+ flash_info.block_size;
+ + // Wait for the last command to finish
+ retcode = flash_wait_for_controller(page, timeout);
+ if (retcode != FLASH_ERR_OK){
+ return retcode;
+ }
+ + HAL_DISABLE_INTERRUPTS(mask);
+ + if (page < PAGE_AT_WITCH_WE_USE_THE_EFC1){
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FCR, +
command |
+ ((page & AT91_MC_FCR_PAGE_MASK) <<
AT91_MC_FCR_PAGE_SHIFT) |
+ AT91_MC_FCR_KEY);
+ } else {
+ HAL_WRITE_UINT32(AT91_MC+AT91_MC_FCR1, +
command |
+ (((page - PAGE_AT_WITCH_WE_USE_THE_EFC1) &
AT91_MC_FCR_PAGE_MASK) << AT91_MC_FCR_PAGE_SHIFT) |
+ AT91_MC_FCR_KEY);
+ }
+
+ retcode = flash_wait_for_controller(page, timeout);
+
+ HAL_RESTORE_INTERRUPTS(mask);
+
+ if (retcode != FLASH_ERR_OK){
+ return retcode;
+ }
+
+ // Check for an error
+ if (page < PAGE_AT_WITCH_WE_USE_THE_EFC1){
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FSR, fsr);
+ } else {
+ HAL_READ_UINT32(AT91_MC+AT91_MC_FSR1, fsr);
+ }
+
+ if ((fsr & AT91_MC_FSR_LOCKE) == AT91_MC_FSR_LOCKE)
+ return FLASH_ERR_PROTECT;
+ if ((fsr & AT91_MC_FSR_PROGE) == AT91_MC_FSR_PROGE)
+ return FLASH_ERR_PROGRAM;
+
+ return FLASH_ERR_OK;
+}
+#else /* not at91sam7x512 */
+
+
// Is the flash controller ready to accept the next command?
static __inline__ cyg_bool flash_controller_is_ready(void) @@ -179,6
+302,9 @@
return FLASH_ERR_OK;
}
+#endif
+
+
// The flash is embedded in the CPU package. So return the chip
// ID. This allows us to determine if the chip is one we support and
// the size of the flash
@@ -243,19 +369,20 @@
flash_info.blocks = 1024;
lock_bits = 16;
break;
+ case AT91_DBG_C1R_FLASH_512K:
+ flash_info.block_size = 256;
#ifdef AT91_MC_FMR1
- case AT91_DBG_C1R_FLASH_512K:
- flash_info.block_size = 256;
- flash_info.blocks = 1024;
- lock_bits = 16;
- (*flash_info.pf)("at91_flash: Only EFC0 is supported for
writes and locks");
- //flash_info.blocks = 2048;
- //lock_bits = 32;
- break;
+ flash_info.blocks = 2048;
+ lock_bits = 32;
+#else
+ flash_info.blocks = 1024;
+ lock_bits = 16;
+ (*flash_info.pf)("at91_flash: Only EFC0 is supported for writes
and locks");
#endif
- default:
- goto out;
- }
+ break;
+ default:
+ goto out;
+ }
} else {
// if there is both flash & ROM then: ROM=AT91_DBG_C1R_FLASH,
flash=AT91_DBG_C1R_FLASH2
switch (chipID1r & AT91_DBG_C1R_FLASH2_MASK) {
@@ -279,19 +406,20 @@
flash_info.blocks = 1024;
lock_bits = 16;
break;
-#ifdef AT91_MC_FMR1
case AT91_DBG_C1R_FLASH2_512K:
flash_info.block_size = 256;
+#ifdef AT91_MC_FMR1
+ flash_info.blocks = 2048;
+ lock_bits = 32;
+#else
flash_info.blocks = 1024;
lock_bits = 16;
(*flash_info.pf)("at91_flash: Only EFC0 is supported for
writes and locks");
- //flash_info.blocks = 2048;
- //lock_bits = 32;
- break;
#endif
- default:
- goto out;
- }
+ break;
+ default:
+ goto out;
+ }
}
flash_info.buffer_size = 0;
flash_info.start = (void *) 0x00100000;
@@ -309,9 +437,6 @@
flash_mode = flash_mode | (fmcn << AT91_MC_FMR_FMCN_SHIFT);
HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR, flash_mode);
#ifdef AT91_MC_FMR1
- HAL_READ_UINT32(AT91_MC+AT91_MC_FMR1, flash_mode);
- flash_mode = flash_mode & ~AT91_MC_FMR_FMCN_MASK;
- flash_mode = flash_mode | (fmcn << AT91_MC_FMR_FMCN_SHIFT);
HAL_WRITE_UINT32(AT91_MC+AT91_MC_FMR1, flash_mode);
#endif
@@ -394,7 +519,16 @@
sector = (((cyg_uint32) block) - (cyg_uint32) flash_info.start) /
sector_size;
+#ifdef AT91_MC_FMR1 /* or in other words at91sam7x512 */
+ if (sector < SECTOR_AT_WITCH_WE_USE_THE_EFC1){
+ HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status);
+ } else {
+ HAL_READ_UINT32(AT91_MC + AT91_MC_FSR1, status);
+ sector = sector - SECTOR_AT_WITCH_WE_USE_THE_EFC1;
+ }
+#else
HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status);
+#endif
if (status & (1 << (sector + 16))){
retcode = flash_run_command(block, @@ -419,7 +553,16 @@
sector = (((cyg_uint32) block) - (cyg_uint32) flash_info.start) /
sector_size;
+#ifdef AT91_MC_FMR1 /* or in other words at91sam7x512 */
+ if (sector < SECTOR_AT_WITCH_WE_USE_THE_EFC1){
+ HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status);
+ } else {
+ HAL_READ_UINT32(AT91_MC + AT91_MC_FSR1, status);
+ sector = sector - SECTOR_AT_WITCH_WE_USE_THE_EFC1;
+ }
+#else
HAL_READ_UINT32(AT91_MC + AT91_MC_FSR, status);
+#endif
if (!(status & (1 << (sector + 16)))){
retcode = flash_run_command(block,