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ADC patches


Thanks for the commit of my ADC driver work. In the meantime I fixed a bug with timer setup and usage for the STM32 driver as well as some typos in the synthetic driver. Patches are attached.
diff --git a/packages/devs/adc/cortexm/stm32/current/ChangeLog b/packages/devs/adc/cortexm/stm32/current/ChangeLog
index 3d7f028..61a4286 100644
--- a/packages/devs/adc/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/adc/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-05  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* src/adc_stm32.c:
+	Fixed a bug in setup and usage of the timer.
+
 2009-02-24  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* cdl/adc_stm32.cdl:
diff --git a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
index a7790db..adb9466 100644
--- a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
+++ b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
@@ -341,17 +341,9 @@ stm32_adc_set_rate( cyg_adc_channel *chan, cyg_uint32 rate)
     HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_ARR,
                      period - 1);
     
-    // Set direction = down, clock divider = 1
-    cr = CYGHWR_HAL_STM32_TIM_CR1_DIR | CYGHWR_HAL_STM32_TIM_CR1_CKD_1;
-    HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR1, cr);
-    
     // Reinitialize timer
     cr = CYGHWR_HAL_STM32_TIM_EGR_UG;
     HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_EGR, cr);
-    
-    // Enable generation of TRGO event
-    cr = CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE;
-    HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR2, cr);
 }
 
 //-----------------------------------------------------------------------------
@@ -367,12 +359,16 @@ stm32_dma_isr(cyg_vector_t vector, cyg_addrword_t data)
     cyg_uint32 chan_active = info->chan_mask;
     cyg_uint16 *sample = info->dma_buf;
     cyg_adc_channel **chan = info->chan;
-    cyg_uint32 res = 0;
+    cyg_uint32 isr;
+    cyg_uint32 res = CYG_ISR_HANDLED;
+    
+    HAL_READ_UINT32(info->setup->dma_base + CYGHWR_HAL_STM32_DMA_ISR, isr);
+    if (!(isr & CYGHWR_HAL_STM32_DMA_ISR_MASK(info->setup->dma_channel)))
+        return 0;
     
     while (chan_active) {
         if (chan_active & 0x1)
-            res |= (CYG_ISR_HANDLED |
-                    cyg_adc_receive_sample(*chan, *sample++ & 0xfff));
+            res |= cyg_adc_receive_sample(*chan, *sample++ & 0xfff);
         chan_active >>= 1;
         chan++;
     }
@@ -486,7 +482,17 @@ stm32_adc_init_device(cyg_adc_device *device)
     // Enable scanning
     cr = CYGHWR_HAL_STM32_ADC_CR1_SCAN;
     HAL_WRITE_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR1, cr);
+
+
+    // Set timer direction = down, clock divider = 1
+    cr = CYGHWR_HAL_STM32_TIM_CR1_DIR | CYGHWR_HAL_STM32_TIM_CR1_CKD_1;
+    HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR1, cr);
+
+    // Enable generation of TRGO event
+    cr = CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE;
+    HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR2, cr);
     
+
     // Setup DMA channel
     HAL_WRITE_UINT32(info->setup->dma_base + 
                      CYGHWR_HAL_STM32_DMA_CPAR(info->setup->dma_channel),
diff --git a/packages/devs/adc/synth/current/ChangeLog b/packages/devs/adc/synth/current/ChangeLog
index c85cdfd..4530e13 100644
--- a/packages/devs/adc/synth/current/ChangeLog
+++ b/packages/devs/adc/synth/current/ChangeLog
@@ -1,3 +1,9 @@
+2009-03-05  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* cdl/adc_synth.cdl:
+	* cdl/adc_synth.c:
+	Fixed some typos.
+
 2009-02-27  Simon Kallweit  <simon.kallweit@intefo.ch>
 
 	* Synthethic ADC driver package created
diff --git a/packages/devs/adc/synth/current/cdl/adc_synth.cdl b/packages/devs/adc/synth/current/cdl/adc_synth.cdl
index bb82e2c..ac471f7 100644
--- a/packages/devs/adc/synth/current/cdl/adc_synth.cdl
+++ b/packages/devs/adc/synth/current/cdl/adc_synth.cdl
@@ -2,7 +2,7 @@
 #
 #      adc_synth.cdl
 #
-#      eCos Synthethic ADC configuration data
+#      eCos Synthetic ADC configuration data
 #
 # ====================================================================
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
diff --git a/packages/devs/adc/synth/current/src/adc_synth.c b/packages/devs/adc/synth/current/src/adc_synth.c
index bb6b77f..42ddab2 100644
--- a/packages/devs/adc/synth/current/src/adc_synth.c
+++ b/packages/devs/adc/synth/current/src/adc_synth.c
@@ -2,7 +2,7 @@
 //
 //      adc_synth.c
 //
-//      ADC driver for Synthethic ADC
+//      ADC driver for Synthetic ADC
 //
 //==========================================================================
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
@@ -96,7 +96,7 @@ typedef struct synth_adc_channel_info {
 } synth_adc_channel_info;
 
 //-----------------------------------------------------------------------------
-// Synthethic ADC device
+// Synthetic ADC device
 
 typedef struct synth_adc_info {
     synth_adc_channel_info  *chan_info;     // Channel infos
@@ -134,7 +134,7 @@ CYG_ADC_FUNCTIONS(synth_adc_funs,
                   synth_adc_set_rate);
 
 //-----------------------------------------------------------------------------
-// Synthethic ADC channel info macro
+// Synthetic ADC channel info macro
 
 #define SYNTH_ADC_CHANNEL_INFO(_chan_)                                      \
 {                                                                           \
@@ -144,7 +144,7 @@ CYG_ADC_FUNCTIONS(synth_adc_funs,
 }
 
 //-----------------------------------------------------------------------------
-// Synthethic ADC channel instance macro
+// Synthetic ADC channel instance macro
 
 #define SYNTH_ADC_CHANNEL(_chan_)                                           \
 CYG_ADC_CHANNEL(                                                            \
@@ -164,7 +164,7 @@ DEVTAB_ENTRY(                                                               \
 );
 
 //-----------------------------------------------------------------------------
-// Synthethic ADC device instance
+// Synthetic ADC device instance
 
 static synth_adc_channel_info synth_adc_channel_infos[NUM_CHANNELS] = {
     SYNTH_ADC_CHANNEL_INFO(0),

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