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RE: ARM9 Cache Handling
- From: "Rene Nielsen" <rbn at vitesse dot com>
- To: <ecos-patches at sourceware dot org>
- Date: Mon, 2 Mar 2009 17:19:49 +0100
- Subject: RE: ARM9 Cache Handling
- References: <376637F07F8A9242AD11921B15FA17DC8AF2DA@mx-dk.vsc.vitesse.com>
Hi again,
Sorry to bug you, but this patch is gating for the HAL Platform I'm
about to post, so if I could get you to have a look at it, I'd be happy.
Thanks,
Rene
-----Original Message-----
From: ecos-patches-owner@ecos.sourceware.org
[mailto:ecos-patches-owner@ecos.sourceware.org] On Behalf Of Rene
Nielsen
Sent: 13. februar 2009 14:04
To: ecos-patches@sourceware.org
Subject: ARM9 Cache Handling
The attached patch contains several changes/additions to the ARM9
variants cache implementation:
The following changes affect all ARM9 variants:
1) In HAL_ICACHE_ENABLE(): Enabling the MMU should not be part of the
cache routines.
2) CYGSEM_HAL_FLASH_CACHES_NODISABLE: New CDL option for controlling how
HAL_FLASH_CACHES_OFF() and HAL_FLASH_CACHES_ON() are implemented. If it
is not defined or 0, it'll be the good old implementation. Otherwise,
these macros will be empty. Default for the option is not defined.
ARM926EJ-specific changes:
3) Parameterized HAL_DCACHE_SIZE and HAL_ICACHE_SIZE. Defaults remain 8
and 16 KBytes, respectively.
4) HAL_DCACHE_STORE(): New macro for flushing part of the D-cache to
memory.
5) HAL_DCACHE_INVALIDATE(): New macro for invalidating part of the
D-cache.
6) HAL_DCACHE_FLUSH(): New macro for flushing and invalidating part of
the D-cache.
Regards,
Rene Schipp von Branitz Nielsen
Vitesse Semiconductors