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[PATCH] [RFC] Separate board's pio layout
- From: Evgeniy Dushistov <dushistov at mail dot ru>
- To: ecos-devel at ecos dot sourceware dot org, ecos-patches at ecos dot sourceware dot org
- Date: Sun, 30 Nov 2008 20:39:10 +0300
- Subject: [PATCH] [RFC] Separate board's pio layout
What do you think about that?
The main goal to make var_io.h little simpler,
so adding a new board would be more easy then now.
This patch separate board's pio layout.
Extract each variant of layout to different header files.
---
.../at91sam7s/current/cdl/hal_arm_at91sam7s.cdl | 9 +
.../phycore/current/cdl/hal_arm_at91_phycore.cdl | 3 +-
.../hal/arm/at91/var/current/include/pio_default.h | 58 ++
.../hal/arm/at91/var/current/include/pio_m55800a.h | 97 ++
.../hal/arm/at91/var/current/include/pio_sam7s.h | 145 +++
.../hal/arm/at91/var/current/include/pio_sam7se.h | 393 +++++++++
.../hal/arm/at91/var/current/include/pio_sam7x.h | 222 +++++
packages/hal/arm/at91/var/current/include/var_io.h | 918 +-------------------
8 files changed, 929 insertions(+), 916 deletions(-)
create mode 100644 packages/hal/arm/at91/var/current/include/pio_default.h
create mode 100644 packages/hal/arm/at91/var/current/include/pio_m55800a.h
create mode 100644 packages/hal/arm/at91/var/current/include/pio_sam7s.h
create mode 100644 packages/hal/arm/at91/var/current/include/pio_sam7se.h
create mode 100644 packages/hal/arm/at91/var/current/include/pio_sam7x.h
diff --git a/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl b/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
index 1bbc51e..e1907bf 100644
--- a/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
+++ b/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
@@ -99,6 +99,9 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 {
CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s321" }
description "
Is the AT91SAM7 device a member of the AT91SAM7S family?"
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_AT91_PIO_LAYOUT_H <cyg/hal/pio_sam7s.h>"
+ }
}
cdl_option CYGHWR_HAL_ARM_AT91SAM7SE {
@@ -108,6 +111,9 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 {
CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7se32" }
description "
Is the AT91SAM7 device a member of the AT91SAM7SE family?"
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_AT91_PIO_LAYOUT_H <cyg/hal/pio_sam7se.h>"
+ }
}
cdl_option CYGHWR_HAL_ARM_AT91SAM7X {
@@ -117,6 +123,9 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 {
CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x128" }
description "
Is the AT91SAM7 device a member of the AT91SAM7X family?"
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_AT91_PIO_LAYOUT_H <cyg/hal/pio_sam7x.h>"
+ }
}
cdl_option CYGHWR_HAL_ARM_AT91SAM7XC {
diff --git a/packages/hal/arm/at91/phycore/current/cdl/hal_arm_at91_phycore.cdl b/packages/hal/arm/at91/phycore/current/cdl/hal_arm_at91_phycore.cdl
index b9f4966..c71d0a6 100644
--- a/packages/hal/arm/at91/phycore/current/cdl/hal_arm_at91_phycore.cdl
+++ b/packages/hal/arm/at91/phycore/current/cdl/hal_arm_at91_phycore.cdl
@@ -67,7 +67,8 @@ cdl_package CYGPKG_HAL_ARM_AT91_PHYCORE {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_at91.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_at91_phycore.h>"
- puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI\""
+ puts $::cdl_system_header "#define CYGBLD_HAL_AT91_PIO_LAYOUT_H <cyg/hal/pio_m55800a.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"phyCORE AT91M55800A\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
}
diff --git a/packages/hal/arm/at91/var/current/include/pio_default.h b/packages/hal/arm/at91/var/current/include/pio_default.h
new file mode 100644
index 0000000..992ff95
--- /dev/null
+++ b/packages/hal/arm/at91/var/current/include/pio_default.h
@@ -0,0 +1,58 @@
+#if defined (CYGHWR_HAL_ARM_AT91SAM7) || \
+ defined(CYGHWR_HAL_ARM_AT91_M55800A)
+#error "m55800a or sam7 defined, should not be used this pio layout"
+#endif
+
+#define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock
+#define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A
+#define AT91_TC_TIOB0 AT91_PIN(0,0, 2) // Timer #0 signal B
+#define AT91_TC_TCLK1 AT91_PIN(0,0, 3) // Timer #1 clock
+#define AT91_TC_TIOA1 AT91_PIN(0,0, 4) // Timer #1 signal A
+#define AT91_TC_TIOB1 AT91_PIN(0,0, 5) // Timer #1 signal B
+#define AT91_TC_TCLK2 AT91_PIN(0,0, 6) // Timer #2 clock
+#define AT91_TC_TIOA2 AT91_PIN(0,0, 7) // Timer #2 signal A
+#define AT91_TC_TIOB2 AT91_PIN(0,0, 8) // Timer #2 signal B
+#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // IRQ #0
+#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // IRQ #1
+#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // IRQ #2
+#define AT91_INT_FIQ AT91_PIN(0,0,12) // FIQ
+#define AT91_USART_SCK0 AT91_PIN(0,0,13) // Serial port #0 clock
+#define AT91_USART_TXD0 AT91_PIN(0,0,14) // Serial port #0 TxD
+#define AT91_USART_RXD0 AT91_PIN(0,0,15) // Serial port #0 RxD
+#define AT91_USART_SCK1 AT91_PIN(0,0,20) // Serial port #1 clock
+#define AT91_USART_TXD1 AT91_PIN(0,0,21) // Serial port #1 TxD
+#define AT91_USART_RXD1 AT91_PIN(0,0,22) // Serial port #1 RxD
+#define AT91_CLK_MCKO AT91_PIN(0,0,25) // Master clock out
+
+#define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock
+#define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A
+#define AT91_PIO_PSR_TIOB0 0x00000004 // Timer #0 signal B
+#define AT91_PIO_PSR_TCLK1 0x00000008 // Timer #1 clock
+#define AT91_PIO_PSR_TIOA1 0x00000010 // Timer #1 signal A
+#define AT91_PIO_PSR_TIOB1 0x00000020 // Timer #1 signal B
+#define AT91_PIO_PSR_TCLK2 0x00000040 // Timer #2 clock
+#define AT91_PIO_PSR_TIOA2 0x00000080 // Timer #2 signal A
+#define AT91_PIO_PSR_TIOB2 0x00000100 // Timer #2 signal B
+#define AT91_PIO_PSR_IRQ0 0x00000200 // IRQ #0
+#define AT91_PIO_PSR_IRQ1 0x00000400 // IRQ #1
+#define AT91_PIO_PSR_IRQ2 0x00000800 // IRQ #2
+#define AT91_PIO_PSR_FIQ 0x00001000 // FIQ
+#define AT91_PIO_PSR_SCK0 0x00002000 // Serial port #0 clock
+#define AT91_PIO_PSR_TXD0 0x00004000 // Serial port #0 TxD
+#define AT91_PIO_PSR_RXD0 0x00008000 // Serial port #0 RxD
+#define AT91_PIO_PSR_P16 0x00010000 // PIO port #16
+#define AT91_PIO_PSR_P17 0x00020000 // PIO port #17
+#define AT91_PIO_PSR_P18 0x00040000 // PIO port #18
+#define AT91_PIO_PSR_P19 0x00080000 // PIO port #19
+#define AT91_PIO_PSR_SCK1 0x00100000 // Serial port #1 clock
+#define AT91_PIO_PSR_TXD1 0x00200000 // Serial port #1 TxD
+#define AT91_PIO_PSR_RXD1 0x00400000 // Serial port #1 RxD
+#define AT91_PIO_PSR_P23 0x00800000 // PIO port #23
+#define AT91_PIO_PSR_P24 0x01000000 // PIO port #24
+#define AT91_PIO_PSR_MCKO 0x02000000 // Master clock out
+#define AT91_PIO_PSR_NCS2 0x04000000 // Chip select #2
+#define AT91_PIO_PSR_NCS3 0x08000000 // Chip select #3
+#define AT91_PIO_PSR_CS7_A20 0x10000000 // Chip select #7 or A20
+#define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21
+#define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22
+#define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23
diff --git a/packages/hal/arm/at91/var/current/include/pio_m55800a.h b/packages/hal/arm/at91/var/current/include/pio_m55800a.h
new file mode 100644
index 0000000..79782fd
--- /dev/null
+++ b/packages/hal/arm/at91/var/current/include/pio_m55800a.h
@@ -0,0 +1,97 @@
+#ifndef CYGHWR_HAL_ARM_AT91_M55800A
+#error "CYGHWR_HAL_ARM_AT91_M55800A not defined"
+#endif
+
+#define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal
+#define AT91_TC_TIOA3 AT91_PIN(0,0, 1) // Timer 3 Signal A
+#define AT91_TC_TIOB3 AT91_PIN(0,0, 2) // Timer 3 Signal B
+#define AT91_TC_TCLK4 AT91_PIN(0,0, 3) // Timer 4 Clock signal
+#define AT91_TC_TIOA4 AT91_PIN(0,0, 4) // Timer 4 Signal A
+#define AT91_TC_TIOB4 AT91_PIN(0,0, 5) // Timer 4 Signal B
+#define AT91_TC_TCLK5 AT91_PIN(0,0, 6) // Timer 5 Clock signal
+#define AT91_TC_TIOA5 AT91_PIN(0,0, 7) // Timer 5 Signal A
+#define AT91_TC_TIOB5 AT91_PIN(0,0, 8) // Timer 5 Signal B
+#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // External Interrupt 0
+#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // External Interrupt 1
+#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // External Interrupt 2
+#define AT91_INT_IRQ3 AT91_PIN(0,0,12) // External Interrupt 3
+#define AT91_INT_FIQ AT91_PIN(0,0,13) // Fast Interrupt
+#define AT91_USART_SCK0 AT91_PIN(0,0,14) // USART 0 Clock signal
+#define AT91_USART_TXD0 AT91_PIN(0,0,15) // USART 0 transmit data
+#define AT91_USART_RXD0 AT91_PIN(0,0,16) // USART 0 receive data
+#define AT91_USART_SCK1 AT91_PIN(0,0,17) // USART 1 Clock signal
+#define AT91_USART_TXD1 AT91_PIN(0,0,18) // USART 1 transmit data
+#define AT91_USART_RXD1 AT91_PIN(0,0,19) // USART 1 receive data
+#define AT91_USART_SCK2 AT91_PIN(0,0,20) // USART 2 Clock signal
+#define AT91_USART_TXD2 AT91_PIN(0,0,21) // USART 2 transmit data
+#define AT91_USART_RXD2 AT91_PIN(0,0,22) // USART 2 receive data
+#define AT91_SPI_SPCK AT91_PIN(0,0,23) // SPI Clock signal
+#define AT91_SPI_MISO AT91_PIN(0,0,24) // SPI Master In Slave Out
+#define AT91_SPI_MOSI AT91_PIN(0,0,25) // SPI Master Out Slave In
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2
+#define AT91_SPI_NPCS3 AT91_PIN(0,0,29) // SPI Peripheral Chip Select 3
+
+#define AT91_INT_IRQ4 AT91_PIN(1,0, 3) // External Interrupt 4
+#define AT91_INT_IRQ5 AT91_PIN(1,0, 4) // External Interrupt 5
+#define AT91_ADC_AD0TRIG AT91_PIN(1,0, 6) // ADC0 External Trigger
+#define AT91_ADC_AD1TRIG AT91_PIN(1,0, 7) // ADC1 External Trigger
+#define AT91_BOOT_BMS AT91_PIN(1,0,12) // Boot Mode Select
+#define AT91_TC_TCLK0 AT91_PIN(1,0,14) // Timer 0 Clock signal
+#define AT91_TC_TIOA0 AT91_PIN(1,0,15) // Timer 0 Signal A
+#define AT91_TC_TIOB0 AT91_PIN(1,0,16) // Timer 0 Signal B
+#define AT91_TC_TCLK1 AT91_PIN(1,0,17) // Timer 1 Clock signal
+#define AT91_TC_TIOA1 AT91_PIN(1,0,18) // Timer 1 Signal A
+#define AT91_TC_TIOB1 AT91_PIN(1,0,19) // Timer 1 Signal B
+#define AT91_TC_TCLK2 AT91_PIN(1,0,20) // Timer 2 Clock signal
+#define AT91_TC_TIOA2 AT91_PIN(1,0,21) // Timer 2 Signal A
+#define AT91_TC_TIOB2 AT91_PIN(1,0,22) // Timer 2 Signal B
+
+// PIOA
+#define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal
+#define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A
+#define AT91_PIO_PSR_TIOB3 0x00000004 // Timer 3 Signal B
+#define AT91_PIO_PSR_TCLK4 0x00000008 // Timer 4 Clock signal
+#define AT91_PIO_PSR_TIOA4 0x00000010 // Timer 4 Signal A
+#define AT91_PIO_PSR_TIOB4 0x00000020 // Timer 4 Signal B
+#define AT91_PIO_PSR_TCLK5 0x00000040 // Timer 5 Clock signal
+#define AT91_PIO_PSR_TIOA5 0x00000080 // Timer 5 Signal A
+#define AT91_PIO_PSR_TIOB5 0x00000100 // Timer 5 Signal B
+#define AT91_PIO_PSR_IRQ0 0x00000200 // External Interrupt 0
+#define AT91_PIO_PSR_IRQ1 0x00000400 // External Interrupt 1
+#define AT91_PIO_PSR_IRQ2 0x00000800 // External Interrupt 2
+#define AT91_PIO_PSR_IRQ3 0x00001000 // External Interrupt 3
+#define AT91_PIO_PSR_FIQ 0x00002000 // Fast Interrupt
+#define AT91_PIO_PSR_SCK0 0x00004000 // USART 0 Clock signal
+#define AT91_PIO_PSR_TXD0 0x00008000 // USART 0 transmit data
+#define AT91_PIO_PSR_RXD0 0x00010000 // USART 0 receive data
+#define AT91_PIO_PSR_SCK1 0x00020000 // USART 1 Clock signal
+#define AT91_PIO_PSR_TXD1 0x00040000 // USART 1 transmit data
+#define AT91_PIO_PSR_RXD1 0x00080000 // USART 1 receive data
+#define AT91_PIO_PSR_SCK2 0x00100000 // USART 2 Clock signal
+#define AT91_PIO_PSR_TXD2 0x00200000 // USART 2 transmit data
+#define AT91_PIO_PSR_RXD2 0x00400000 // USART 2 receive data
+#define AT91_PIO_PSR_SPCK 0x00800000 // SPI Clock signal
+#define AT91_PIO_PSR_MISO 0x01000000 // SPI Master In Slave Out
+#define AT91_PIO_PSR_MOSI 0x02000000 // SPI Master Out Slave In
+#define AT91_PIO_PSR_NPCS0 0x04000000 // SPI Peripheral Chip Select 0
+#define AT91_PIO_PSR_NPCS1 0x08000000 // SPI Peripheral Chip Select 1
+#define AT91_PIO_PSR_NPCS2 0x10000000 // SPI Peripheral Chip Select 2
+#define AT91_PIO_PSR_NPCS3 0x20000000 // SPI Peripheral Chip Select 3
+
+// PIOB
+#define AT91_PIO_PSR_IRQ4 0x00000008 // External Interrupt 4
+#define AT91_PIO_PSR_IRQ5 0x00000010 // External Interrupt 5
+#define AT91_PIO_PSR_AD0TRIG 0x00000040 // ADC0 External Trigger
+#define AT91_PIO_PSR_AD1TRIG 0x00000080 // ADC1 External Trigger
+#define AT91_PIO_PSR_BMS 0x00040000 // Boot Mode Select
+#define AT91_PIO_PSR_TCLK0 0x00080000 // Timer 0 Clock signal
+#define AT91_PIO_PSR_TIOA0 0x00100000 // Timer 0 Signal A
+#define AT91_PIO_PSR_TIOB0 0x00200000 // Timer 0 Signal B
+#define AT91_PIO_PSR_TCLK1 0x00400000 // Timer 1 Clock signal
+#define AT91_PIO_PSR_TIOA1 0x00800000 // Timer 1 Signal A
+#define AT91_PIO_PSR_TIOB1 0x01000000 // Timer 1 Signal B
+#define AT91_PIO_PSR_TCLK2 0x02000000 // Timer 2 Clock signal
+#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A
+#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B
diff --git a/packages/hal/arm/at91/var/current/include/pio_sam7s.h b/packages/hal/arm/at91/var/current/include/pio_sam7s.h
new file mode 100644
index 0000000..d590ccd
--- /dev/null
+++ b/packages/hal/arm/at91/var/current/include/pio_sam7s.h
@@ -0,0 +1,145 @@
+#ifndef CYGHWR_HAL_ARM_AT91SAM7S
+#error "CYGHWR_HAL_ARM_AT91SAM7S not defined"
+#endif
+
+#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
+#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
+#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
+#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
+#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
+#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
+#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
+#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
+#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
+#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
+#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
+#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
+#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
+#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
+#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
+#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
+#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
+#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
+#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
+#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
+#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
+#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
+#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
+#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
+#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
+#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
+#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
+#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
+#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
+#endif
+
+#define AT91_TC_TIOA0 AT91_PIN(0,1, 0) // Timer/Counter 0 IO Line A
+#define AT91_TC_TIOB0 AT91_PIN(0,1, 1) // Timer/Counter 0 IO Line B
+#define AT91_USART_SCK0 AT91_PIN(0,1, 2) // USART 0 Serial Clock
+#define AT91_SPI_NPCS3 AT91_PIN(0,1, 3) // SPI Chip Select 3
+#define AT91_TC_TCLK0 AT91_PIN(0,1, 4) // Timer/Counter 0 Clock Input
+#define AT91_SPI_NPCS3X AT91_PIN(0,1, 5) // SPI Chip Select 3 (again)
+#define AT91_PCK_PCK0 AT91_PIN(0,1, 6) // Programmable Clock Output 0
+#define AT91_PWM_PWM3 AT91_PIN(0,1, 7) // Pulse Width Modulation #3
+#define AT91_ADC_ADTRG AT91_PIN(0,1, 8) // ADC Trigger
+#define AT91_SPI_NPCS1X AT91_PIN(0,1, 9) // SPI Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(0,1,10) // SPI Chip Select 2
+#define AT91_PWM_PWM0X AT91_PIN(0,1,11) // Pulse Width Modulation #0
+#define AT91_PIO_PWM_PWM1X AT91_PIN(0,1,12) // Pulse Width Modulation #1
+#define AT91_PIO_PWM_PWM2X AT91_PIN(0,1,13) // Pulse Width Modulation #2
+#define AT91_PIO_PWM_PWM4X AT91_PIN(0,1,14) // Pulse Width Modulation #4
+#define AT91_TC_TIOA1 AT91_PIN(0,1,15) // Timer/Counter 1 IO Line A
+#define AT91_TC_TIOB1 AT91_PIN(0,1,16) // Timer/Counter 1 IO Line B
+#define AT91_PCK_PCK1 AT91_PIN(0,1,17) // Programmable Clock Output 1
+#define AT91_PCK_PCK2 AT91_PIN(0,1,18) // Programmable Clock Output 2
+#define AT91_INT_FIQ AT91_PIN(0,1,19) // Fast Interrupt Request
+#define AT91_INT_IRQ0 AT91_PIN(0,1,20) // Interrupt Request 0
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_PCK_PCK1X AT91_PIN(0,1,21) // Programmable Clock Output 1
+#define AT91_SPI_NPCS3XX AT91_PIN(0,1,22) // SPI Chip Select 3 (yet again)
+#define AT91_PWM_PWM0XX AT91_PIN(0,1,23) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1XX AT91_PIN(0,1,24) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2XX AT91_PIN(0,1,25) // Pulse Width Modulation 2
+#define AT91_TC_TIOA2 AT91_PIN(0,1,26) // Timer/Counter 2 IO Line A
+#define AT91_TC_TIOB2 AT91_PIN(0,1,27) // Timer/Counter 2 IO Line B
+#define AT91_TC_TCLK1 AT91_PIN(0,1,28) // External Clock Input 1
+#define AT91_TC_TCLK2 AT91_PIN(0,1,29) // External Clock Input 2
+#define AT91_SPI_NPCS2X AT91_PIN(0,1,30) // SPI Chip Select 2 (again)
+#define AT91_PCK_PCK2X AT91_PIN(0,1,31) // Programmable Clock Output 2
+#endif //!defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+
+// PIO Peripheral A
+#define AT91_PIO_PSR_PWM0 0x00000001 // Pulse Width Modulation 0
+#define AT91_PIO_PSR_PWM1 0x00000002 // Pulse Width Modulation 1
+#define AT91_PIO_PSR_PWM2 0x00000004 // Pulse Width Modulation 2
+#define AT91_PIO_PSR_TWD 0x00000008 // Two Wire Data
+#define AT91_PIO_PSR_TWCK 0x00000010 // Two Wire Clock
+#define AT91_PIO_PSR_RXD0 0x00000020 // USART 0 Receive Data
+#define AT91_PIO_PSR_TXD0 0x00000040 // USART 0 Transmit Data
+#define AT91_PIO_PSR_RTS0 0x00000080 // USART 0 Ready To Send
+#define AT91_PIO_PSR_CTS0 0x00000100 // USART 0 Clear To Send
+#define AT91_PIO_PSR_DRXD 0x00000200 // Debug UART Receive
+#define AT91_PIO_PSR_DTXD 0x00000400 // Debug UART Transmit
+#define AT91_PIO_PSR_NPCS0 0x00000800 // SPI Chip Select 0
+#define AT91_PIO_PSR_MISO 0x00001000 // SPI Input
+#define AT91_PIO_PSR_MOSI 0x00002000 // SPI Output
+#define AT91_PIO_PSR_SPCK 0x00004000 // SPI clock
+#define AT91_PIO_PSR_TF 0x00008000 // S2C Transmit Frame Sync
+#define AT91_PIO_PSR_TK 0x00010000 // S2C Transmit Clock
+#define AT91_PIO_PSR_TD 0x00020000 // S2C Transmit Data
+#define AT91_PIO_PSR_RD 0x00040000 // S2C Receive Data
+#define AT91_PIO_PSR_RK 0x00080000 // S2C Receive Clock
+#define AT91_PIO_PSR_RF 0x00100000 // S2C Receive Frame Sync
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_PIO_PSR_RXD1 0x00200000 // USART 1 Receive Data
+#define AT91_PIO_PSR_TXD1 0x00400000 // USART 1 Transmit Data
+#define AT91_PIO_PSR_SCK1 0x00800000 // USART 1 Serial Clock
+#define AT91_PIO_PSR_RTS1 0x01000000 // USART 1 Ready To Send
+#define AT91_PIO_PSR_CTS1 0x02000000 // USART 1 Clear To Send
+#define AT91_PIO_PSR_DCD1 0x04000000 // USART 1 Data Carrier Detect
+#define AT91_PIO_PSR_DTR1 0x08000000 // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_DSR1 0x10000000 // USART 1 Data Set Ready
+#define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator
+#define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1
+#define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1
+#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+
+// PIO Peripheral B
+#define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A
+#define AT91_PIO_PSR_TIOB0 0x00000002 // Timer/Counter 0 IO Line B
+#define AT91_PIO_PSR_SCK0 0x00000004 // USART 0 Serial Clock
+#define AT91_PIO_PSR_NPCS3 0x00000008 // SPI Chip Select 3
+#define AT91_PIO_PSR_TCLK0 0x00000010 // Timer/Counter 0 Clock Input
+#define AT91_PIO_PSR_NPCS3X 0x00000020 // SPI Chip Select 3 (again)
+#define AT91_PIO_PSR_PCK0 0x00000040 // Programmable Clock Output 0
+#define AT91_PIO_PSR_PWM3 0x00000080 // Pulse Width Modulation #3
+#define AT91_PIO_PSR_ADTRG 0x00000100 // ADC Trigger
+#define AT91_PIO_PSR_NPCS1X 0x00000200 // SPI Chip Select 1 (again)
+#define AT91_PIO_PSR_NPCS2 0x00000400 // SPI Chip Select 2
+#define AT91_PIO_PSR_PWMOX 0x00000800 // Pulse Width Modulation #0 (again)
+#define AT91_PIO_PSR_PWM1X 0x00001000 // Pulse Width Modulation #1 (again)
+#define AT91_PIO_PSR_PWM2X 0x00002000 // Pulse Width Modulation #2 (again)
+#define AT91_PIO_PSR_PWM3X 0x00004000 // Pulse Width Modulation #4 (again)
+#define AT91_PIO_PSR_TIOA1 0x00008000 // Timer/Counter 1 IO Line A
+#define AT91_PIO_PSR_TIOB1 0x00010000 // Timer/Counter 1 IO Line B
+#define AT91_PIO_PSR_PCK1 0x00020000 // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2 0x00040000 // Programmable Clock Output 2
+#define AT91_PIO_PSR_FIQ 0x00080000 // Fast Interrupt Request
+#define AT91_PIO_PSR_IRQ0 0x00100000 // Interrupt Request 0
+#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
+#define AT91_PIO_PSR_PCK1X 0x00200000 // Programmable Clock Output 1(again)
+#define AT91_PIO_PSR_NPCS3XX 0x00400000 // SPI Chip Select 3 (yet again)
+#define AT91_PIO_PSR_PWMOXX 0x00800000 // Pulse Width Modulation #0 (again)
+#define AT91_PIO_PSR_PWM1XX 0x01000000 // Pulse Width Modulation #1 (again)
+#define AT91_PIO_PSR_PWM2XX 0x02000000 // Pulse Width Modulation #2 (again)
+#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer/Counter 2 IO Line A
+#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer/Counter 2 IO Line B
+#define AT91_PIO_PSR_TCLK1 0x10000000 // External Clock Input 1
+#define AT91_PIO_PSR_TCLK2 0x20000000 // External Clock Input 2
+#define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again)
+#define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again)
+#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
diff --git a/packages/hal/arm/at91/var/current/include/pio_sam7se.h b/packages/hal/arm/at91/var/current/include/pio_sam7se.h
new file mode 100644
index 0000000..b7daef1
--- /dev/null
+++ b/packages/hal/arm/at91/var/current/include/pio_sam7se.h
@@ -0,0 +1,393 @@
+#ifndef CYGHWR_HAL_ARM_AT91SAM7SE
+#error "CYGHWR_HAL_ARM_AT91SAM7SE not defined"
+#endif
+
+//PIO Controller A Peripheral A
+#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
+#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
+#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
+#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
+#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
+#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
+#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
+#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
+#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
+#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
+#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
+#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
+#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
+#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
+#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
+#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
+#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
+#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
+#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
+#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
+#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
+#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
+#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
+#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
+#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
+#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
+#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
+#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
+#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
+#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
+
+//PIO Controller A Peripheral B
+#define AT91_EBI_A0_NBS0 AT91_PIN(0,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
+#define AT91_EBI_A1_NBS2 AT91_PIN(0,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
+#define AT91_EBI_A2 AT91_PIN(0,1, 2) // EBI: Addr 2
+#define AT91_EBI_A3 AT91_PIN(0,1, 3) // EBI: Addr 3
+#define AT91_EBI_A4 AT91_PIN(0,1, 4) // EBI: Addr 4
+#define AT91_EBI_A5 AT91_PIN(0,1, 5) // EBI: Addr 5
+#define AT91_EBI_A6 AT91_PIN(0,1, 6) // EBI: Addr 6
+#define AT91_EBI_A7 AT91_PIN(0,1, 7) // EBI: Addr 7
+#define AT91_EBI_A8 AT91_PIN(0,1, 8) // EBI: Addr 8
+#define AT91_EBI_A9 AT91_PIN(0,1, 9) // EBI: Addr 9
+#define AT91_EBI_A10 AT91_PIN(0,1,10) // EBI: Addr 10
+#define AT91_EBI_A11 AT91_PIN(0,1,11) // EBI: Addr 11
+#define AT91_EBI_A12 AT91_PIN(0,1,12) // EBI: Addr 12
+#define AT91_EBI_A13 AT91_PIN(0,1,13) // EBI: Addr 13
+#define AT91_EBI_A14 AT91_PIN(0,1,14) // EBI: Addr 14
+#define AT91_EBI_A15 AT91_PIN(0,1,15) // EBI: Addr 15
+#define AT91_EBI_A16_BA0 AT91_PIN(0,1,16) // EBI: Addr 16 / SDRAM Bank Sel 0
+#define AT91_EBI_A17_BA1 AT91_PIN(0,1,17) // EBI: Addr 17 / SDRAM Bank Sel 1
+#define AT91_EBI_NBS3_CFIOW AT91_PIN(0,1,18) // EBI: SDRAM Byte Mask 3 /
+ // CompactFlash I/O Write Signal
+#define AT91_EBI_NCS4_CFCS0 AT91_PIN(0,1,19) // EBI: Chip Select 4 /
+ // CompactFlash Chip Select 0
+#define AT91_EBI_NCS2_CFCS1 AT91_PIN(0,1,20) // EBI: Chip Select 2 /
+ // CompactFlash Chip Select 1
+#define AT91_EBI_NCS6_CFCE2 AT91_PIN(0,1,21) // EBI: Chip Select 6 /
+ // CompactFlash Chip Enable 2
+#define AT91_EBI_NCS5_CFCE1 AT91_PIN(0,1,22) // EBI: Chip Select 5 /
+ // CompactFlash Chip Enable 1
+#define AT91_EBI_NWR1_NBS1_CFIOR \
+ AT91_PIN(0,1,23) // EBI: SMC Write 1 /
+ // SDRAM Byte Mask 1 /
+ // CompactFlash I/O Read Signal
+#define AT91_EBI_SDA10 AT91_PIN(0,1,24) // EBI: SDRAM Address 10
+#define AT91_EBI_SDCKE AT91_PIN(0,1,25) // EBI: SDRAM Clock Enable
+#define AT91_EBI_NCS1_SDCS AT91_PIN(0,1,26) // EBI: Chip Select 1 /
+ // SDRAM Controller Chip Select
+#define AT91_EBI_SDWE AT91_PIN(0,1,27) // EBI: SDRAM Write Enable
+#define AT91_EBI_CAS AT91_PIN(0,1,28) // EBI: SDRAM Column Signal
+#define AT91_EBI_RAS AT91_PIN(0,1,29) // EBI: SDRAM Row Signal
+#define AT91_EBI_D30 AT91_PIN(0,1,30) // EBI: Data 30
+#define AT91_EBI_D31 AT91_PIN(0,1,31) // EBI: Data 31
+
+//PIO Controller A Peripheral A
+#define AT91_PIO_PSR_PWM0 (1<< 0) // Pulse Width Modulation 0
+#define AT91_PIO_PSR_PWM1 (1<< 1) // Pulse Width Modulation 1
+#define AT91_PIO_PSR_PWM2 (1<< 2) // Pulse Width Modulation 2
+#define AT91_PIO_PSR_TWD (1<< 3) // Two Wire Data
+#define AT91_PIO_PSR_TWCK (1<< 4) // Two Wire Clock
+#define AT91_PIO_PSR_RXD0 (1<< 5) // USART 0 Receive Data
+#define AT91_PIO_PSR_TXD0 (1<< 6) // USART 0 Transmit Data
+#define AT91_PIO_PSR_RTS0 (1<< 7) // USART 0 Ready To Send
+#define AT91_PIO_PSR_CTS0 (1<< 8) // USART 0 Clear To Send
+#define AT91_PIO_PSR_DRXD (1<< 9) // Debug UART Receive
+#define AT91_PIO_PSR_DTXD (1<<10) // Debug UART Transmit
+#define AT91_PIO_PSR_NPCS0 (1<<11) // SPI Chip Select 0
+#define AT91_PIO_PSR_MISO (1<<12) // SPI Input
+#define AT91_PIO_PSR_MOSI (1<<13) // SPI Output
+#define AT91_PIO_PSR_SPCK (1<<14) // SPI clock
+#define AT91_PIO_PSR_TF (1<<15) // S2C Transmit Frame Sync
+#define AT91_PIO_PSR_TK (1<<16) // S2C Transmit Clock
+#define AT91_PIO_PSR_TD (1<<17) // S2C Transmit Data
+#define AT91_PIO_PSR_RD (1<<18) // S2C Receive Data
+#define AT91_PIO_PSR_RK (1<<19) // S2C Receive Clock
+#define AT91_PIO_PSR_RF (1<<20) // S2C Receive Frame Sync
+#define AT91_PIO_PSR_RXD1 (1<<21) // USART 1 Receive Data
+#define AT91_PIO_PSR_TXD1 (1<<22) // USART 1 Transmit Data
+#define AT91_PIO_PSR_SCK1 (1<<23) // USART 1 Serial Clock
+#define AT91_PIO_PSR_RTS1 (1<<24) // USART 1 Ready To Send
+#define AT91_PIO_PSR_CTS1 (1<<25) // USART 1 Clear To Send
+#define AT91_PIO_PSR_DVD1 (1<<26) // USART 1 Data Carrier Detect
+#define AT91_PIO_PSR_DTR1 (1<<27) // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_DSR1 (1<<28) // USART 1 Data Set Ready
+#define AT91_PIO_PSR_RI1 (1<<29) // USART 2 Ring Indicator
+#define AT91_PIO_PSR_IRQ1 (1<<30) // Interrupt Request 1
+#define AT91_PIO_PSR_NPCS1 (1<<31) // SPI Chip Select 1
+
+//PIO Controller A Peripheral B
+#define AT91_PIO_PSR_A0_NBS0 (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
+#define AT91_PIO_PSR_A1_NBS2 (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
+#define AT91_PIO_PSR_A2 (1<< 2) // EBI: Address 2
+#define AT91_PIO_PSR_A3 (1<< 3) // EBI: Address 3
+#define AT91_PIO_PSR_A4 (1<< 4) // EBI: Address 4
+#define AT91_PIO_PSR_A5 (1<< 5) // EBI: Address 5
+#define AT91_PIO_PSR_A6 (1<< 6) // EBI: Address 6
+#define AT91_PIO_PSR_A7 (1<< 7) // EBI: Address 7
+#define AT91_PIO_PSR_A8 (1<< 8) // EBI: Address 8
+#define AT91_PIO_PSR_A9 (1<< 9) // EBI: Address 9
+#define AT91_PIO_PSR_A10 (1<<10) // EBI: Address 10
+#define AT91_PIO_PSR_A11 (1<<11) // EBI: Address 11
+#define AT91_PIO_PSR_A12 (1<<12) // EBI: Address 12
+#define AT91_PIO_PSR_A13 (1<<13) // EBI: Address 13
+#define AT91_PIO_PSR_A14 (1<<14) // EBI: Address 14
+#define AT91_PIO_PSR_A15 (1<<15) // EBI: Address 15
+#define AT91_PIO_PSR_A16_BA0 (1<<16) // EBI: Address 16 / SDRAM Bank Sel 0
+#define AT91_PIO_PSR_A17_BA1 (1<<17) // EBI: Address 17 / SDRAM Bank Sel 1
+#define AT91_PIO_PSR_NBS3_CFIOW (1<<18) // EBI: SDRAM Byte Mask 3 /
+ // CompactFlash I/O Write Signal
+#define AT91_PIO_PSR_NCS4_CFCS0 (1<<19) // EBI: Chip Select 4 /
+ // CompactFlash Chip Select 0
+#define AT91_PIO_PSR_NCS2_CFCS1 (1<<20) // EBI: Chip Select 2 /
+ // CompactFlash Chip Select 1
+#define AT91_PIO_PSR_NCS6_CFCE2 (1<<21) // EBI: Chip Select 6 /
+ // CompactFlash Chip Enable 2
+#define AT91_PIO_PSR_NCS5_CFCE1 (1<<22) // EBI: Chip Select 5 /
+ // CompactFlash Chip Enable 1
+#define AT91_PIO_PSR_NWR1_NBS1_CFIOR \
+ (1<<23) // EBI: Write 1 / SDRAM Byte Mask 1 /
+ // CompactFlash I/O Read Signal
+#define AT91_PIO_PSR_SDA10 (1<<24) // EBI: SDRAM Address 10
+#define AT91_PIO_PSR_SDCKE (1<<25) // EBI: SDRAM Clock Enable
+#define AT91_PIO_PSR_NCS1_SDCS (1<<26) // EBI: Chip Select 1 /
+ // SDRAM Controller Chip Select
+#define AT91_PIO_PSR_SDWE (1<<27) // EBI: SDRAM Write Enable
+#define AT91_PIO_PSR_CAS (1<<28) // EBI: SDRAM Column Signal
+#define AT91_PIO_PSR_RAS (1<<29) // EBI: SDRAM Row Signal
+#define AT91_PIO_PSR_D30 (1<<30) // EBI: Data 30
+#define AT91_PIO_PSR_D31 (1<<31) // EBI: Data 31
+
+//PIO Controller B Peripheral A
+#define AT91_TC_TIOA0 AT91_PIN(1,0, 0) // Timer/Counter 0 IO Line A
+#define AT91_TC_TIOB0 AT91_PIN(1,0, 1) // Timer/Counter 0 IO Line B
+#define AT91_USART_SCK0 AT91_PIN(1,0, 2) // USART 0 Serial Clock
+#define AT91_SPI_NPCS3 AT91_PIN(1,0, 3) // SPI Chip Select 3
+#define AT91_TC_TCLK0 AT91_PIN(1,0, 4) // Timer/Counter 0 Clock Input
+#define AT91_SPI_NPCS3X AT91_PIN(1,0, 5) // SPI Chip Select 3 (again)
+#define AT91_PCK_PCK0 AT91_PIN(1,0, 6) // Programmable Clock Output 0
+#define AT91_PWM_PWM3 AT91_PIN(1,0, 7) // Pulse Width Modulation #3
+#define AT91_ADC_ADTRG AT91_PIN(1,0, 8) // ADC Trigger
+#define AT91_SPI_NPCS1X AT91_PIN(1,0, 9) // SPI Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(1,0,10) // SPI Chip Select 2
+#define AT91_PWM_PWM0X AT91_PIN(1,0,11) // Pulse Width Modulation #0
+#define AT91_PIO_PWM_PWM1X AT91_PIN(1,0,12) // Pulse Width Modulation #1
+#define AT91_PIO_PWM_PWM2X AT91_PIN(1,0,13) // Pulse Width Modulation #2
+#define AT91_PIO_PWM_PWM4X AT91_PIN(1,0,14) // Pulse Width Modulation #4
+#define AT91_TC_TIOA1 AT91_PIN(1,0,15) // Timer/Counter 1 IO Line A
+#define AT91_TC_TIOB1 AT91_PIN(1,0,16) // Timer/Counter 1 IO Line B
+#define AT91_PCK_PCK1 AT91_PIN(1,0,17) // Programmable Clock Output 1
+#define AT91_PCK_PCK2 AT91_PIN(1,0,18) // Programmable Clock Output 2
+#define AT91_INT_FIQ AT91_PIN(1,0,19) // Fast Interrupt Request
+#define AT91_INT_IRQ0 AT91_PIN(1,0,20) // Interrupt Request 0
+#define AT91_PCK_PCK1X AT91_PIN(1,0,21) // Programmable Clock Output 1
+#define AT91_SPI_NPCS3XX AT91_PIN(1,0,22) // SPI Chip Select 3 (yet again)
+#define AT91_PWM_PWM0XX AT91_PIN(1,0,23) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1XX AT91_PIN(1,0,24) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2XX AT91_PIN(1,0,25) // Pulse Width Modulation 2
+#define AT91_TC_TIOA2 AT91_PIN(1,0,26) // Timer/Counter 2 IO Line A
+#define AT91_TC_TIOB2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line B
+#define AT91_TC_TCLK1 AT91_PIN(1,0,28) // External Clock Input 1
+#define AT91_TC_TCLK2 AT91_PIN(1,0,29) // External Clock Input 2
+#define AT91_SPI_NPCS2X AT91_PIN(1,0,30) // SPI Chip Select 2 (again)
+#define AT91_PCK_PCK2X AT91_PIN(1,0,31) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_EBI_A0_NBS0X AT91_PIN(1,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
+#define AT91_EBI_A1_NBS2X AT91_PIN(1,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
+#define AT91_EBI_A2X AT91_PIN(1,1, 2) // EBI: Addr 2
+#define AT91_EBI_A3X AT91_PIN(1,1, 3) // EBI: Addr 3
+#define AT91_EBI_A4X AT91_PIN(1,1, 4) // EBI: Addr 4
+#define AT91_EBI_A5X AT91_PIN(1,1, 5) // EBI: Addr 5
+#define AT91_EBI_A6X AT91_PIN(1,1, 6) // EBI: Addr 6
+#define AT91_EBI_A7X AT91_PIN(1,1, 7) // EBI: Addr 7
+#define AT91_EBI_A8X AT91_PIN(1,1, 8) // EBI: Addr 8
+#define AT91_EBI_A9X AT91_PIN(1,1, 9) // EBI: Addr 9
+#define AT91_EBI_A10X AT91_PIN(1,1,10) // EBI: Addr 10
+#define AT91_EBI_A11X AT91_PIN(1,1,11) // EBI: Addr 11
+#define AT91_EBI_A12X AT91_PIN(1,1,12) // EBI: Addr 12
+#define AT91_EBI_A13X AT91_PIN(1,1,13) // EBI: Addr 13
+#define AT91_EBI_A14X AT91_PIN(1,1,14) // EBI: Addr 14
+#define AT91_EBI_A15X AT91_PIN(1,1,15) // EBI: Addr 15
+#define AT91_EBI_A16_BA0X AT91_PIN(1,1,16) // EBI: Addr 16 /
+ // SDRAM Bank Select 0
+#define AT91_EBI_A17_BA1X AT91_PIN(1,1,17) // EBI: Addr 17 /
+ // SDRAM Bank Select 1
+#define AT91_EBI_D16 AT91_PIN(1,1,18) // EBI: Data 16
+#define AT91_EBI_D17 AT91_PIN(1,1,19) // EBI: Data 17
+#define AT91_EBI_D18 AT91_PIN(1,1,20) // EBI: Data 18
+#define AT91_EBI_D19 AT91_PIN(1,1,21) // EBI: Data 19
+#define AT91_EBI_D20 AT91_PIN(1,1,22) // EBI: Data 20
+#define AT91_EBI_D21 AT91_PIN(1,1,23) // EBI: Data 21
+#define AT91_EBI_D22 AT91_PIN(1,1,24) // EBI: Data 22
+#define AT91_EBI_D23 AT91_PIN(1,1,25) // EBI: Data 23
+#define AT91_EBI_D24 AT91_PIN(1,1,26) // EBI: Data 24
+#define AT91_EBI_D25 AT91_PIN(1,1,27) // EBI: Data 25
+#define AT91_EBI_D26 AT91_PIN(1,1,28) // EBI: Data 26
+#define AT91_EBI_D27 AT91_PIN(1,1,29) // EBI: Data 27
+#define AT91_EBI_D28 AT91_PIN(1,1,30) // EBI: Data 28
+#define AT91_EBI_D29 AT91_PIN(1,1,31) // EBI: Data 29
+
+//PIO Controller B Peripheral A
+#define AT91_PIO_PSR_TIOA0 (1<< 0) // Timer/Counter 0 IO Line A
+#define AT91_PIO_PSR_TIOB0 (1<< 1) // Timer/Counter 0 IO Line B
+#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
+#define AT91_PIO_PSR_NPCS3 (1<< 3) // SPI Chip Select 3
+#define AT91_PIO_PSR_TCLK0 (1<< 4) // Timer/Counter 0 Clock Input
+#define AT91_PIO_PSR_NPCS3X (1<< 5) // SPI Chip Select 3 (again)
+#define AT91_PIO_PSR_PCK0 (1<< 6) // Programmable Clock Output 0
+#define AT91_PIO_PSR_PWM3 (1<< 7) // Pulse Width Modulation #3
+#define AT91_PIO_PSR_ADTRG (1<< 8) // ADC Trigger
+#define AT91_PIO_PSR_NPCS1X (1<< 9) // SPI Chip Select 1
+#define AT91_PIO_PSR_NPCS2 (1<<10) // SPI Chip Select 2
+#define AT91_PIO_PSR_PWM0X (1<<11) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1X (1<<12) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2X (1<<13) // Pulse Width Modulation #2
+#define AT91_PIO_PSR_PWM4X (1<<14) // Pulse Width Modulation #4
+#define AT91_PIO_PSR_TIOA1 (1<<15) // Timer/Counter 1 IO Line A
+#define AT91_PIO_PSR_TIOB1 (1<<16) // Timer/Counter 1 IO Line B
+#define AT91_PIO_PSR_PCK1 (1<<17) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2 (1<<18) // Programmable Clock Output 2
+#define AT91_PIO_PSR_FIQ (1<<19) // Fast Interrupt Request
+#define AT91_PIO_PSR_IRQ0 (1<<20) // Interrupt Request 0
+#define AT91_PIO_PSR_PCK1X (1<<21) // Programmable Clock Output 1
+#define AT91_PIO_PSR_NPCS3XX (1<<22) // SPI Chip Select 3 (yet again)
+#define AT91_PIO_PSR_PWM0XX (1<<23) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1XX (1<<24) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2XX (1<<25) // Pulse Width Modulation 2
+#define AT91_PIO_PSR_TIOA2 (1<<26) // Timer/Counter 2 IO Line A
+#define AT91_PIO_PSR_TIOB2 (1<<27) // Timer/Counter 2 IO Line B
+#define AT91_PIO_PSR_TCLK1 (1<<28) // External Clock Input 1
+#define AT91_PIO_PSR_TCLK2 (1<<29) // External Clock Input 2
+#define AT91_PIO_PSR_NPCS2X (1<<30) // SPI Chip Select 2 (again)
+#define AT91_PIO_PSR_PCK2X (1<<31) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_PIO_PSR_NBS0X (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
+#define AT91_PIO_PSR_NBS2X (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
+#define AT91_PIO_PSR_A2X (1<< 2) // EBI: Address 2
+#define AT91_PIO_PSR_A3X (1<< 3) // EBI: Address 3
+#define AT91_PIO_PSR_A4X (1<< 4) // EBI: Address 4
+#define AT91_PIO_PSR_A5X (1<< 5) // EBI: Address 5
+#define AT91_PIO_PSR_A6X (1<< 6) // EBI: Address 6
+#define AT91_PIO_PSR_A7X (1<< 7) // EBI: Address 7
+#define AT91_PIO_PSR_A8X (1<< 8) // EBI: Address 8
+#define AT91_PIO_PSR_A9X (1<< 9) // EBI: Address 9
+#define AT91_PIO_PSR_A10X (1<<10) // EBI: Address 10
+#define AT91_PIO_PSR_A11X (1<<11) // EBI: Address 11
+#define AT91_PIO_PSR_A12X (1<<12) // EBI: Address 12
+#define AT91_PIO_PSR_A13X (1<<13) // EBI: Address 13
+#define AT91_PIO_PSR_A14X (1<<14) // EBI: Address 14
+#define AT91_PIO_PSR_A15X (1<<15) // EBI: Address 15
+#define AT91_PIO_PSR_BA0X (1<<16) // EBI: Address 16 /
+ // SDRAM Bank Select 0
+#define AT91_PIO_PSR_BA1X (1<<17) // EBI: Address 17 /
+ // SDRAM Bank Select 1
+#define AT91_PIO_PSR_D16 (1<<18) // EBI: Data 16
+#define AT91_PIO_PSR_D17 (1<<19) // EBI: Data 17
+#define AT91_PIO_PSR_D18 (1<<20) // EBI: Data 18
+#define AT91_PIO_PSR_D19 (1<<21) // EBI: Data 19
+#define AT91_PIO_PSR_D20 (1<<22) // EBI: Data 20
+#define AT91_PIO_PSR_D21 (1<<23) // EBI: Data 21
+#define AT91_PIO_PSR_D22 (1<<24) // EBI: Data 22
+#define AT91_PIO_PSR_D23 (1<<25) // EBI: Data 23
+#define AT91_PIO_PSR_D24 (1<<26) // EBI: Data 24
+#define AT91_PIO_PSR_D25 (1<<27) // EBI: Data 25
+#define AT91_PIO_PSR_D26 (1<<28) // EBI: Data 26
+#define AT91_PIO_PSR_D27 (1<<29) // EBI: Data 27
+#define AT91_PIO_PSR_D28 (1<<30) // EBI: Data 28
+#define AT91_PIO_PSR_D29 (1<<31) // EBI: Data 29
+
+//PIO Controller C Peripheral A
+#define AT91_EBI_D0 AT91_PIN(2,0, 0) // EBI: Data 0
+#define AT91_EBI_D1 AT91_PIN(2,0, 1) // EBI: Data 1
+#define AT91_EBI_D2 AT91_PIN(2,0, 2) // EBI: Data 2
+#define AT91_EBI_D3 AT91_PIN(2,0, 3) // EBI: Data 3
+#define AT91_EBI_D4 AT91_PIN(2,0, 4) // EBI: Data 4
+#define AT91_EBI_D5 AT91_PIN(2,0, 5) // EBI: Data 5
+#define AT91_EBI_D6 AT91_PIN(2,0, 6) // EBI: Data 6
+#define AT91_EBI_D7 AT91_PIN(2,0, 7) // EBI: Data 7
+#define AT91_EBI_D8 AT91_PIN(2,0, 8) // EBI: Data 8
+#define AT91_EBI_D9 AT91_PIN(2,0, 9) // EBI: Data 9
+#define AT91_EBI_D10 AT91_PIN(2,0,10) // EBI: Data 10
+#define AT91_EBI_D11 AT91_PIN(2,0,11) // EBI: Data 11
+#define AT91_EBI_D12 AT91_PIN(2,0,12) // EBI: Data 12
+#define AT91_EBI_D13 AT91_PIN(2,0,13) // EBI: Data 13
+#define AT91_EBI_D14 AT91_PIN(2,0,14) // EBI: Data 14
+#define AT91_EBI_D15 AT91_PIN(2,0,15) // EBI: Data 15
+#define AT91_EBI_A18 AT91_PIN(2,0,16) // EBI: Address 18
+#define AT91_EBI_A19 AT91_PIN(2,0,17) // EBI: Address 19
+#define AT91_EBI_A20 AT91_PIN(2,0,18) // EBI: Address 20
+#define AT91_EBI_A21_NANDALE \
+ AT91_PIN(2,0,19) // EBI: Address 21 /
+ // NAND Flash Address Line Enable
+#define AT91_EBI_A22_REG_NANDCLE \
+ AT91_PIN(2,0,20) // EBI: Address 22 /
+ // CompactFlash REG Signal /
+ // NAND Flash Command Line Enable
+#define AT91_EBI_CFNRW AT91_PIN(2,0,23) // EBI: CF Read Not Write Signal
+
+//PIO Controller C Peripheral B
+#define AT91_USART_RTS1X AT91_PIN(2,1, 8) // USART 1 Ready To Send
+#define AT91_USART_DTR1X AT91_PIN(2,1, 9) // USART 1 Data Terminal Ready
+#define AT91_PCK_PCK0X AT91_PIN(2,1,10) // Programmable Clock Output 0
+#define AT91_PCK_PCK1XX AT91_PIN(2,1,11) // Programmable Clock Output 1
+#define AT91_PCK_PCK2XX AT91_PIN(2,1,12) // Programmable Clock Output 2
+#define AT91_SPI_NPCS1XX AT91_PIN(2,1,14) // SPI Chip Select 1
+#define AT91_EBI_NCS3_NANDCS \
+ AT91_PIN(2,1,15) // EBI: Chip Select 3 /
+ // NAND Flash Chip Select
+#define AT91_EBI_NWAIT AT91_PIN(2,1,16) // EBI: External Wait Signal
+#define AT91_EBI_NANDOE AT91_PIN(2,1,17) // EBI: NAND Flash Output Enable
+#define AT91_EBI_NANDWE AT91_PIN(2,1,18) // EBI: NAND Flash Write Enable
+#define AT91_EBI_NCS7 AT91_PIN(2,1,20) // EBI: Chip Select 7
+#define AT91_EBI_NWR0_NWE_CFWE \
+ AT91_PIN(2,1,21) // EBI: Write 0 /
+ // SMC Write Enable /
+ // CompactFlash Write Enable
+#define AT91_EBI_NRD_CFOE AT91_PIN(2,1,22) // EBI: SMC Read Enable /
+ // CompactFlash Output Enable
+#define AT91_EBI_NCS0 AT91_PIN(2,1,23) // EBI: Chip Select 0
+
+//PIO Controller C Peripheral A
+#define AT91_PIO_PSR_D0 (1<< 0) // EBI: Data 0
+#define AT91_PIO_PSR_D1 (1<< 1) // EBI: Data 1
+#define AT91_PIO_PSR_D2 (1<< 2) // EBI: Data 2
+#define AT91_PIO_PSR_D3 (1<< 3) // EBI: Data 3
+#define AT91_PIO_PSR_D4 (1<< 4) // EBI: Data 4
+#define AT91_PIO_PSR_D5 (1<< 5) // EBI: Data 5
+#define AT91_PIO_PSR_D6 (1<< 6) // EBI: Data 6
+#define AT91_PIO_PSR_D7 (1<< 7) // EBI: Data 7
+#define AT91_PIO_PSR_D8 (1<< 8) // EBI: Data 8
+#define AT91_PIO_PSR_D9 (1<< 9) // EBI: Data 9
+#define AT91_PIO_PSR_D10 (1<<10) // EBI: Data 10
+#define AT91_PIO_PSR_D11 (1<<11) // EBI: Data 11
+#define AT91_PIO_PSR_D12 (1<<12) // EBI: Data 12
+#define AT91_PIO_PSR_D13 (1<<13) // EBI: Data 13
+#define AT91_PIO_PSR_D14 (1<<14) // EBI: Data 14
+#define AT91_PIO_PSR_D15 (1<<15) // EBI: Data 15
+#define AT91_PIO_PSR_A18 (1<<16) // EBI: Address 18
+#define AT91_PIO_PSR_A19 (1<<17) // EBI: Address 19
+#define AT91_PIO_PSR_A20 (1<<18) // EBI: Address 20
+#define AT91_PIO_PSR_NANDALE (1<<19) // EBI: Address 21 /
+ // NAND Flash Address Line Enable
+#define AT91_PIO_PSR_NANDCLE (1<<20) // EBI: Address 22 /
+ // CompactFlash REG Signal /
+ // NAND Flash Command Line Enable
+#define AT91_PIO_PSR_CFNRW (1<<23) // EBI: CF Read Not Write Signal
+
+//PIO Controller C Peripheral B
+#define AT91_PIO_PSR_RTS1X (1<< 8) // USART 1 Ready To Send
+#define AT91_PIO_PSR_DTR1X (1<< 9) // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_PCK0X (1<<10) // Programmable Clock Output 0
+#define AT91_PIO_PSR_PCK1XX (1<<11) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2XX (1<<12) // Programmable Clock Output 2
+#define AT91_PIO_PSR_NPCS1XX (1<<14) // SPI Chip Select 1
+#define AT91_PIO_PSR_NANDCS (1<<15) // EBI: Chip Select 3 /
+ // NAND Flash Chip Select
+#define AT91_PIO_PSR_NWAIT (1<<16) // EBI: External Wait Signal
+#define AT91_PIO_PSR_NANDOE (1<<17) // EBI: NAND Flash Output Enable
+#define AT91_PIO_PSR_NANDWE (1<<18) // EBI: NAND Flash Write Enable
+#define AT91_PIO_PSR_NCS7 (1<<20) // EBI: Chip Select 7
+#define AT91_PIO_PSR_CFWE (1<<21) // EBI: Write 0 / SMC Write Enable /
+ // CompactFlash Write Enable
+#define AT91_PIO_PSR_CFOE (1<<22) // EBI: SMC Read Enable /
+ // CompactFlash Output Enable
+#define AT91_PIO_PSR_NCS0 (1<<23) // EBI: Chip Select 0
diff --git a/packages/hal/arm/at91/var/current/include/pio_sam7x.h b/packages/hal/arm/at91/var/current/include/pio_sam7x.h
new file mode 100644
index 0000000..9a43495
--- /dev/null
+++ b/packages/hal/arm/at91/var/current/include/pio_sam7x.h
@@ -0,0 +1,222 @@
+#ifndef CYGHWR_HAL_ARM_AT91SAM7X
+#error "CYGHWR_HAL_ARM_AT91SAM7X not defined"
+#endif
+
+// PIO Controller A, peripheral A
+#define AT91_USART_RXD0 AT91_PIN(0,0, 0) // USART 0 Receive Data
+#define AT91_USART_TXD0 AT91_PIN(0,0, 1) // USART 0 Transmit Data
+#define AT91_USART_SCK0 AT91_PIN(0,0, 2) // USART 0 Serial Clock
+#define AT91_USART_RTS0 AT91_PIN(0,0, 3) // USART 0 Request To Send
+#define AT91_USART_CTS0 AT91_PIN(0,0, 4) // USART 0 Clear To Send
+#define AT91_USART_RXD1 AT91_PIN(0,0, 5) // USART 1 Receive Data
+#define AT91_USART_TXD1 AT91_PIN(0,0, 6) // USART 1 Transmit Data
+#define AT91_USART_SCK1 AT91_PIN(0,0, 7) // USART 1 Serial Clock
+#define AT91_USART_RTS1 AT91_PIN(0,0, 8) // USART 1 Request To Send
+#define AT91_USART_CTS1 AT91_PIN(0,0, 9) // USART 1 Clear To Send
+#define AT91_TWI_TWD AT91_PIN(0,0,10) // Two Wire Data
+#define AT91_TWI_TWCK AT91_PIN(0,0,11) // Two Wire Clock
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,12) // SPI 0 Chip Select 0
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,13) // SPI 0 Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(0,0,14) // SPI 0 Chip Select 2
+#define AT91_SPI_NPCS3 AT91_PIN(0,0,15) // SPI 0 Chip Select 3
+#define AT91_SPI_MISO AT91_PIN(0,0,16) // SPI 0 Master In Slave Out
+#define AT91_SPI_MOSI AT91_PIN(0,0,17) // SPI 0 Master Out Slave In
+#define AT91_SPI_SPCK AT91_PIN(0,0,18) // SPI 0 Clock
+#define AT91_CAN_CANRX AT91_PIN(0,0,19) // CAN Receive
+#define AT91_CAN_CANTX AT91_PIN(0,0,20) // CAN Transmit
+#define AT91_SSC_TF AT91_PIN(0,0,21) // SSC Transmit Frame Sync
+#define AT91_S2C_TK AT91_PIN(0,0,22) // SSC Transmit Clock
+#define AT91_S2C_TD AT91_PIN(0,0,23) // SSC Transmit Data
+#define AT91_S2C_RD AT91_PIN(0,0,24) // SSC Receive Data
+#define AT91_S2C_RK AT91_PIN(0,0,25) // SSC Receive Clock
+#define AT91_S2C_RF AT91_PIN(0,0,26) // SSC Receive Frame Sync
+#define AT91_DBG_DRXD AT91_PIN(0,0,27) // DBGU Receive Data
+#define AT91_DBG_DTXD AT91_PIN(0,0,28) // DBGU Transmit Data
+#define AT91_INT_FIQ AT91_PIN(0,0,29) // Fast Interrupt Request
+#define AT91_INT_IRQ0 AT91_PIN(0,0,30) // Interrupt Request 0
+
+//PIO controller A, peripheral B
+#define AT91_SPI1_NPCS1 AT91_PIN(0,1, 2) // SPI 1 Chip Select 1
+#define AT91_SPI1_NPCS2 AT91_PIN(0,1, 3) // SPI 1 Chip Select 2
+#define AT91_SPI1_NPCS3 AT91_PIN(0,1, 4) // SPI 1 Chip Select 3
+#define AT91_SPI_NPCS1X AT91_PIN(0,1, 7) // SPI 0 Chip Select 1
+#define AT91_SPI_NPCS2X AT91_PIN(0,1, 8) // SPI 0 Chip Select 2
+#define AT91_SPI_NPCS3X AT91_PIN(0,1, 9) // SPI 0 Chip Select 3
+#define AT91_PCK_PCK1 AT91_PIN(0,1,13) // Programmable Clock Output 1
+#define AT91_INT_IRQ1 AT91_PIN(0,1,14) // Interrupt Request 1
+#define AT91_TC_TCLK1 AT91_PIN(0,1,15) // Timer/Counter 1 Clock Input
+#define AT91_SPI1_NPCS0 AT91_PIN(0,1,21) // SPI 1 Chip Select 0
+#define AT91_SPI1_SPCK AT91_PIN(0,1,22) // SPI 1 Clock
+#define AT91_SPI1_MOSI AT91_PIN(0,1,23) // SPI 1 Master Out Slave In
+#define AT91_SPI1_MISO AT91_PIN(0,1,24) // SPI 0 Master In Slave Out
+#define AT91_SPI1_NPCS1X AT91_PIN(0,1,25) // SPI 1 Chip Select 1
+#define AT91_SPI1_NPCS2X AT91_PIN(0,1,26) // SPI 1 Chip Select 2
+#define AT91_PCK_PCK3 AT91_PIN(0,1,27) // Programmable Clock Output 3
+#define AT91_SPI1_NPCS3X AT91_PIN(0,1,29) // SPI 1 Chip Select 3
+#define AT91_PCK_PCK2 AT91_PIN(0,1,30) // Programmable Clock Output 2
+
+//PIO Controller B, Peripheral A
+#define AT91_EMAC_EREFCK AT91_PIN(1,0, 0) // EMAC Reference Clock
+#define AT91_EMAC_ETXEN AT91_PIN(1,0, 1) // EMAC Transmit Enable
+#define AT91_EMAC_ETX0 AT91_PIN(1,0, 2) // EMAC Transmit Data 0
+#define AT91_EMAC_ETX1 AT91_PIN(1,0, 3) // EMAC Transmit Data 1
+#define AT91_EMAC_ECRS AT91_PIN(1,0, 4) // EMAC Carrier Sense
+#define AT91_EMAC_ERX0 AT91_PIN(1,0, 5) // EMAC Receive Data 0
+#define AT91_EMAC_ERX1 AT91_PIN(1,0, 6) // EMAC Receive Data 1
+#define AT91_EMAC_ERXER AT91_PIN(1,0, 7) // EMAC Receive Error
+#define AT91_EMAC_EMDC AT91_PIN(1,0, 8) // EMAC Management Data Clock
+#define AT91_EMAC_EMDIO AT91_PIN(1,0, 9) // EMAC Management Data IO
+#define AT91_EMAC_ETX2 AT91_PIN(1,0,10) // EMAC Transmit Data 2
+#define AT91_EMAC_ETX3 AT91_PIN(1,0,11) // EMAC Transmit Data 3
+#define AT91_EMAC_ETXER AT91_PIN(1,0,12) // EMAC Transmit Coding Error
+#define AT91_EMAC_ERX2 AT91_PIN(1,0,13) // EMAC Receive Data 2
+#define AT91_EMAC_ERX3 AT91_PIN(1,0,14) // EMAC Receive Data 3
+#define AT91_EMAC_ECRSDV AT91_PIN(1,0,15) // EMAC Carrier Sense And Data Valid
+#define AT91_EMAC_ERXDV AT91_PIN(1,0,15) // EMAC Receive Data Valid
+#define AT91_EMAC_ECOL AT91_PIN(1,0,16) // EMAC Collision Detected
+#define AT91_EMAC_ERXCK AT91_PIN(1,0,17) // EMAC Receive Clock
+#define AT91_EMAC_EF100 AT91_PIN(1,0,18) // EMAC Force 100Mb/s
+#define AT91_PWM_PWM0 AT91_PIN(1,0,19) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1 AT91_PIN(1,0,20) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2 AT91_PIN(1,0,21) // Pulse Width Modulation #2
+#define AT91_PWM_PWM3 AT91_PIN(1,0,22) // Pulse Width Modulation #3
+#define AT91_TC_TIOA0 AT91_PIN(1,0,23) // Timer/Counter 0 IO Line A
+#define AT91_TC_TIOB0 AT91_PIN(1,0,24) // Timer/Counter 0 IO Line B
+#define AT91_TC_TIOA1 AT91_PIN(1,0,25) // Timer/Counter 1 IO Line A
+#define AT91_TC_TIOB1 AT91_PIN(1,0,26) // Timer/Counter 1 IO Line B
+#define AT91_TC_TIOA2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line A
+#define AT91_TC_TIOB2 AT91_PIN(1,0,28) // Timer/Counter 2 IO Line B
+#define AT91_PCK_PCK1X AT91_PIN(1,0,29) // Programmable Clock Output 1
+#define AT91_PCK_PCK2X AT91_PIN(1,0,30) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_PCK_PCK0 AT91_PIN(1,1, 0) // Programmable Clock Output 0
+#define AT91_SPI1_NPCS1XX AT91_PIN(1,1,10) // SPI 1 Chip Select 1
+#define AT91_SPI1_NPCS2XX AT91_PIN(1,1,11) // SPI 1 Chip Select 2
+#define AT91_TC_TCLK0 AT91_PIN(1,1,12) // Timer/Counter 0 Clock Input
+#define AT91_SPI_NPCS1XX AT91_PIN(1,1,13) // SPI 0 Chip Select 1
+#define AT91_SPI_NPCS2XX AT91_PIN(1,1,14) // SPI 0 Chip Select 2
+#define AT91_SPI1_NPCS3XX AT91_PIN(1,1,16) // SPI 1 Chip Select 3
+#define AT91_SPI_NPCS3XX AT91_PIN(1,1,17) // SPI 0 Chip Select 3
+#define AT91_ADC_ADTRG AT91_PIN(1,1,18) // ADC Trigger
+#define AT91_TC_TCLK1X AT91_PIN(1,1,19) // Timer/Counter 1 Clock Input
+#define AT91_PCK_PCK0X AT91_PIN(1,1,20) // Programmable Clock Output 0
+#define AT91_PCK_PCK1XX AT91_PIN(1,1,21) // Programmable Clock Output 1
+#define AT91_PCK_PCK2XX AT91_PIN(1,1,22) // Programmable Clock Output 2
+#define AT91_USART_DCD1 AT91_PIN(1,1,23) // USART 1 Data Carrier Detect
+#define AT91_USART_DSR1 AT91_PIN(1,1,24) // USART 1 Data Set Ready
+#define AT91_USART_DTR1 AT91_PIN(1,1,25) // USART 1 Data Terminal Ready
+#define AT91_USART_RI1 AT91_PIN(1,1,26) // USART 1 Ring Indication
+#define AT91_PWM_PWM0X AT91_PIN(1,1,27) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1X AT91_PIN(1,1,28) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2X AT91_PIN(1,1,29) // Pulse Width Modulation #2
+#define AT91_PWM_PWM3X AT91_PIN(1,1,30) // Pulse Width Modulation #3
+
+// PIO Controller A, peripheral A
+#define AT91_PIO_PSR_RXD0 (1<< 0) // USART 0 Receive Data
+#define AT91_PIO_PSR_TXD0 (1<< 1) // USART 0 Transmit Data
+#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
+#define AT91_PIO_PSR_RTS0 (1<< 3) // USART 0 Request To Send
+#define AT91_PIO_PSR_CTS0 (1<< 4) // USART 0 Clear To Send
+#define AT91_PIO_PSR_RXD1 (1<< 5) // USART 1 Receive Data
+#define AT91_PIO_PSR_TXD1 (1<< 6) // USART 1 Transmit Data
+#define AT91_PIO_PSR_SCK1 (1<< 7) // USART 1 Serial Clock
+#define AT91_PIO_PSR_RTS1 (1<< 8) // USART 1 Request To Send
+#define AT91_PIO_PSR_CTS1 (1<< 9) // USART 1 Clear To Send
+#define AT91_PIO_PSR_TWD (1<<10) // Two Wire Data
+#define AT91_PIO_PSR_TWCK (1<<11) // Two Wire Clock
+#define AT91_PIO_PSR_SPI_NPCS0 (1<<12) // SPI 0 Chip Select 0
+#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
+#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
+#define AT91_PIO_PSR_SPI_NPCS3 (1<<15) // SPI 0 Chip Select 3
+#define AT91_PIO_PSR_SPI_MISO (1<<16) // SPI 0 Master In Slave Out
+#define AT91_PIO_PSR_SPI_MOSI (1<<17) // SPI 0 Master Out Slave In
+#define AT91_PIO_PSR_SPI_SPCK (1<<18) // SPI 0 Clock
+#define AT91_PIO_PSR_CANRX (1<<19) // CAN Receive
+#define AT91_PIO_PSR_CANTX (1<<20) // CAN Transmit
+#define AT91_PIO_PSR_TF (1<<21) // SSC Transmit Frame Sync
+#define AT91_PIO_PSR_TK (1<<22) // SSC Transmit Clock
+#define AT91_PIO_PSR_TD (1<<23) // SSC Transmit Data
+#define AT91_PIO_PSR_RD (1<<24) // SSC Receive Data
+#define AT91_PIO_PSR_RK (1<<25) // SSC Receive Clock
+#define AT91_PIO_PSR_RF (1<<26) // SSC Receive Frame Sync
+#define AT91_PIO_PSR_DRXD (1<<27) // DBGU Receive Data
+#define AT91_PIO_PSR_DTXD (1<<28) // DBGU Transmit Data
+#define AT91_PIO_PSR_FIQ (1<<29) // Fast Interrupt Request
+#define AT91_PIO_PSR_IRQ0 (1<<30) // Interrupt Request 0
+
+//PIO controller A, peripheral B
+#define AT91_PIO_PSR_SPI1_NPCS1 (1<< 2) // SPI 1 Chip Select 1
+#define AT91_PIO_PSR_SPI1_NPCS2 (1<< 3) // SPI 1 Chip Select 2
+#define AT91_PIO_PSR_SPI1_NPCS3 (1<< 4) // SPI 1 Chip Select 3
+#define AT91_PIO_PSR_SPI_NPCS1X (1<< 7) // SPI 0 Chip Select 1
+#define AT91_PIO_PSR_SPI_NPCS2X (1<< 8) // SPI 0 Chip Select 2
+#define AT91_PIO_PSR_SPI_NPCS3X (1<< 9) // SPI 0 Chip Select 3
+#define AT91_PIO_PSR_PCK1 (1<<13) // Programmable Clock Output 1
+#define AT91_PIO_PSR_IRQ1 (1<<14) // Interrupt Request 1
+#define AT91_PIO_PSR_TCLK1 (1<<15) // Timer/Counter 1 Clock Input
+#define AT91_PIO_PSR_SPI1_NPCS0 (1<<21) // SPI 1 Chip Select 0
+#define AT91_PIO_PSR_SPI1_SPCK (1<<22) // SPI 1 Clock
+#define AT91_PIO_PSR_SPI1_MOSI (1<<23) // SPI 1 Master Out Slave In
+#define AT91_PIO_PSR_SPI1_MISO (1<<24) // SPI 0 Master In Slave Out
+#define AT91_PIO_PSR_SPI1_NPCS1X (1<<25) // SPI 1 Chip Select 1
+#define AT91_PIO_PSR_SPI1_NPCS2X (1<<26) // SPI 1 Chip Select 2
+#define AT91_PIO_PSR_PCK3 (1<<27) // Programmable Clock Output 3
+#define AT91_PIO_PSR_SPI1_NPCS3X (1<<29) // SPI 1 Chip Select 3
+#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
+
+//PIO Controller B, Peripheral A
+#define AT91_PIO_PSR_EREFCK (1<< 0) // EMAC Reference Clock
+#define AT91_PIO_PSR_ETXEN (1<< 1) // EMAC Transmit Enable
+#define AT91_PIO_PSR_ETX0 (1<< 2) // EMAC Transmit Data 0
+#define AT91_PIO_PSR_ETX1 (1<< 3) // EMAC Transmit Data 1
+#define AT91_PIO_PSR_ECRS (1<< 4) // EMAC Carrier Sense
+#define AT91_PIO_PSR_ERX0 (1<< 5) // EMAC Receive Data 0
+#define AT91_PIO_PSR_ERX1 (1<< 6) // EMAC Receive Data 1
+#define AT91_PIO_PSR_ERXER (1<< 7) // EMAC Receive Error
+#define AT91_PIO_PSR_EMDC (1<< 8) // EMAC Management Data Clock
+#define AT91_PIO_PSR_EMDIO (1<< 9) // EMAC Management Data IO
+#define AT91_PIO_PSR_ETX2 (1<<10) // EMAC Transmit Data 2
+#define AT91_PIO_PSR_ETX3 (1<<11) // EMAC Transmit Data 3
+#define AT91_PIO_PSR_ETXER (1<<12) // EMAC Transmit Coding Error
+#define AT91_PIO_PSR_ERX2 (1<<13) // EMAC Receive Data 2
+#define AT91_PIO_PSR_ERX3 (1<<14) // EMAC Receive Data 3
+#define AT91_PIO_PSR_ECRSDV (1<<15) // EMAC Carrier Sense And Data Valid
+#define AT91_PIO_PSR_ECOL (1<<16) // EMAC Collision Detected
+#define AT91_PIO_PSR_ERXCK (1<<17) // EMAC Receive Clock
+#define AT91_PIO_PSR_EF100 (1<<18) // EMAC Force 100Mb/s
+#define AT91_PIO_PSR_PWM0 (1<<19) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1 (1<<20) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2 (1<<21) // Pulse Width Modulation #2
+#define AT91_PIO_PSR_PWM3 (1<<22) // Pulse Width Modulation #3
+#define AT91_PIO_PSR_TIOA0 (1<<23) // Timer/Counter 0 IO Line A
+#define AT91_PIO_PSR_TIOB0 (1<<24) // Timer/Counter 0 IO Line B
+#define AT91_PIO_PSR_TIOA1 (1<<25) // Timer/Counter 1 IO Line A
+#define AT91_PIO_PSR_TIOB1 (1<<26) // Timer/Counter 1 IO Line B
+#define AT91_PIO_PSR_TIOA2 (1<<27) // Timer/Counter 2 IO Line A
+#define AT91_PIO_PSR_TIOB2 (1<<28) // Timer/Counter 2 IO Line B
+#define AT91_PIO_PSR_PCK1X (1<<29) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_PIO_PSR_PCK0 (1<< 0) // Programmable Clock Output 0
+#define AT91_PIO_PSR_SPI1_NPCS1XX (1<<10) // SPI 1 Chip Select 1
+#define AT91_PIO_PSR_SPI1_NPCS2XX (1<<11) // SPI 1 Chip Select 2
+#define AT91_PIO_PSR_TCLK0 (1<<12) // Timer/Counter 0 Clock Input
+#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
+#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
+#define AT91_PIO_PSR_SPI1_NPCS3XX (1<<16) // SPI 1 Chip Select 3
+#define AT91_PIO_PSR_SPI_NPCS3XX (1<<17) // SPI 0 Chip Select 3
+#define AT91_PIO_PSR_ADTRG (1<<18) // ADC Trigger
+#define AT91_PIO_PSR_TCLK1X (1<<19) // Timer/Counter 1 Clock Input
+#define AT91_PIO_PSR_PCK0X (1<<20) // Programmable Clock Output 0
+#define AT91_PIO_PSR_PCK1XX (1<<21) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2X (1<<22) // Programmable Clock Output 2
+#define AT91_PIO_PSR_DCD1 (1<<23) // USART 1 Data Carrier Detect
+#define AT91_PIO_PSR_DSR1 (1<<24) // USART 1 Data Set Ready
+#define AT91_PIO_PSR_DTR1 (1<<25) // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_RI1 (1<<26) // USART 1 Ring Indication
+#define AT91_PIO_PSR_PWM0X (1<<27) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2
+#define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3
diff --git a/packages/hal/arm/at91/var/current/include/var_io.h b/packages/hal/arm/at91/var/current/include/var_io.h
index 404fb68..973e814 100644
--- a/packages/hal/arm/at91/var/current/include/var_io.h
+++ b/packages/hal/arm/at91/var/current/include/var_io.h
@@ -280,923 +280,11 @@
#define AT91_GPIO_PC31 AT91_PIN(2,0,31)
#endif //AT91_PIOC
-#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
-
-#define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal
-#define AT91_TC_TIOA3 AT91_PIN(0,0, 1) // Timer 3 Signal A
-#define AT91_TC_TIOB3 AT91_PIN(0,0, 2) // Timer 3 Signal B
-#define AT91_TC_TCLK4 AT91_PIN(0,0, 3) // Timer 4 Clock signal
-#define AT91_TC_TIOA4 AT91_PIN(0,0, 4) // Timer 4 Signal A
-#define AT91_TC_TIOB4 AT91_PIN(0,0, 5) // Timer 4 Signal B
-#define AT91_TC_TCLK5 AT91_PIN(0,0, 6) // Timer 5 Clock signal
-#define AT91_TC_TIOA5 AT91_PIN(0,0, 7) // Timer 5 Signal A
-#define AT91_TC_TIOB5 AT91_PIN(0,0, 8) // Timer 5 Signal B
-#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // External Interrupt 0
-#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // External Interrupt 1
-#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // External Interrupt 2
-#define AT91_INT_IRQ3 AT91_PIN(0,0,12) // External Interrupt 3
-#define AT91_INT_FIQ AT91_PIN(0,0,13) // Fast Interrupt
-#define AT91_USART_SCK0 AT91_PIN(0,0,14) // USART 0 Clock signal
-#define AT91_USART_TXD0 AT91_PIN(0,0,15) // USART 0 transmit data
-#define AT91_USART_RXD0 AT91_PIN(0,0,16) // USART 0 receive data
-#define AT91_USART_SCK1 AT91_PIN(0,0,17) // USART 1 Clock signal
-#define AT91_USART_TXD1 AT91_PIN(0,0,18) // USART 1 transmit data
-#define AT91_USART_RXD1 AT91_PIN(0,0,19) // USART 1 receive data
-#define AT91_USART_SCK2 AT91_PIN(0,0,20) // USART 2 Clock signal
-#define AT91_USART_TXD2 AT91_PIN(0,0,21) // USART 2 transmit data
-#define AT91_USART_RXD2 AT91_PIN(0,0,22) // USART 2 receive data
-#define AT91_SPI_SPCK AT91_PIN(0,0,23) // SPI Clock signal
-#define AT91_SPI_MISO AT91_PIN(0,0,24) // SPI Master In Slave Out
-#define AT91_SPI_MOSI AT91_PIN(0,0,25) // SPI Master Out Slave In
-#define AT91_SPI_NPCS0 AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0
-#define AT91_SPI_NPCS1 AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1
-#define AT91_SPI_NPCS2 AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2
-#define AT91_SPI_NPCS3 AT91_PIN(0,0,29) // SPI Peripheral Chip Select 3
-
-#define AT91_INT_IRQ4 AT91_PIN(1,0, 3) // External Interrupt 4
-#define AT91_INT_IRQ5 AT91_PIN(1,0, 4) // External Interrupt 5
-#define AT91_ADC_AD0TRIG AT91_PIN(1,0, 6) // ADC0 External Trigger
-#define AT91_ADC_AD1TRIG AT91_PIN(1,0, 7) // ADC1 External Trigger
-#define AT91_BOOT_BMS AT91_PIN(1,0,12) // Boot Mode Select
-#define AT91_TC_TCLK0 AT91_PIN(1,0,14) // Timer 0 Clock signal
-#define AT91_TC_TIOA0 AT91_PIN(1,0,15) // Timer 0 Signal A
-#define AT91_TC_TIOB0 AT91_PIN(1,0,16) // Timer 0 Signal B
-#define AT91_TC_TCLK1 AT91_PIN(1,0,17) // Timer 1 Clock signal
-#define AT91_TC_TIOA1 AT91_PIN(1,0,18) // Timer 1 Signal A
-#define AT91_TC_TIOB1 AT91_PIN(1,0,19) // Timer 1 Signal B
-#define AT91_TC_TCLK2 AT91_PIN(1,0,20) // Timer 2 Clock signal
-#define AT91_TC_TIOA2 AT91_PIN(1,0,21) // Timer 2 Signal A
-#define AT91_TC_TIOB2 AT91_PIN(1,0,22) // Timer 2 Signal B
-
-// PIOA
-#define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal
-#define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A
-#define AT91_PIO_PSR_TIOB3 0x00000004 // Timer 3 Signal B
-#define AT91_PIO_PSR_TCLK4 0x00000008 // Timer 4 Clock signal
-#define AT91_PIO_PSR_TIOA4 0x00000010 // Timer 4 Signal A
-#define AT91_PIO_PSR_TIOB4 0x00000020 // Timer 4 Signal B
-#define AT91_PIO_PSR_TCLK5 0x00000040 // Timer 5 Clock signal
-#define AT91_PIO_PSR_TIOA5 0x00000080 // Timer 5 Signal A
-#define AT91_PIO_PSR_TIOB5 0x00000100 // Timer 5 Signal B
-#define AT91_PIO_PSR_IRQ0 0x00000200 // External Interrupt 0
-#define AT91_PIO_PSR_IRQ1 0x00000400 // External Interrupt 1
-#define AT91_PIO_PSR_IRQ2 0x00000800 // External Interrupt 2
-#define AT91_PIO_PSR_IRQ3 0x00001000 // External Interrupt 3
-#define AT91_PIO_PSR_FIQ 0x00002000 // Fast Interrupt
-#define AT91_PIO_PSR_SCK0 0x00004000 // USART 0 Clock signal
-#define AT91_PIO_PSR_TXD0 0x00008000 // USART 0 transmit data
-#define AT91_PIO_PSR_RXD0 0x00010000 // USART 0 receive data
-#define AT91_PIO_PSR_SCK1 0x00020000 // USART 1 Clock signal
-#define AT91_PIO_PSR_TXD1 0x00040000 // USART 1 transmit data
-#define AT91_PIO_PSR_RXD1 0x00080000 // USART 1 receive data
-#define AT91_PIO_PSR_SCK2 0x00100000 // USART 2 Clock signal
-#define AT91_PIO_PSR_TXD2 0x00200000 // USART 2 transmit data
-#define AT91_PIO_PSR_RXD2 0x00400000 // USART 2 receive data
-#define AT91_PIO_PSR_SPCK 0x00800000 // SPI Clock signal
-#define AT91_PIO_PSR_MISO 0x01000000 // SPI Master In Slave Out
-#define AT91_PIO_PSR_MOSI 0x02000000 // SPI Master Out Slave In
-#define AT91_PIO_PSR_NPCS0 0x04000000 // SPI Peripheral Chip Select 0
-#define AT91_PIO_PSR_NPCS1 0x08000000 // SPI Peripheral Chip Select 1
-#define AT91_PIO_PSR_NPCS2 0x10000000 // SPI Peripheral Chip Select 2
-#define AT91_PIO_PSR_NPCS3 0x20000000 // SPI Peripheral Chip Select 3
-
-// PIOB
-#define AT91_PIO_PSR_IRQ4 0x00000008 // External Interrupt 4
-#define AT91_PIO_PSR_IRQ5 0x00000010 // External Interrupt 5
-#define AT91_PIO_PSR_AD0TRIG 0x00000040 // ADC0 External Trigger
-#define AT91_PIO_PSR_AD1TRIG 0x00000080 // ADC1 External Trigger
-#define AT91_PIO_PSR_BMS 0x00040000 // Boot Mode Select
-#define AT91_PIO_PSR_TCLK0 0x00080000 // Timer 0 Clock signal
-#define AT91_PIO_PSR_TIOA0 0x00100000 // Timer 0 Signal A
-#define AT91_PIO_PSR_TIOB0 0x00200000 // Timer 0 Signal B
-#define AT91_PIO_PSR_TCLK1 0x00400000 // Timer 1 Clock signal
-#define AT91_PIO_PSR_TIOA1 0x00800000 // Timer 1 Signal A
-#define AT91_PIO_PSR_TIOB1 0x01000000 // Timer 1 Signal B
-#define AT91_PIO_PSR_TCLK2 0x02000000 // Timer 2 Clock signal
-#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A
-#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B
-
-#elif defined (CYGHWR_HAL_ARM_AT91SAM7)
-#include <pkgconf/hal_arm_at91sam7.h>
-
-#ifdef CYGHWR_HAL_ARM_AT91SAM7S
-#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
-#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
-#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
-#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
-#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
-#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
-#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
-#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
-#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
-#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
-#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
-#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
-#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
-#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
-#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
-#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
-#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
-#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
-#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
-#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
-#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
-#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
-#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
-#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
-#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
-#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
-#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
-#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
-#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
-#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
-#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
-#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
+#ifndef CYGBLD_HAL_AT91_PIO_LAYOUT_H
+#define CYGBLD_HAL_AT91_PIO_LAYOUT_H <cyg/hal/pio_default.h>
#endif
-#define AT91_TC_TIOA0 AT91_PIN(0,1, 0) // Timer/Counter 0 IO Line A
-#define AT91_TC_TIOB0 AT91_PIN(0,1, 1) // Timer/Counter 0 IO Line B
-#define AT91_USART_SCK0 AT91_PIN(0,1, 2) // USART 0 Serial Clock
-#define AT91_SPI_NPCS3 AT91_PIN(0,1, 3) // SPI Chip Select 3
-#define AT91_TC_TCLK0 AT91_PIN(0,1, 4) // Timer/Counter 0 Clock Input
-#define AT91_SPI_NPCS3X AT91_PIN(0,1, 5) // SPI Chip Select 3 (again)
-#define AT91_PCK_PCK0 AT91_PIN(0,1, 6) // Programmable Clock Output 0
-#define AT91_PWM_PWM3 AT91_PIN(0,1, 7) // Pulse Width Modulation #3
-#define AT91_ADC_ADTRG AT91_PIN(0,1, 8) // ADC Trigger
-#define AT91_SPI_NPCS1X AT91_PIN(0,1, 9) // SPI Chip Select 1
-#define AT91_SPI_NPCS2 AT91_PIN(0,1,10) // SPI Chip Select 2
-#define AT91_PWM_PWM0X AT91_PIN(0,1,11) // Pulse Width Modulation #0
-#define AT91_PIO_PWM_PWM1X AT91_PIN(0,1,12) // Pulse Width Modulation #1
-#define AT91_PIO_PWM_PWM2X AT91_PIN(0,1,13) // Pulse Width Modulation #2
-#define AT91_PIO_PWM_PWM4X AT91_PIN(0,1,14) // Pulse Width Modulation #4
-#define AT91_TC_TIOA1 AT91_PIN(0,1,15) // Timer/Counter 1 IO Line A
-#define AT91_TC_TIOB1 AT91_PIN(0,1,16) // Timer/Counter 1 IO Line B
-#define AT91_PCK_PCK1 AT91_PIN(0,1,17) // Programmable Clock Output 1
-#define AT91_PCK_PCK2 AT91_PIN(0,1,18) // Programmable Clock Output 2
-#define AT91_INT_FIQ AT91_PIN(0,1,19) // Fast Interrupt Request
-#define AT91_INT_IRQ0 AT91_PIN(0,1,20) // Interrupt Request 0
-#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-#define AT91_PCK_PCK1X AT91_PIN(0,1,21) // Programmable Clock Output 1
-#define AT91_SPI_NPCS3XX AT91_PIN(0,1,22) // SPI Chip Select 3 (yet again)
-#define AT91_PWM_PWM0XX AT91_PIN(0,1,23) // Pulse Width Modulation #0
-#define AT91_PWM_PWM1XX AT91_PIN(0,1,24) // Pulse Width Modulation #1
-#define AT91_PWM_PWM2XX AT91_PIN(0,1,25) // Pulse Width Modulation 2
-#define AT91_TC_TIOA2 AT91_PIN(0,1,26) // Timer/Counter 2 IO Line A
-#define AT91_TC_TIOB2 AT91_PIN(0,1,27) // Timer/Counter 2 IO Line B
-#define AT91_TC_TCLK1 AT91_PIN(0,1,28) // External Clock Input 1
-#define AT91_TC_TCLK2 AT91_PIN(0,1,29) // External Clock Input 2
-#define AT91_SPI_NPCS2X AT91_PIN(0,1,30) // SPI Chip Select 2 (again)
-#define AT91_PCK_PCK2X AT91_PIN(0,1,31) // Programmable Clock Output 2
-#endif //!defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-
-// PIO Peripheral A
-#define AT91_PIO_PSR_PWM0 0x00000001 // Pulse Width Modulation 0
-#define AT91_PIO_PSR_PWM1 0x00000002 // Pulse Width Modulation 1
-#define AT91_PIO_PSR_PWM2 0x00000004 // Pulse Width Modulation 2
-#define AT91_PIO_PSR_TWD 0x00000008 // Two Wire Data
-#define AT91_PIO_PSR_TWCK 0x00000010 // Two Wire Clock
-#define AT91_PIO_PSR_RXD0 0x00000020 // USART 0 Receive Data
-#define AT91_PIO_PSR_TXD0 0x00000040 // USART 0 Transmit Data
-#define AT91_PIO_PSR_RTS0 0x00000080 // USART 0 Ready To Send
-#define AT91_PIO_PSR_CTS0 0x00000100 // USART 0 Clear To Send
-#define AT91_PIO_PSR_DRXD 0x00000200 // Debug UART Receive
-#define AT91_PIO_PSR_DTXD 0x00000400 // Debug UART Transmit
-#define AT91_PIO_PSR_NPCS0 0x00000800 // SPI Chip Select 0
-#define AT91_PIO_PSR_MISO 0x00001000 // SPI Input
-#define AT91_PIO_PSR_MOSI 0x00002000 // SPI Output
-#define AT91_PIO_PSR_SPCK 0x00004000 // SPI clock
-#define AT91_PIO_PSR_TF 0x00008000 // S2C Transmit Frame Sync
-#define AT91_PIO_PSR_TK 0x00010000 // S2C Transmit Clock
-#define AT91_PIO_PSR_TD 0x00020000 // S2C Transmit Data
-#define AT91_PIO_PSR_RD 0x00040000 // S2C Receive Data
-#define AT91_PIO_PSR_RK 0x00080000 // S2C Receive Clock
-#define AT91_PIO_PSR_RF 0x00100000 // S2C Receive Frame Sync
-#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-#define AT91_PIO_PSR_RXD1 0x00200000 // USART 1 Receive Data
-#define AT91_PIO_PSR_TXD1 0x00400000 // USART 1 Transmit Data
-#define AT91_PIO_PSR_SCK1 0x00800000 // USART 1 Serial Clock
-#define AT91_PIO_PSR_RTS1 0x01000000 // USART 1 Ready To Send
-#define AT91_PIO_PSR_CTS1 0x02000000 // USART 1 Clear To Send
-#define AT91_PIO_PSR_DCD1 0x04000000 // USART 1 Data Carrier Detect
-#define AT91_PIO_PSR_DTR1 0x08000000 // USART 1 Data Terminal Ready
-#define AT91_PIO_PSR_DSR1 0x10000000 // USART 1 Data Set Ready
-#define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator
-#define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1
-#define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1
-#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-
-// PIO Peripheral B
-#define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A
-#define AT91_PIO_PSR_TIOB0 0x00000002 // Timer/Counter 0 IO Line B
-#define AT91_PIO_PSR_SCK0 0x00000004 // USART 0 Serial Clock
-#define AT91_PIO_PSR_NPCS3 0x00000008 // SPI Chip Select 3
-#define AT91_PIO_PSR_TCLK0 0x00000010 // Timer/Counter 0 Clock Input
-#define AT91_PIO_PSR_NPCS3X 0x00000020 // SPI Chip Select 3 (again)
-#define AT91_PIO_PSR_PCK0 0x00000040 // Programmable Clock Output 0
-#define AT91_PIO_PSR_PWM3 0x00000080 // Pulse Width Modulation #3
-#define AT91_PIO_PSR_ADTRG 0x00000100 // ADC Trigger
-#define AT91_PIO_PSR_NPCS1X 0x00000200 // SPI Chip Select 1 (again)
-#define AT91_PIO_PSR_NPCS2 0x00000400 // SPI Chip Select 2
-#define AT91_PIO_PSR_PWMOX 0x00000800 // Pulse Width Modulation #0 (again)
-#define AT91_PIO_PSR_PWM1X 0x00001000 // Pulse Width Modulation #1 (again)
-#define AT91_PIO_PSR_PWM2X 0x00002000 // Pulse Width Modulation #2 (again)
-#define AT91_PIO_PSR_PWM3X 0x00004000 // Pulse Width Modulation #4 (again)
-#define AT91_PIO_PSR_TIOA1 0x00008000 // Timer/Counter 1 IO Line A
-#define AT91_PIO_PSR_TIOB1 0x00010000 // Timer/Counter 1 IO Line B
-#define AT91_PIO_PSR_PCK1 0x00020000 // Programmable Clock Output 1
-#define AT91_PIO_PSR_PCK2 0x00040000 // Programmable Clock Output 2
-#define AT91_PIO_PSR_FIQ 0x00080000 // Fast Interrupt Request
-#define AT91_PIO_PSR_IRQ0 0x00100000 // Interrupt Request 0
-#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-#define AT91_PIO_PSR_PCK1X 0x00200000 // Programmable Clock Output 1(again)
-#define AT91_PIO_PSR_NPCS3XX 0x00400000 // SPI Chip Select 3 (yet again)
-#define AT91_PIO_PSR_PWMOXX 0x00800000 // Pulse Width Modulation #0 (again)
-#define AT91_PIO_PSR_PWM1XX 0x01000000 // Pulse Width Modulation #1 (again)
-#define AT91_PIO_PSR_PWM2XX 0x02000000 // Pulse Width Modulation #2 (again)
-#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer/Counter 2 IO Line A
-#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer/Counter 2 IO Line B
-#define AT91_PIO_PSR_TCLK1 0x10000000 // External Clock Input 1
-#define AT91_PIO_PSR_TCLK2 0x20000000 // External Clock Input 2
-#define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again)
-#define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again)
-#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
-#endif // CYGHWR_HAL_ARM_AT91SAM7S
-
-#ifdef CYGHWR_HAL_ARM_AT91SAM7X
-
-// PIO Controller A, peripheral A
-#define AT91_USART_RXD0 AT91_PIN(0,0, 0) // USART 0 Receive Data
-#define AT91_USART_TXD0 AT91_PIN(0,0, 1) // USART 0 Transmit Data
-#define AT91_USART_SCK0 AT91_PIN(0,0, 2) // USART 0 Serial Clock
-#define AT91_USART_RTS0 AT91_PIN(0,0, 3) // USART 0 Request To Send
-#define AT91_USART_CTS0 AT91_PIN(0,0, 4) // USART 0 Clear To Send
-#define AT91_USART_RXD1 AT91_PIN(0,0, 5) // USART 1 Receive Data
-#define AT91_USART_TXD1 AT91_PIN(0,0, 6) // USART 1 Transmit Data
-#define AT91_USART_SCK1 AT91_PIN(0,0, 7) // USART 1 Serial Clock
-#define AT91_USART_RTS1 AT91_PIN(0,0, 8) // USART 1 Request To Send
-#define AT91_USART_CTS1 AT91_PIN(0,0, 9) // USART 1 Clear To Send
-#define AT91_TWI_TWD AT91_PIN(0,0,10) // Two Wire Data
-#define AT91_TWI_TWCK AT91_PIN(0,0,11) // Two Wire Clock
-#define AT91_SPI_NPCS0 AT91_PIN(0,0,12) // SPI 0 Chip Select 0
-#define AT91_SPI_NPCS1 AT91_PIN(0,0,13) // SPI 0 Chip Select 1
-#define AT91_SPI_NPCS2 AT91_PIN(0,0,14) // SPI 0 Chip Select 2
-#define AT91_SPI_NPCS3 AT91_PIN(0,0,15) // SPI 0 Chip Select 3
-#define AT91_SPI_MISO AT91_PIN(0,0,16) // SPI 0 Master In Slave Out
-#define AT91_SPI_MOSI AT91_PIN(0,0,17) // SPI 0 Master Out Slave In
-#define AT91_SPI_SPCK AT91_PIN(0,0,18) // SPI 0 Clock
-#define AT91_CAN_CANRX AT91_PIN(0,0,19) // CAN Receive
-#define AT91_CAN_CANTX AT91_PIN(0,0,20) // CAN Transmit
-#define AT91_SSC_TF AT91_PIN(0,0,21) // SSC Transmit Frame Sync
-#define AT91_S2C_TK AT91_PIN(0,0,22) // SSC Transmit Clock
-#define AT91_S2C_TD AT91_PIN(0,0,23) // SSC Transmit Data
-#define AT91_S2C_RD AT91_PIN(0,0,24) // SSC Receive Data
-#define AT91_S2C_RK AT91_PIN(0,0,25) // SSC Receive Clock
-#define AT91_S2C_RF AT91_PIN(0,0,26) // SSC Receive Frame Sync
-#define AT91_DBG_DRXD AT91_PIN(0,0,27) // DBGU Receive Data
-#define AT91_DBG_DTXD AT91_PIN(0,0,28) // DBGU Transmit Data
-#define AT91_INT_FIQ AT91_PIN(0,0,29) // Fast Interrupt Request
-#define AT91_INT_IRQ0 AT91_PIN(0,0,30) // Interrupt Request 0
-
-//PIO controller A, peripheral B
-#define AT91_SPI1_NPCS1 AT91_PIN(0,1, 2) // SPI 1 Chip Select 1
-#define AT91_SPI1_NPCS2 AT91_PIN(0,1, 3) // SPI 1 Chip Select 2
-#define AT91_SPI1_NPCS3 AT91_PIN(0,1, 4) // SPI 1 Chip Select 3
-#define AT91_SPI_NPCS1X AT91_PIN(0,1, 7) // SPI 0 Chip Select 1
-#define AT91_SPI_NPCS2X AT91_PIN(0,1, 8) // SPI 0 Chip Select 2
-#define AT91_SPI_NPCS3X AT91_PIN(0,1, 9) // SPI 0 Chip Select 3
-#define AT91_PCK_PCK1 AT91_PIN(0,1,13) // Programmable Clock Output 1
-#define AT91_INT_IRQ1 AT91_PIN(0,1,14) // Interrupt Request 1
-#define AT91_TC_TCLK1 AT91_PIN(0,1,15) // Timer/Counter 1 Clock Input
-#define AT91_SPI1_NPCS0 AT91_PIN(0,1,21) // SPI 1 Chip Select 0
-#define AT91_SPI1_SPCK AT91_PIN(0,1,22) // SPI 1 Clock
-#define AT91_SPI1_MOSI AT91_PIN(0,1,23) // SPI 1 Master Out Slave In
-#define AT91_SPI1_MISO AT91_PIN(0,1,24) // SPI 0 Master In Slave Out
-#define AT91_SPI1_NPCS1X AT91_PIN(0,1,25) // SPI 1 Chip Select 1
-#define AT91_SPI1_NPCS2X AT91_PIN(0,1,26) // SPI 1 Chip Select 2
-#define AT91_PCK_PCK3 AT91_PIN(0,1,27) // Programmable Clock Output 3
-#define AT91_SPI1_NPCS3X AT91_PIN(0,1,29) // SPI 1 Chip Select 3
-#define AT91_PCK_PCK2 AT91_PIN(0,1,30) // Programmable Clock Output 2
-
-//PIO Controller B, Peripheral A
-#define AT91_EMAC_EREFCK AT91_PIN(1,0, 0) // EMAC Reference Clock
-#define AT91_EMAC_ETXEN AT91_PIN(1,0, 1) // EMAC Transmit Enable
-#define AT91_EMAC_ETX0 AT91_PIN(1,0, 2) // EMAC Transmit Data 0
-#define AT91_EMAC_ETX1 AT91_PIN(1,0, 3) // EMAC Transmit Data 1
-#define AT91_EMAC_ECRS AT91_PIN(1,0, 4) // EMAC Carrier Sense
-#define AT91_EMAC_ERX0 AT91_PIN(1,0, 5) // EMAC Receive Data 0
-#define AT91_EMAC_ERX1 AT91_PIN(1,0, 6) // EMAC Receive Data 1
-#define AT91_EMAC_ERXER AT91_PIN(1,0, 7) // EMAC Receive Error
-#define AT91_EMAC_EMDC AT91_PIN(1,0, 8) // EMAC Management Data Clock
-#define AT91_EMAC_EMDIO AT91_PIN(1,0, 9) // EMAC Management Data IO
-#define AT91_EMAC_ETX2 AT91_PIN(1,0,10) // EMAC Transmit Data 2
-#define AT91_EMAC_ETX3 AT91_PIN(1,0,11) // EMAC Transmit Data 3
-#define AT91_EMAC_ETXER AT91_PIN(1,0,12) // EMAC Transmit Coding Error
-#define AT91_EMAC_ERX2 AT91_PIN(1,0,13) // EMAC Receive Data 2
-#define AT91_EMAC_ERX3 AT91_PIN(1,0,14) // EMAC Receive Data 3
-#define AT91_EMAC_ECRSDV AT91_PIN(1,0,15) // EMAC Carrier Sense And Data Valid
-#define AT91_EMAC_ERXDV AT91_PIN(1,0,15) // EMAC Receive Data Valid
-#define AT91_EMAC_ECOL AT91_PIN(1,0,16) // EMAC Collision Detected
-#define AT91_EMAC_ERXCK AT91_PIN(1,0,17) // EMAC Receive Clock
-#define AT91_EMAC_EF100 AT91_PIN(1,0,18) // EMAC Force 100Mb/s
-#define AT91_PWM_PWM0 AT91_PIN(1,0,19) // Pulse Width Modulation #0
-#define AT91_PWM_PWM1 AT91_PIN(1,0,20) // Pulse Width Modulation #1
-#define AT91_PWM_PWM2 AT91_PIN(1,0,21) // Pulse Width Modulation #2
-#define AT91_PWM_PWM3 AT91_PIN(1,0,22) // Pulse Width Modulation #3
-#define AT91_TC_TIOA0 AT91_PIN(1,0,23) // Timer/Counter 0 IO Line A
-#define AT91_TC_TIOB0 AT91_PIN(1,0,24) // Timer/Counter 0 IO Line B
-#define AT91_TC_TIOA1 AT91_PIN(1,0,25) // Timer/Counter 1 IO Line A
-#define AT91_TC_TIOB1 AT91_PIN(1,0,26) // Timer/Counter 1 IO Line B
-#define AT91_TC_TIOA2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line A
-#define AT91_TC_TIOB2 AT91_PIN(1,0,28) // Timer/Counter 2 IO Line B
-#define AT91_PCK_PCK1X AT91_PIN(1,0,29) // Programmable Clock Output 1
-#define AT91_PCK_PCK2X AT91_PIN(1,0,30) // Programmable Clock Output 2
-
-//PIO Controller B Peripheral B
-#define AT91_PCK_PCK0 AT91_PIN(1,1, 0) // Programmable Clock Output 0
-#define AT91_SPI1_NPCS1XX AT91_PIN(1,1,10) // SPI 1 Chip Select 1
-#define AT91_SPI1_NPCS2XX AT91_PIN(1,1,11) // SPI 1 Chip Select 2
-#define AT91_TC_TCLK0 AT91_PIN(1,1,12) // Timer/Counter 0 Clock Input
-#define AT91_SPI_NPCS1XX AT91_PIN(1,1,13) // SPI 0 Chip Select 1
-#define AT91_SPI_NPCS2XX AT91_PIN(1,1,14) // SPI 0 Chip Select 2
-#define AT91_SPI1_NPCS3XX AT91_PIN(1,1,16) // SPI 1 Chip Select 3
-#define AT91_SPI_NPCS3XX AT91_PIN(1,1,17) // SPI 0 Chip Select 3
-#define AT91_ADC_ADTRG AT91_PIN(1,1,18) // ADC Trigger
-#define AT91_TC_TCLK1X AT91_PIN(1,1,19) // Timer/Counter 1 Clock Input
-#define AT91_PCK_PCK0X AT91_PIN(1,1,20) // Programmable Clock Output 0
-#define AT91_PCK_PCK1XX AT91_PIN(1,1,21) // Programmable Clock Output 1
-#define AT91_PCK_PCK2XX AT91_PIN(1,1,22) // Programmable Clock Output 2
-#define AT91_USART_DCD1 AT91_PIN(1,1,23) // USART 1 Data Carrier Detect
-#define AT91_USART_DSR1 AT91_PIN(1,1,24) // USART 1 Data Set Ready
-#define AT91_USART_DTR1 AT91_PIN(1,1,25) // USART 1 Data Terminal Ready
-#define AT91_USART_RI1 AT91_PIN(1,1,26) // USART 1 Ring Indication
-#define AT91_PWM_PWM0X AT91_PIN(1,1,27) // Pulse Width Modulation #0
-#define AT91_PWM_PWM1X AT91_PIN(1,1,28) // Pulse Width Modulation #1
-#define AT91_PWM_PWM2X AT91_PIN(1,1,29) // Pulse Width Modulation #2
-#define AT91_PWM_PWM3X AT91_PIN(1,1,30) // Pulse Width Modulation #3
-
-// PIO Controller A, peripheral A
-#define AT91_PIO_PSR_RXD0 (1<< 0) // USART 0 Receive Data
-#define AT91_PIO_PSR_TXD0 (1<< 1) // USART 0 Transmit Data
-#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
-#define AT91_PIO_PSR_RTS0 (1<< 3) // USART 0 Request To Send
-#define AT91_PIO_PSR_CTS0 (1<< 4) // USART 0 Clear To Send
-#define AT91_PIO_PSR_RXD1 (1<< 5) // USART 1 Receive Data
-#define AT91_PIO_PSR_TXD1 (1<< 6) // USART 1 Transmit Data
-#define AT91_PIO_PSR_SCK1 (1<< 7) // USART 1 Serial Clock
-#define AT91_PIO_PSR_RTS1 (1<< 8) // USART 1 Request To Send
-#define AT91_PIO_PSR_CTS1 (1<< 9) // USART 1 Clear To Send
-#define AT91_PIO_PSR_TWD (1<<10) // Two Wire Data
-#define AT91_PIO_PSR_TWCK (1<<11) // Two Wire Clock
-#define AT91_PIO_PSR_SPI_NPCS0 (1<<12) // SPI 0 Chip Select 0
-#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
-#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
-#define AT91_PIO_PSR_SPI_NPCS3 (1<<15) // SPI 0 Chip Select 3
-#define AT91_PIO_PSR_SPI_MISO (1<<16) // SPI 0 Master In Slave Out
-#define AT91_PIO_PSR_SPI_MOSI (1<<17) // SPI 0 Master Out Slave In
-#define AT91_PIO_PSR_SPI_SPCK (1<<18) // SPI 0 Clock
-#define AT91_PIO_PSR_CANRX (1<<19) // CAN Receive
-#define AT91_PIO_PSR_CANTX (1<<20) // CAN Transmit
-#define AT91_PIO_PSR_TF (1<<21) // SSC Transmit Frame Sync
-#define AT91_PIO_PSR_TK (1<<22) // SSC Transmit Clock
-#define AT91_PIO_PSR_TD (1<<23) // SSC Transmit Data
-#define AT91_PIO_PSR_RD (1<<24) // SSC Receive Data
-#define AT91_PIO_PSR_RK (1<<25) // SSC Receive Clock
-#define AT91_PIO_PSR_RF (1<<26) // SSC Receive Frame Sync
-#define AT91_PIO_PSR_DRXD (1<<27) // DBGU Receive Data
-#define AT91_PIO_PSR_DTXD (1<<28) // DBGU Transmit Data
-#define AT91_PIO_PSR_FIQ (1<<29) // Fast Interrupt Request
-#define AT91_PIO_PSR_IRQ0 (1<<30) // Interrupt Request 0
-
-//PIO controller A, peripheral B
-#define AT91_PIO_PSR_SPI1_NPCS1 (1<< 2) // SPI 1 Chip Select 1
-#define AT91_PIO_PSR_SPI1_NPCS2 (1<< 3) // SPI 1 Chip Select 2
-#define AT91_PIO_PSR_SPI1_NPCS3 (1<< 4) // SPI 1 Chip Select 3
-#define AT91_PIO_PSR_SPI_NPCS1X (1<< 7) // SPI 0 Chip Select 1
-#define AT91_PIO_PSR_SPI_NPCS2X (1<< 8) // SPI 0 Chip Select 2
-#define AT91_PIO_PSR_SPI_NPCS3X (1<< 9) // SPI 0 Chip Select 3
-#define AT91_PIO_PSR_PCK1 (1<<13) // Programmable Clock Output 1
-#define AT91_PIO_PSR_IRQ1 (1<<14) // Interrupt Request 1
-#define AT91_PIO_PSR_TCLK1 (1<<15) // Timer/Counter 1 Clock Input
-#define AT91_PIO_PSR_SPI1_NPCS0 (1<<21) // SPI 1 Chip Select 0
-#define AT91_PIO_PSR_SPI1_SPCK (1<<22) // SPI 1 Clock
-#define AT91_PIO_PSR_SPI1_MOSI (1<<23) // SPI 1 Master Out Slave In
-#define AT91_PIO_PSR_SPI1_MISO (1<<24) // SPI 0 Master In Slave Out
-#define AT91_PIO_PSR_SPI1_NPCS1X (1<<25) // SPI 1 Chip Select 1
-#define AT91_PIO_PSR_SPI1_NPCS2X (1<<26) // SPI 1 Chip Select 2
-#define AT91_PIO_PSR_PCK3 (1<<27) // Programmable Clock Output 3
-#define AT91_PIO_PSR_SPI1_NPCS3X (1<<29) // SPI 1 Chip Select 3
-#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
-
-//PIO Controller B, Peripheral A
-#define AT91_PIO_PSR_EREFCK (1<< 0) // EMAC Reference Clock
-#define AT91_PIO_PSR_ETXEN (1<< 1) // EMAC Transmit Enable
-#define AT91_PIO_PSR_ETX0 (1<< 2) // EMAC Transmit Data 0
-#define AT91_PIO_PSR_ETX1 (1<< 3) // EMAC Transmit Data 1
-#define AT91_PIO_PSR_ECRS (1<< 4) // EMAC Carrier Sense
-#define AT91_PIO_PSR_ERX0 (1<< 5) // EMAC Receive Data 0
-#define AT91_PIO_PSR_ERX1 (1<< 6) // EMAC Receive Data 1
-#define AT91_PIO_PSR_ERXER (1<< 7) // EMAC Receive Error
-#define AT91_PIO_PSR_EMDC (1<< 8) // EMAC Management Data Clock
-#define AT91_PIO_PSR_EMDIO (1<< 9) // EMAC Management Data IO
-#define AT91_PIO_PSR_ETX2 (1<<10) // EMAC Transmit Data 2
-#define AT91_PIO_PSR_ETX3 (1<<11) // EMAC Transmit Data 3
-#define AT91_PIO_PSR_ETXER (1<<12) // EMAC Transmit Coding Error
-#define AT91_PIO_PSR_ERX2 (1<<13) // EMAC Receive Data 2
-#define AT91_PIO_PSR_ERX3 (1<<14) // EMAC Receive Data 3
-#define AT91_PIO_PSR_ECRSDV (1<<15) // EMAC Carrier Sense And Data Valid
-#define AT91_PIO_PSR_ECOL (1<<16) // EMAC Collision Detected
-#define AT91_PIO_PSR_ERXCK (1<<17) // EMAC Receive Clock
-#define AT91_PIO_PSR_EF100 (1<<18) // EMAC Force 100Mb/s
-#define AT91_PIO_PSR_PWM0 (1<<19) // Pulse Width Modulation #0
-#define AT91_PIO_PSR_PWM1 (1<<20) // Pulse Width Modulation #1
-#define AT91_PIO_PSR_PWM2 (1<<21) // Pulse Width Modulation #2
-#define AT91_PIO_PSR_PWM3 (1<<22) // Pulse Width Modulation #3
-#define AT91_PIO_PSR_TIOA0 (1<<23) // Timer/Counter 0 IO Line A
-#define AT91_PIO_PSR_TIOB0 (1<<24) // Timer/Counter 0 IO Line B
-#define AT91_PIO_PSR_TIOA1 (1<<25) // Timer/Counter 1 IO Line A
-#define AT91_PIO_PSR_TIOB1 (1<<26) // Timer/Counter 1 IO Line B
-#define AT91_PIO_PSR_TIOA2 (1<<27) // Timer/Counter 2 IO Line A
-#define AT91_PIO_PSR_TIOB2 (1<<28) // Timer/Counter 2 IO Line B
-#define AT91_PIO_PSR_PCK1X (1<<29) // Programmable Clock Output 1
-#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
-
-//PIO Controller B Peripheral B
-#define AT91_PIO_PSR_PCK0 (1<< 0) // Programmable Clock Output 0
-#define AT91_PIO_PSR_SPI1_NPCS1XX (1<<10) // SPI 1 Chip Select 1
-#define AT91_PIO_PSR_SPI1_NPCS2XX (1<<11) // SPI 1 Chip Select 2
-#define AT91_PIO_PSR_TCLK0 (1<<12) // Timer/Counter 0 Clock Input
-#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
-#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
-#define AT91_PIO_PSR_SPI1_NPCS3XX (1<<16) // SPI 1 Chip Select 3
-#define AT91_PIO_PSR_SPI_NPCS3XX (1<<17) // SPI 0 Chip Select 3
-#define AT91_PIO_PSR_ADTRG (1<<18) // ADC Trigger
-#define AT91_PIO_PSR_TCLK1X (1<<19) // Timer/Counter 1 Clock Input
-#define AT91_PIO_PSR_PCK0X (1<<20) // Programmable Clock Output 0
-#define AT91_PIO_PSR_PCK1XX (1<<21) // Programmable Clock Output 1
-#define AT91_PIO_PSR_PCK2X (1<<22) // Programmable Clock Output 2
-#define AT91_PIO_PSR_DCD1 (1<<23) // USART 1 Data Carrier Detect
-#define AT91_PIO_PSR_DSR1 (1<<24) // USART 1 Data Set Ready
-#define AT91_PIO_PSR_DTR1 (1<<25) // USART 1 Data Terminal Ready
-#define AT91_PIO_PSR_RI1 (1<<26) // USART 1 Ring Indication
-#define AT91_PIO_PSR_PWM0X (1<<27) // Pulse Width Modulation #0
-#define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1
-#define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2
-#define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3
-#endif // CYGHWR_HAL_ARM_AT91SAM7X
-
-#ifdef CYGHWR_HAL_ARM_AT91SAM7XC
-#error Sorry, still missing. Happy typing
-#endif
-
-#ifdef CYGHWR_HAL_ARM_AT91SAM7SE
-//PIO Controller A Peripheral A
-#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
-#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
-#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
-#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
-#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
-#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
-#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
-#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
-#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
-#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
-#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
-#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
-#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
-#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
-#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
-#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
-#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
-#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
-#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
-#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
-#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
-#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
-#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
-#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
-#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
-#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
-#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
-#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
-#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
-#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
-#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
-#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
-
-//PIO Controller A Peripheral B
-#define AT91_EBI_A0_NBS0 AT91_PIN(0,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
-#define AT91_EBI_A1_NBS2 AT91_PIN(0,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
-#define AT91_EBI_A2 AT91_PIN(0,1, 2) // EBI: Addr 2
-#define AT91_EBI_A3 AT91_PIN(0,1, 3) // EBI: Addr 3
-#define AT91_EBI_A4 AT91_PIN(0,1, 4) // EBI: Addr 4
-#define AT91_EBI_A5 AT91_PIN(0,1, 5) // EBI: Addr 5
-#define AT91_EBI_A6 AT91_PIN(0,1, 6) // EBI: Addr 6
-#define AT91_EBI_A7 AT91_PIN(0,1, 7) // EBI: Addr 7
-#define AT91_EBI_A8 AT91_PIN(0,1, 8) // EBI: Addr 8
-#define AT91_EBI_A9 AT91_PIN(0,1, 9) // EBI: Addr 9
-#define AT91_EBI_A10 AT91_PIN(0,1,10) // EBI: Addr 10
-#define AT91_EBI_A11 AT91_PIN(0,1,11) // EBI: Addr 11
-#define AT91_EBI_A12 AT91_PIN(0,1,12) // EBI: Addr 12
-#define AT91_EBI_A13 AT91_PIN(0,1,13) // EBI: Addr 13
-#define AT91_EBI_A14 AT91_PIN(0,1,14) // EBI: Addr 14
-#define AT91_EBI_A15 AT91_PIN(0,1,15) // EBI: Addr 15
-#define AT91_EBI_A16_BA0 AT91_PIN(0,1,16) // EBI: Addr 16 / SDRAM Bank Sel 0
-#define AT91_EBI_A17_BA1 AT91_PIN(0,1,17) // EBI: Addr 17 / SDRAM Bank Sel 1
-#define AT91_EBI_NBS3_CFIOW AT91_PIN(0,1,18) // EBI: SDRAM Byte Mask 3 /
- // CompactFlash I/O Write Signal
-#define AT91_EBI_NCS4_CFCS0 AT91_PIN(0,1,19) // EBI: Chip Select 4 /
- // CompactFlash Chip Select 0
-#define AT91_EBI_NCS2_CFCS1 AT91_PIN(0,1,20) // EBI: Chip Select 2 /
- // CompactFlash Chip Select 1
-#define AT91_EBI_NCS6_CFCE2 AT91_PIN(0,1,21) // EBI: Chip Select 6 /
- // CompactFlash Chip Enable 2
-#define AT91_EBI_NCS5_CFCE1 AT91_PIN(0,1,22) // EBI: Chip Select 5 /
- // CompactFlash Chip Enable 1
-#define AT91_EBI_NWR1_NBS1_CFIOR \
- AT91_PIN(0,1,23) // EBI: SMC Write 1 /
- // SDRAM Byte Mask 1 /
- // CompactFlash I/O Read Signal
-#define AT91_EBI_SDA10 AT91_PIN(0,1,24) // EBI: SDRAM Address 10
-#define AT91_EBI_SDCKE AT91_PIN(0,1,25) // EBI: SDRAM Clock Enable
-#define AT91_EBI_NCS1_SDCS AT91_PIN(0,1,26) // EBI: Chip Select 1 /
- // SDRAM Controller Chip Select
-#define AT91_EBI_SDWE AT91_PIN(0,1,27) // EBI: SDRAM Write Enable
-#define AT91_EBI_CAS AT91_PIN(0,1,28) // EBI: SDRAM Column Signal
-#define AT91_EBI_RAS AT91_PIN(0,1,29) // EBI: SDRAM Row Signal
-#define AT91_EBI_D30 AT91_PIN(0,1,30) // EBI: Data 30
-#define AT91_EBI_D31 AT91_PIN(0,1,31) // EBI: Data 31
-
-//PIO Controller A Peripheral A
-#define AT91_PIO_PSR_PWM0 (1<< 0) // Pulse Width Modulation 0
-#define AT91_PIO_PSR_PWM1 (1<< 1) // Pulse Width Modulation 1
-#define AT91_PIO_PSR_PWM2 (1<< 2) // Pulse Width Modulation 2
-#define AT91_PIO_PSR_TWD (1<< 3) // Two Wire Data
-#define AT91_PIO_PSR_TWCK (1<< 4) // Two Wire Clock
-#define AT91_PIO_PSR_RXD0 (1<< 5) // USART 0 Receive Data
-#define AT91_PIO_PSR_TXD0 (1<< 6) // USART 0 Transmit Data
-#define AT91_PIO_PSR_RTS0 (1<< 7) // USART 0 Ready To Send
-#define AT91_PIO_PSR_CTS0 (1<< 8) // USART 0 Clear To Send
-#define AT91_PIO_PSR_DRXD (1<< 9) // Debug UART Receive
-#define AT91_PIO_PSR_DTXD (1<<10) // Debug UART Transmit
-#define AT91_PIO_PSR_NPCS0 (1<<11) // SPI Chip Select 0
-#define AT91_PIO_PSR_MISO (1<<12) // SPI Input
-#define AT91_PIO_PSR_MOSI (1<<13) // SPI Output
-#define AT91_PIO_PSR_SPCK (1<<14) // SPI clock
-#define AT91_PIO_PSR_TF (1<<15) // S2C Transmit Frame Sync
-#define AT91_PIO_PSR_TK (1<<16) // S2C Transmit Clock
-#define AT91_PIO_PSR_TD (1<<17) // S2C Transmit Data
-#define AT91_PIO_PSR_RD (1<<18) // S2C Receive Data
-#define AT91_PIO_PSR_RK (1<<19) // S2C Receive Clock
-#define AT91_PIO_PSR_RF (1<<20) // S2C Receive Frame Sync
-#define AT91_PIO_PSR_RXD1 (1<<21) // USART 1 Receive Data
-#define AT91_PIO_PSR_TXD1 (1<<22) // USART 1 Transmit Data
-#define AT91_PIO_PSR_SCK1 (1<<23) // USART 1 Serial Clock
-#define AT91_PIO_PSR_RTS1 (1<<24) // USART 1 Ready To Send
-#define AT91_PIO_PSR_CTS1 (1<<25) // USART 1 Clear To Send
-#define AT91_PIO_PSR_DVD1 (1<<26) // USART 1 Data Carrier Detect
-#define AT91_PIO_PSR_DTR1 (1<<27) // USART 1 Data Terminal Ready
-#define AT91_PIO_PSR_DSR1 (1<<28) // USART 1 Data Set Ready
-#define AT91_PIO_PSR_RI1 (1<<29) // USART 2 Ring Indicator
-#define AT91_PIO_PSR_IRQ1 (1<<30) // Interrupt Request 1
-#define AT91_PIO_PSR_NPCS1 (1<<31) // SPI Chip Select 1
-
-//PIO Controller A Peripheral B
-#define AT91_PIO_PSR_A0_NBS0 (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
-#define AT91_PIO_PSR_A1_NBS2 (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
-#define AT91_PIO_PSR_A2 (1<< 2) // EBI: Address 2
-#define AT91_PIO_PSR_A3 (1<< 3) // EBI: Address 3
-#define AT91_PIO_PSR_A4 (1<< 4) // EBI: Address 4
-#define AT91_PIO_PSR_A5 (1<< 5) // EBI: Address 5
-#define AT91_PIO_PSR_A6 (1<< 6) // EBI: Address 6
-#define AT91_PIO_PSR_A7 (1<< 7) // EBI: Address 7
-#define AT91_PIO_PSR_A8 (1<< 8) // EBI: Address 8
-#define AT91_PIO_PSR_A9 (1<< 9) // EBI: Address 9
-#define AT91_PIO_PSR_A10 (1<<10) // EBI: Address 10
-#define AT91_PIO_PSR_A11 (1<<11) // EBI: Address 11
-#define AT91_PIO_PSR_A12 (1<<12) // EBI: Address 12
-#define AT91_PIO_PSR_A13 (1<<13) // EBI: Address 13
-#define AT91_PIO_PSR_A14 (1<<14) // EBI: Address 14
-#define AT91_PIO_PSR_A15 (1<<15) // EBI: Address 15
-#define AT91_PIO_PSR_A16_BA0 (1<<16) // EBI: Address 16 / SDRAM Bank Sel 0
-#define AT91_PIO_PSR_A17_BA1 (1<<17) // EBI: Address 17 / SDRAM Bank Sel 1
-#define AT91_PIO_PSR_NBS3_CFIOW (1<<18) // EBI: SDRAM Byte Mask 3 /
- // CompactFlash I/O Write Signal
-#define AT91_PIO_PSR_NCS4_CFCS0 (1<<19) // EBI: Chip Select 4 /
- // CompactFlash Chip Select 0
-#define AT91_PIO_PSR_NCS2_CFCS1 (1<<20) // EBI: Chip Select 2 /
- // CompactFlash Chip Select 1
-#define AT91_PIO_PSR_NCS6_CFCE2 (1<<21) // EBI: Chip Select 6 /
- // CompactFlash Chip Enable 2
-#define AT91_PIO_PSR_NCS5_CFCE1 (1<<22) // EBI: Chip Select 5 /
- // CompactFlash Chip Enable 1
-#define AT91_PIO_PSR_NWR1_NBS1_CFIOR \
- (1<<23) // EBI: Write 1 / SDRAM Byte Mask 1 /
- // CompactFlash I/O Read Signal
-#define AT91_PIO_PSR_SDA10 (1<<24) // EBI: SDRAM Address 10
-#define AT91_PIO_PSR_SDCKE (1<<25) // EBI: SDRAM Clock Enable
-#define AT91_PIO_PSR_NCS1_SDCS (1<<26) // EBI: Chip Select 1 /
- // SDRAM Controller Chip Select
-#define AT91_PIO_PSR_SDWE (1<<27) // EBI: SDRAM Write Enable
-#define AT91_PIO_PSR_CAS (1<<28) // EBI: SDRAM Column Signal
-#define AT91_PIO_PSR_RAS (1<<29) // EBI: SDRAM Row Signal
-#define AT91_PIO_PSR_D30 (1<<30) // EBI: Data 30
-#define AT91_PIO_PSR_D31 (1<<31) // EBI: Data 31
-
-//PIO Controller B Peripheral A
-#define AT91_TC_TIOA0 AT91_PIN(1,0, 0) // Timer/Counter 0 IO Line A
-#define AT91_TC_TIOB0 AT91_PIN(1,0, 1) // Timer/Counter 0 IO Line B
-#define AT91_USART_SCK0 AT91_PIN(1,0, 2) // USART 0 Serial Clock
-#define AT91_SPI_NPCS3 AT91_PIN(1,0, 3) // SPI Chip Select 3
-#define AT91_TC_TCLK0 AT91_PIN(1,0, 4) // Timer/Counter 0 Clock Input
-#define AT91_SPI_NPCS3X AT91_PIN(1,0, 5) // SPI Chip Select 3 (again)
-#define AT91_PCK_PCK0 AT91_PIN(1,0, 6) // Programmable Clock Output 0
-#define AT91_PWM_PWM3 AT91_PIN(1,0, 7) // Pulse Width Modulation #3
-#define AT91_ADC_ADTRG AT91_PIN(1,0, 8) // ADC Trigger
-#define AT91_SPI_NPCS1X AT91_PIN(1,0, 9) // SPI Chip Select 1
-#define AT91_SPI_NPCS2 AT91_PIN(1,0,10) // SPI Chip Select 2
-#define AT91_PWM_PWM0X AT91_PIN(1,0,11) // Pulse Width Modulation #0
-#define AT91_PIO_PWM_PWM1X AT91_PIN(1,0,12) // Pulse Width Modulation #1
-#define AT91_PIO_PWM_PWM2X AT91_PIN(1,0,13) // Pulse Width Modulation #2
-#define AT91_PIO_PWM_PWM4X AT91_PIN(1,0,14) // Pulse Width Modulation #4
-#define AT91_TC_TIOA1 AT91_PIN(1,0,15) // Timer/Counter 1 IO Line A
-#define AT91_TC_TIOB1 AT91_PIN(1,0,16) // Timer/Counter 1 IO Line B
-#define AT91_PCK_PCK1 AT91_PIN(1,0,17) // Programmable Clock Output 1
-#define AT91_PCK_PCK2 AT91_PIN(1,0,18) // Programmable Clock Output 2
-#define AT91_INT_FIQ AT91_PIN(1,0,19) // Fast Interrupt Request
-#define AT91_INT_IRQ0 AT91_PIN(1,0,20) // Interrupt Request 0
-#define AT91_PCK_PCK1X AT91_PIN(1,0,21) // Programmable Clock Output 1
-#define AT91_SPI_NPCS3XX AT91_PIN(1,0,22) // SPI Chip Select 3 (yet again)
-#define AT91_PWM_PWM0XX AT91_PIN(1,0,23) // Pulse Width Modulation #0
-#define AT91_PWM_PWM1XX AT91_PIN(1,0,24) // Pulse Width Modulation #1
-#define AT91_PWM_PWM2XX AT91_PIN(1,0,25) // Pulse Width Modulation 2
-#define AT91_TC_TIOA2 AT91_PIN(1,0,26) // Timer/Counter 2 IO Line A
-#define AT91_TC_TIOB2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line B
-#define AT91_TC_TCLK1 AT91_PIN(1,0,28) // External Clock Input 1
-#define AT91_TC_TCLK2 AT91_PIN(1,0,29) // External Clock Input 2
-#define AT91_SPI_NPCS2X AT91_PIN(1,0,30) // SPI Chip Select 2 (again)
-#define AT91_PCK_PCK2X AT91_PIN(1,0,31) // Programmable Clock Output 2
-
-//PIO Controller B Peripheral B
-#define AT91_EBI_A0_NBS0X AT91_PIN(1,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
-#define AT91_EBI_A1_NBS2X AT91_PIN(1,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
-#define AT91_EBI_A2X AT91_PIN(1,1, 2) // EBI: Addr 2
-#define AT91_EBI_A3X AT91_PIN(1,1, 3) // EBI: Addr 3
-#define AT91_EBI_A4X AT91_PIN(1,1, 4) // EBI: Addr 4
-#define AT91_EBI_A5X AT91_PIN(1,1, 5) // EBI: Addr 5
-#define AT91_EBI_A6X AT91_PIN(1,1, 6) // EBI: Addr 6
-#define AT91_EBI_A7X AT91_PIN(1,1, 7) // EBI: Addr 7
-#define AT91_EBI_A8X AT91_PIN(1,1, 8) // EBI: Addr 8
-#define AT91_EBI_A9X AT91_PIN(1,1, 9) // EBI: Addr 9
-#define AT91_EBI_A10X AT91_PIN(1,1,10) // EBI: Addr 10
-#define AT91_EBI_A11X AT91_PIN(1,1,11) // EBI: Addr 11
-#define AT91_EBI_A12X AT91_PIN(1,1,12) // EBI: Addr 12
-#define AT91_EBI_A13X AT91_PIN(1,1,13) // EBI: Addr 13
-#define AT91_EBI_A14X AT91_PIN(1,1,14) // EBI: Addr 14
-#define AT91_EBI_A15X AT91_PIN(1,1,15) // EBI: Addr 15
-#define AT91_EBI_A16_BA0X AT91_PIN(1,1,16) // EBI: Addr 16 /
- // SDRAM Bank Select 0
-#define AT91_EBI_A17_BA1X AT91_PIN(1,1,17) // EBI: Addr 17 /
- // SDRAM Bank Select 1
-#define AT91_EBI_D16 AT91_PIN(1,1,18) // EBI: Data 16
-#define AT91_EBI_D17 AT91_PIN(1,1,19) // EBI: Data 17
-#define AT91_EBI_D18 AT91_PIN(1,1,20) // EBI: Data 18
-#define AT91_EBI_D19 AT91_PIN(1,1,21) // EBI: Data 19
-#define AT91_EBI_D20 AT91_PIN(1,1,22) // EBI: Data 20
-#define AT91_EBI_D21 AT91_PIN(1,1,23) // EBI: Data 21
-#define AT91_EBI_D22 AT91_PIN(1,1,24) // EBI: Data 22
-#define AT91_EBI_D23 AT91_PIN(1,1,25) // EBI: Data 23
-#define AT91_EBI_D24 AT91_PIN(1,1,26) // EBI: Data 24
-#define AT91_EBI_D25 AT91_PIN(1,1,27) // EBI: Data 25
-#define AT91_EBI_D26 AT91_PIN(1,1,28) // EBI: Data 26
-#define AT91_EBI_D27 AT91_PIN(1,1,29) // EBI: Data 27
-#define AT91_EBI_D28 AT91_PIN(1,1,30) // EBI: Data 28
-#define AT91_EBI_D29 AT91_PIN(1,1,31) // EBI: Data 29
-
-//PIO Controller B Peripheral A
-#define AT91_PIO_PSR_TIOA0 (1<< 0) // Timer/Counter 0 IO Line A
-#define AT91_PIO_PSR_TIOB0 (1<< 1) // Timer/Counter 0 IO Line B
-#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
-#define AT91_PIO_PSR_NPCS3 (1<< 3) // SPI Chip Select 3
-#define AT91_PIO_PSR_TCLK0 (1<< 4) // Timer/Counter 0 Clock Input
-#define AT91_PIO_PSR_NPCS3X (1<< 5) // SPI Chip Select 3 (again)
-#define AT91_PIO_PSR_PCK0 (1<< 6) // Programmable Clock Output 0
-#define AT91_PIO_PSR_PWM3 (1<< 7) // Pulse Width Modulation #3
-#define AT91_PIO_PSR_ADTRG (1<< 8) // ADC Trigger
-#define AT91_PIO_PSR_NPCS1X (1<< 9) // SPI Chip Select 1
-#define AT91_PIO_PSR_NPCS2 (1<<10) // SPI Chip Select 2
-#define AT91_PIO_PSR_PWM0X (1<<11) // Pulse Width Modulation #0
-#define AT91_PIO_PSR_PWM1X (1<<12) // Pulse Width Modulation #1
-#define AT91_PIO_PSR_PWM2X (1<<13) // Pulse Width Modulation #2
-#define AT91_PIO_PSR_PWM4X (1<<14) // Pulse Width Modulation #4
-#define AT91_PIO_PSR_TIOA1 (1<<15) // Timer/Counter 1 IO Line A
-#define AT91_PIO_PSR_TIOB1 (1<<16) // Timer/Counter 1 IO Line B
-#define AT91_PIO_PSR_PCK1 (1<<17) // Programmable Clock Output 1
-#define AT91_PIO_PSR_PCK2 (1<<18) // Programmable Clock Output 2
-#define AT91_PIO_PSR_FIQ (1<<19) // Fast Interrupt Request
-#define AT91_PIO_PSR_IRQ0 (1<<20) // Interrupt Request 0
-#define AT91_PIO_PSR_PCK1X (1<<21) // Programmable Clock Output 1
-#define AT91_PIO_PSR_NPCS3XX (1<<22) // SPI Chip Select 3 (yet again)
-#define AT91_PIO_PSR_PWM0XX (1<<23) // Pulse Width Modulation #0
-#define AT91_PIO_PSR_PWM1XX (1<<24) // Pulse Width Modulation #1
-#define AT91_PIO_PSR_PWM2XX (1<<25) // Pulse Width Modulation 2
-#define AT91_PIO_PSR_TIOA2 (1<<26) // Timer/Counter 2 IO Line A
-#define AT91_PIO_PSR_TIOB2 (1<<27) // Timer/Counter 2 IO Line B
-#define AT91_PIO_PSR_TCLK1 (1<<28) // External Clock Input 1
-#define AT91_PIO_PSR_TCLK2 (1<<29) // External Clock Input 2
-#define AT91_PIO_PSR_NPCS2X (1<<30) // SPI Chip Select 2 (again)
-#define AT91_PIO_PSR_PCK2X (1<<31) // Programmable Clock Output 2
-
-//PIO Controller B Peripheral B
-#define AT91_PIO_PSR_NBS0X (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
-#define AT91_PIO_PSR_NBS2X (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
-#define AT91_PIO_PSR_A2X (1<< 2) // EBI: Address 2
-#define AT91_PIO_PSR_A3X (1<< 3) // EBI: Address 3
-#define AT91_PIO_PSR_A4X (1<< 4) // EBI: Address 4
-#define AT91_PIO_PSR_A5X (1<< 5) // EBI: Address 5
-#define AT91_PIO_PSR_A6X (1<< 6) // EBI: Address 6
-#define AT91_PIO_PSR_A7X (1<< 7) // EBI: Address 7
-#define AT91_PIO_PSR_A8X (1<< 8) // EBI: Address 8
-#define AT91_PIO_PSR_A9X (1<< 9) // EBI: Address 9
-#define AT91_PIO_PSR_A10X (1<<10) // EBI: Address 10
-#define AT91_PIO_PSR_A11X (1<<11) // EBI: Address 11
-#define AT91_PIO_PSR_A12X (1<<12) // EBI: Address 12
-#define AT91_PIO_PSR_A13X (1<<13) // EBI: Address 13
-#define AT91_PIO_PSR_A14X (1<<14) // EBI: Address 14
-#define AT91_PIO_PSR_A15X (1<<15) // EBI: Address 15
-#define AT91_PIO_PSR_BA0X (1<<16) // EBI: Address 16 /
- // SDRAM Bank Select 0
-#define AT91_PIO_PSR_BA1X (1<<17) // EBI: Address 17 /
- // SDRAM Bank Select 1
-#define AT91_PIO_PSR_D16 (1<<18) // EBI: Data 16
-#define AT91_PIO_PSR_D17 (1<<19) // EBI: Data 17
-#define AT91_PIO_PSR_D18 (1<<20) // EBI: Data 18
-#define AT91_PIO_PSR_D19 (1<<21) // EBI: Data 19
-#define AT91_PIO_PSR_D20 (1<<22) // EBI: Data 20
-#define AT91_PIO_PSR_D21 (1<<23) // EBI: Data 21
-#define AT91_PIO_PSR_D22 (1<<24) // EBI: Data 22
-#define AT91_PIO_PSR_D23 (1<<25) // EBI: Data 23
-#define AT91_PIO_PSR_D24 (1<<26) // EBI: Data 24
-#define AT91_PIO_PSR_D25 (1<<27) // EBI: Data 25
-#define AT91_PIO_PSR_D26 (1<<28) // EBI: Data 26
-#define AT91_PIO_PSR_D27 (1<<29) // EBI: Data 27
-#define AT91_PIO_PSR_D28 (1<<30) // EBI: Data 28
-#define AT91_PIO_PSR_D29 (1<<31) // EBI: Data 29
-
-//PIO Controller C Peripheral A
-#define AT91_EBI_D0 AT91_PIN(2,0, 0) // EBI: Data 0
-#define AT91_EBI_D1 AT91_PIN(2,0, 1) // EBI: Data 1
-#define AT91_EBI_D2 AT91_PIN(2,0, 2) // EBI: Data 2
-#define AT91_EBI_D3 AT91_PIN(2,0, 3) // EBI: Data 3
-#define AT91_EBI_D4 AT91_PIN(2,0, 4) // EBI: Data 4
-#define AT91_EBI_D5 AT91_PIN(2,0, 5) // EBI: Data 5
-#define AT91_EBI_D6 AT91_PIN(2,0, 6) // EBI: Data 6
-#define AT91_EBI_D7 AT91_PIN(2,0, 7) // EBI: Data 7
-#define AT91_EBI_D8 AT91_PIN(2,0, 8) // EBI: Data 8
-#define AT91_EBI_D9 AT91_PIN(2,0, 9) // EBI: Data 9
-#define AT91_EBI_D10 AT91_PIN(2,0,10) // EBI: Data 10
-#define AT91_EBI_D11 AT91_PIN(2,0,11) // EBI: Data 11
-#define AT91_EBI_D12 AT91_PIN(2,0,12) // EBI: Data 12
-#define AT91_EBI_D13 AT91_PIN(2,0,13) // EBI: Data 13
-#define AT91_EBI_D14 AT91_PIN(2,0,14) // EBI: Data 14
-#define AT91_EBI_D15 AT91_PIN(2,0,15) // EBI: Data 15
-#define AT91_EBI_A18 AT91_PIN(2,0,16) // EBI: Address 18
-#define AT91_EBI_A19 AT91_PIN(2,0,17) // EBI: Address 19
-#define AT91_EBI_A20 AT91_PIN(2,0,18) // EBI: Address 20
-#define AT91_EBI_A21_NANDALE \
- AT91_PIN(2,0,19) // EBI: Address 21 /
- // NAND Flash Address Line Enable
-#define AT91_EBI_A22_REG_NANDCLE \
- AT91_PIN(2,0,20) // EBI: Address 22 /
- // CompactFlash REG Signal /
- // NAND Flash Command Line Enable
-#define AT91_EBI_CFNRW AT91_PIN(2,0,23) // EBI: CF Read Not Write Signal
-
-//PIO Controller C Peripheral B
-#define AT91_USART_RTS1X AT91_PIN(2,1, 8) // USART 1 Ready To Send
-#define AT91_USART_DTR1X AT91_PIN(2,1, 9) // USART 1 Data Terminal Ready
-#define AT91_PCK_PCK0X AT91_PIN(2,1,10) // Programmable Clock Output 0
-#define AT91_PCK_PCK1XX AT91_PIN(2,1,11) // Programmable Clock Output 1
-#define AT91_PCK_PCK2XX AT91_PIN(2,1,12) // Programmable Clock Output 2
-#define AT91_SPI_NPCS1XX AT91_PIN(2,1,14) // SPI Chip Select 1
-#define AT91_EBI_NCS3_NANDCS \
- AT91_PIN(2,1,15) // EBI: Chip Select 3 /
- // NAND Flash Chip Select
-#define AT91_EBI_NWAIT AT91_PIN(2,1,16) // EBI: External Wait Signal
-#define AT91_EBI_NANDOE AT91_PIN(2,1,17) // EBI: NAND Flash Output Enable
-#define AT91_EBI_NANDWE AT91_PIN(2,1,18) // EBI: NAND Flash Write Enable
-#define AT91_EBI_NCS7 AT91_PIN(2,1,20) // EBI: Chip Select 7
-#define AT91_EBI_NWR0_NWE_CFWE \
- AT91_PIN(2,1,21) // EBI: Write 0 /
- // SMC Write Enable /
- // CompactFlash Write Enable
-#define AT91_EBI_NRD_CFOE AT91_PIN(2,1,22) // EBI: SMC Read Enable /
- // CompactFlash Output Enable
-#define AT91_EBI_NCS0 AT91_PIN(2,1,23) // EBI: Chip Select 0
-
-//PIO Controller C Peripheral A
-#define AT91_PIO_PSR_D0 (1<< 0) // EBI: Data 0
-#define AT91_PIO_PSR_D1 (1<< 1) // EBI: Data 1
-#define AT91_PIO_PSR_D2 (1<< 2) // EBI: Data 2
-#define AT91_PIO_PSR_D3 (1<< 3) // EBI: Data 3
-#define AT91_PIO_PSR_D4 (1<< 4) // EBI: Data 4
-#define AT91_PIO_PSR_D5 (1<< 5) // EBI: Data 5
-#define AT91_PIO_PSR_D6 (1<< 6) // EBI: Data 6
-#define AT91_PIO_PSR_D7 (1<< 7) // EBI: Data 7
-#define AT91_PIO_PSR_D8 (1<< 8) // EBI: Data 8
-#define AT91_PIO_PSR_D9 (1<< 9) // EBI: Data 9
-#define AT91_PIO_PSR_D10 (1<<10) // EBI: Data 10
-#define AT91_PIO_PSR_D11 (1<<11) // EBI: Data 11
-#define AT91_PIO_PSR_D12 (1<<12) // EBI: Data 12
-#define AT91_PIO_PSR_D13 (1<<13) // EBI: Data 13
-#define AT91_PIO_PSR_D14 (1<<14) // EBI: Data 14
-#define AT91_PIO_PSR_D15 (1<<15) // EBI: Data 15
-#define AT91_PIO_PSR_A18 (1<<16) // EBI: Address 18
-#define AT91_PIO_PSR_A19 (1<<17) // EBI: Address 19
-#define AT91_PIO_PSR_A20 (1<<18) // EBI: Address 20
-#define AT91_PIO_PSR_NANDALE (1<<19) // EBI: Address 21 /
- // NAND Flash Address Line Enable
-#define AT91_PIO_PSR_NANDCLE (1<<20) // EBI: Address 22 /
- // CompactFlash REG Signal /
- // NAND Flash Command Line Enable
-#define AT91_PIO_PSR_CFNRW (1<<23) // EBI: CF Read Not Write Signal
-
-//PIO Controller C Peripheral B
-#define AT91_PIO_PSR_RTS1X (1<< 8) // USART 1 Ready To Send
-#define AT91_PIO_PSR_DTR1X (1<< 9) // USART 1 Data Terminal Ready
-#define AT91_PIO_PSR_PCK0X (1<<10) // Programmable Clock Output 0
-#define AT91_PIO_PSR_PCK1XX (1<<11) // Programmable Clock Output 1
-#define AT91_PIO_PSR_PCK2XX (1<<12) // Programmable Clock Output 2
-#define AT91_PIO_PSR_NPCS1XX (1<<14) // SPI Chip Select 1
-#define AT91_PIO_PSR_NANDCS (1<<15) // EBI: Chip Select 3 /
- // NAND Flash Chip Select
-#define AT91_PIO_PSR_NWAIT (1<<16) // EBI: External Wait Signal
-#define AT91_PIO_PSR_NANDOE (1<<17) // EBI: NAND Flash Output Enable
-#define AT91_PIO_PSR_NANDWE (1<<18) // EBI: NAND Flash Write Enable
-#define AT91_PIO_PSR_NCS7 (1<<20) // EBI: Chip Select 7
-#define AT91_PIO_PSR_CFWE (1<<21) // EBI: Write 0 / SMC Write Enable /
- // CompactFlash Write Enable
-#define AT91_PIO_PSR_CFOE (1<<22) // EBI: SMC Read Enable /
- // CompactFlash Output Enable
-#define AT91_PIO_PSR_NCS0 (1<<23) // EBI: Chip Select 0
-
-#endif // CYGHWR_HAL_ARM_AT91SAM7SE
-
-#else
-#define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock
-#define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A
-#define AT91_TC_TIOB0 AT91_PIN(0,0, 2) // Timer #0 signal B
-#define AT91_TC_TCLK1 AT91_PIN(0,0, 3) // Timer #1 clock
-#define AT91_TC_TIOA1 AT91_PIN(0,0, 4) // Timer #1 signal A
-#define AT91_TC_TIOB1 AT91_PIN(0,0, 5) // Timer #1 signal B
-#define AT91_TC_TCLK2 AT91_PIN(0,0, 6) // Timer #2 clock
-#define AT91_TC_TIOA2 AT91_PIN(0,0, 7) // Timer #2 signal A
-#define AT91_TC_TIOB2 AT91_PIN(0,0, 8) // Timer #2 signal B
-#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // IRQ #0
-#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // IRQ #1
-#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // IRQ #2
-#define AT91_INT_FIQ AT91_PIN(0,0,12) // FIQ
-#define AT91_USART_SCK0 AT91_PIN(0,0,13) // Serial port #0 clock
-#define AT91_USART_TXD0 AT91_PIN(0,0,14) // Serial port #0 TxD
-#define AT91_USART_RXD0 AT91_PIN(0,0,15) // Serial port #0 RxD
-#define AT91_USART_SCK1 AT91_PIN(0,0,20) // Serial port #1 clock
-#define AT91_USART_TXD1 AT91_PIN(0,0,21) // Serial port #1 TxD
-#define AT91_USART_RXD1 AT91_PIN(0,0,22) // Serial port #1 RxD
-#define AT91_CLK_MCKO AT91_PIN(0,0,25) // Master clock out
-
-#define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock
-#define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A
-#define AT91_PIO_PSR_TIOB0 0x00000004 // Timer #0 signal B
-#define AT91_PIO_PSR_TCLK1 0x00000008 // Timer #1 clock
-#define AT91_PIO_PSR_TIOA1 0x00000010 // Timer #1 signal A
-#define AT91_PIO_PSR_TIOB1 0x00000020 // Timer #1 signal B
-#define AT91_PIO_PSR_TCLK2 0x00000040 // Timer #2 clock
-#define AT91_PIO_PSR_TIOA2 0x00000080 // Timer #2 signal A
-#define AT91_PIO_PSR_TIOB2 0x00000100 // Timer #2 signal B
-#define AT91_PIO_PSR_IRQ0 0x00000200 // IRQ #0
-#define AT91_PIO_PSR_IRQ1 0x00000400 // IRQ #1
-#define AT91_PIO_PSR_IRQ2 0x00000800 // IRQ #2
-#define AT91_PIO_PSR_FIQ 0x00001000 // FIQ
-#define AT91_PIO_PSR_SCK0 0x00002000 // Serial port #0 clock
-#define AT91_PIO_PSR_TXD0 0x00004000 // Serial port #0 TxD
-#define AT91_PIO_PSR_RXD0 0x00008000 // Serial port #0 RxD
-#define AT91_PIO_PSR_P16 0x00010000 // PIO port #16
-#define AT91_PIO_PSR_P17 0x00020000 // PIO port #17
-#define AT91_PIO_PSR_P18 0x00040000 // PIO port #18
-#define AT91_PIO_PSR_P19 0x00080000 // PIO port #19
-#define AT91_PIO_PSR_SCK1 0x00100000 // Serial port #1 clock
-#define AT91_PIO_PSR_TXD1 0x00200000 // Serial port #1 TxD
-#define AT91_PIO_PSR_RXD1 0x00400000 // Serial port #1 RxD
-#define AT91_PIO_PSR_P23 0x00800000 // PIO port #23
-#define AT91_PIO_PSR_P24 0x01000000 // PIO port #24
-#define AT91_PIO_PSR_MCKO 0x02000000 // Master clock out
-#define AT91_PIO_PSR_NCS2 0x04000000 // Chip select #2
-#define AT91_PIO_PSR_NCS3 0x08000000 // Chip select #3
-#define AT91_PIO_PSR_CS7_A20 0x10000000 // Chip select #7 or A20
-#define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21
-#define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22
-#define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23
-#endif
+#include CYGBLD_HAL_AT91_PIO_LAYOUT_H
#define AT91_PIO_OER 0x10 // Output enable
#define AT91_PIO_ODR 0x14 // Output disable
--
1.6.0.4
--
/Evgeniy