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Re: [PATCH] Intel StrataFlash fix for MIPS
- From: Andrew Lunn <andrew at lunn dot ch>
- To: Thomas Koeller <thomas dot koeller at baslerweb dot com>
- Cc: ecos-patches at sources dot redhat dot com
- Date: Fri, 14 Jan 2005 14:57:41 +0100
- Subject: Re: [PATCH] Intel StrataFlash fix for MIPS
- References: <200501141419.25818.thomas.koeller@baslerweb.com>
> Since the processor guarantees execution of load/store operations
> in program order, a dummy read fixes this. It took me a while to
> notice that neither HAL_REORDER_BARRIER() nor HAL_IO_BARRIER()
> (the latter does not even exist for MIPS) address this particular
> problem. AFAICT there is nothing in ecos that does, or am I missing
> something here?
Humm, interesting point. I can kind of understand these macros not
doing what you want. They don't consider instruction fetches as
upsetting the flow of code. Any processor which can do "branch"
prediction could be filling its pipeline with code from the caller,
whch does not work, because its not accessable.
It would be interesting to see what the GCC people say about
this. Maybe we need to add some sort of HAL_FUNCTION_BARRIER macro!
Andrew