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Re: Philips LPC2xxx variant port
Here's the updated patch. Uses accesor macro wrapping a function, to get at lpc_pclk since
that is used by peripherals.Both lpc_pclk and lpc_cclk are static vars now.
Other misc cleanups and fixes were made in addition to those resulting from your observations.
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/ChangeLog
@@ -0,0 +1,44 @@
+2004-09-12 Jani Monoses <jani@iv.ro>
+
+ * src/hal_diag.c:
+ * src/lpc2xxx_misc.c:
+ * include/plf_stub.h:
+ * include/var_io.h:
+ * include/var_arch.h:
+ * include/hal_var_ints.h:
+ * include/hal_diag.h:
+ * include/hal_cache.h:
+ * cdl/hal_arm_lpc2xxx.cdl: New port - based on AT91 variant.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl
@@ -0,0 +1,119 @@
+# ====================================================================
+#
+# hal_arm_lpc.cdl
+#
+# Philips LPC2XXX HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+## Copyright (C) 2004 eCosCentric Limited
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): jani
+# Contributors: gthomas, tkoeller, tdrury, nickg
+# Date: 2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ARM_LPC2XXX {
+ display "Philips LPC2XXX variant HAL"
+ parent CYGPKG_HAL_ARM
+ define_header hal_arm_lpc2xxx.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The LPC2XXX HAL package provides the support needed to run
+ eCos on Philips LPC2XXX based targets."
+
+ compile hal_diag.c lpc2xxx_misc.c
+
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+ implements CYGINT_HAL_ARM_ARCH_ARM7
+ implements CYGINT_HAL_ARM_THUMB_ARCH
+
+ # Let the architectural HAL see this variant's files
+ define_proc {
+ puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_ARCH_H"
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC2XXX {
+ display "LPC2XXX variant used"
+ flavor data
+ default_value {"LPC210x"}
+ legal_values {"LPC210x"
+ "LPC2114" "LPC2119" "LPC2124" "LPC2129" "LPC2132" "LPC2138" "LPC2194"
+ "LPC2212" "LPC2214" "LPC2290" "LPC2292" "LPC2294"}
+ description "The LPC2XXX microcontroller family has several variants,
+ the main differences being the amount of on-chip RAM,
+ flash and peripherals. This option allows the
+ platform HALs to select the specific microcontroller
+ being used."
+ }
+
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ default_value 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ default_value ((CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED) / CYGNUM_HAL_RTC_DENOMINATOR)
+ }
+ }
+
+ cdl_option CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA {
+ display "EXTINT.1 errata workaround"
+ flavor data
+ default_value 0
+ description "On some chips writing to the EXTPOLAR or EXTMODE registers while
+ VPBDIV is non-zero can corrupt the latter.Also reading them will yield incorrect values.
+ Enable this option to work around the problem."
+ }
+}
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/hal_cache.h
@@ -0,0 +1,108 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:
+// Date: 2004-09-08
+// Purpose: Cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+// cache control operations.
+// Usage:
+// #include <cyg/hal/hal_cache.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ (_state_) = 0; \
+ CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ (_state_) = 0; \
+ CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/hal_diag.h
@@ -0,0 +1,84 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+//=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas, tkoeller
+// Date: 2001-07-12
+// Purpose: HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage: #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+//-----------------------------------------------------------------------------
+// LED
+externC void hal_diag_led(int mask);
+
+externC void hal_lpc2xxx_set_leds(int mask);
+
+//-----------------------------------------------------------------------------
+// delay
+
+externC void hal_delay_us(cyg_int32 usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n);
+
+//-----------------------------------------------------------------------------
+// reset
+
+extern void hal_lpc2xxx_reset_cpu(void);
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/hal_var_ints.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+// hal_var_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:
+// Date: 2004-09-12
+// Purpose: Define Interrupt support
+// Description: The interrupt details for the LPC2XXX are defined here.
+// Usage:
+// #include <pkgconf/system.h>
+// #include CYGBLD_HAL_VARIANT_H
+// #include CYGBLD_HAL_VAR_INTS_H
+//
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+#define CYGNUM_HAL_INTERRUPT_WD 0
+#define CYGNUM_HAL_INTERRUPT_SOFT 1
+#define CYGNUM_HAL_INTERRUPT_DCC_RX 2
+#define CYGNUM_HAL_INTERRUPT_DCC_TX 3
+#define CYGNUM_HAL_INTERRUPT_TIMER0 4
+#define CYGNUM_HAL_INTERRUPT_TIMER1 5
+#define CYGNUM_HAL_INTERRUPT_UART0 6
+#define CYGNUM_HAL_INTERRUPT_UART1 7
+#define CYGNUM_HAL_INTERRUPT_PWM0 8
+#define CYGNUM_HAL_INTERRUPT_I2C 9
+#define CYGNUM_HAL_INTERRUPT_SPI0 10
+#define CYGNUM_HAL_INTERRUPT_SPI1 11
+#define CYGNUM_HAL_INTERRUPT_PLL 12
+#define CYGNUM_HAL_INTERRUPT_RTCDEV 13 //actual RTC device not the eCos 'real time clock' interrupt. The latter is on TIMER0.
+#define CYGNUM_HAL_INTERRUPT_EINT0 14
+#define CYGNUM_HAL_INTERRUPT_EINT1 15
+#define CYGNUM_HAL_INTERRUPT_EINT2 16
+#define CYGNUM_HAL_INTERRUPT_EINT3 17
+
+#define CYGNUM_HAL_INTERRUPT_AD 18
+
+#define CYGNUM_HAL_INTERRUPT_CAN 19
+
+#define CYGNUM_HAL_INTERRUPT_CAN1_TX 20
+#define CYGNUM_HAL_INTERRUPT_CAN2_TX 21
+#define CYGNUM_HAL_INTERRUPT_CAN3_TX 22
+#define CYGNUM_HAL_INTERRUPT_CAN4_TX 23
+
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX 26
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX 27
+#define CYGNUM_HAL_INTERRUPT_CAN3_RX 28
+#define CYGNUM_HAL_INTERRUPT_CAN4_RX 29
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (31)
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+__externC cyg_uint32 hal_lpc_get_pclk(void);
+#define CYG_HAL_ARM_LPC2XXX_PCLK() hal_lpc_get_pclk()
+#define CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR(baud) (CYG_HAL_ARM_LPC2XXX_PCLK()/((baud)*16))
+
+//The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+
+__externC void hal_lpc_watchdog_reset(void);
+#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0
+
+#endif // CYGONCE_HAL_VAR_INTS_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/plf_stub.h
@@ -0,0 +1,84 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:jskov, gthomas
+// Date: 2004-10-5
+// Purpose: Platform HAL stub support for LPC2XXX based boards.
+// Usage: #include <cyg/hal/plf_stub.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/var_arch.h
@@ -0,0 +1,75 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+// var_arch.h
+//
+// LPC2XXX variant architecture overrides
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Jonathan Larmour <jifl@eCosCentric.com>
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors: jlarmour,Daniel Neri
+// Date: 2004-10-05
+// Purpose: LPC2XXX variant architecture overrides
+// Description:
+// Usage: #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. These implementations halt the system core clock.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+
+
+#define HAL_IDLE_THREAD_ACTION(_count_) \
+CYG_MACRO_START \
+HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_PCON, CYGARC_HAL_LPC2XXX_REG_PCON_IDL); \
+CYG_MACRO_END
+
+
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/var_io.h
@@ -0,0 +1,572 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jlarmour
+// Contributors:
+// Date: 2004-07-23
+// Purpose: Philips LPC2xxx variant specific registers
+// Description:
+// Usage: #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_arm_lpc2xxx.h> // variant chip model selection.
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Watchdog (WD)
+
+#define CYGARC_HAL_LPC2XXX_REG_WD_BASE 0xE0000000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_WDMOD 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDEN (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDRESET (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDTOF (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDINT (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_WDTC 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_WDFEED 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC1 0xAA
+#define CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC2 0x55
+#define CYGARC_HAL_LPC2XXX_REG_WDTV 0x000C
+
+//=============================================================================
+// Timers (Tx)
+
+#define CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE 0xE0004000
+#define CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE 0xE0008000
+
+// Registers are offsets from base for each timer
+#define CYGARC_HAL_LPC2XXX_REG_TxIR 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_MR0 (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_MR1 (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_MR2 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_MR3 (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_CR0 (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_CR1 (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_CR2 (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_TxIR_CR3 (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_TxTCR 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_ENABLE (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_RESET (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_TxTC 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_TxPR 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_TxPC 0x0010
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR 0x0014
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_INT (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_STOP (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR1_INT (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR1_RESET (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR1_STOP (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR2_INT (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR2_RESET (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR2_STOP (1<<8)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR3_INT (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR3_RESET (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR3_STOP (1<<11)
+#define CYGARC_HAL_LPC2XXX_REG_TxMR0 0x0018
+#define CYGARC_HAL_LPC2XXX_REG_TxMR1 0x001C
+#define CYGARC_HAL_LPC2XXX_REG_TxMR2 0x0020
+#define CYGARC_HAL_LPC2XXX_REG_TxMR3 0x0024
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR 0x0028
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR0_RISE (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR0_FALL (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR0 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR1_RISE (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR1_FALL (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR1 (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2_RISE (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2_FALL (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2 (1<<8)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR3_RISE (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR3_FALL (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR3 (1<<11)
+#define CYGARC_HAL_LPC2XXX_REG_TxCR0 0x002C
+#define CYGARC_HAL_LPC2XXX_REG_TxCR1 0x0030
+#define CYGARC_HAL_LPC2XXX_REG_TxCR2 0x0034
+#define CYGARC_HAL_LPC2XXX_REG_TxCR3 0x0038
+#define CYGARC_HAL_LPC2XXX_REG_TxEMR 0x003C
+#define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM0 (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM1 (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM2 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM3 (1<<3)
+
+//=============================================================================
+// UARTs (Ux)
+
+#define CYGARC_HAL_LPC2XXX_REG_UART0_BASE 0xE000C000
+#define CYGARC_HAL_LPC2XXX_REG_UART1_BASE 0xE0010000
+
+// Registers are offsets from base for each UART
+#define CYGARC_HAL_LPC2XXX_REG_UxRBR 0x0000 // DLAB=0 read
+#define CYGARC_HAL_LPC2XXX_REG_UxTHR 0x0000 // DLAB=0 write
+#define CYGARC_HAL_LPC2XXX_REG_UxDLL 0x0000 // DLAB=1 r/w
+#define CYGARC_HAL_LPC2XXX_REG_UxIER 0x0004 // DLAB=0
+#define CYGARC_HAL_LPC2XXX_REG_UxIER_RXDATA_INT (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_UxIER_THRE_INT (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_UxIER_RXLS_INT (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_U1IER_RXMS_INT (1<<3) // U1 only
+#define CYGARC_HAL_LPC2XXX_REG_UxDLM 0x0004 // DLAB=1
+
+#define CYGARC_HAL_LPC2XXX_REG_UxIIR 0x0008 // read
+#define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR0 (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR1 (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR2 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR3 (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_UxIIR_FIFOS (0xB0)
+
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR 0x0008 // write
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_FIFO_ENA (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_FIFO_RESET (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_TX_FIFO_RESET (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_0 (0x00)
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_1 (0x40)
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_2 (0x80)
+#define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_3 (0xB0)
+
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_5 (0x00)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_6 (0x01)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_7 (0x02)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_8 (0x03)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_STOP_1 (0x00)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_STOP_2 (0x04)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ENA (0x08)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ODD (0x00)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_EVEN (0x10)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ONE (0x20)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ZERO (0x30)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_BREAK_ENA (0x40)
+#define CYGARC_HAL_LPC2XXX_REG_UxLCR_DLAB (0x80)
+
+
+// Modem Control Register is UART1 only
+#define CYGARC_HAL_LPC2XXX_REG_U1MCR 0x0010
+#define CYGARC_HAL_LPC2XXX_REG_U1MCR_DTR (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_U1MCR_RTS (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_U1MCR_LOOPBACK (1<<4)
+
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR 0x0014
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_RDR (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_OE (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_PE (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_FE (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_BI (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_THRE (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_TEMT (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_UxLSR_RX_FIFO_ERR (1<<7)
+
+// Modem Status Register is UART1 only
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR 0x0018
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_DCTS (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_DDSR (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_RI_FALL (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_DDCD (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_CTS (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_DSR (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_RI (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_U1MSR_DCD (1<<7)
+
+#define CYGARC_HAL_LPC2XXX_REG_UxSCR 0x001C
+
+//=============================================================================
+// Pulse Width Modulator (PWM)
+
+#define CYGARC_HAL_LPC2XXX_REG_PWM_BASE 0xE0014000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR0_INT (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR1_INT (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR2_INT (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR3_INT (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR4_INT (1<<8)
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR5_INT (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR6_INT (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_PWMTCR 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_PWMTCR_CTR_ENA (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_PWMTCR_CTR_RESET (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PWMTCR_PWM_ENA (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_PWMTC 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_PWMPR 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_PWMPC 0x0010
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR 0x0014
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR0_INT (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR0_RESET (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR0_STOP (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR1_INT (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR1_RESET (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR1_STOP (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR2_INT (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR2_RESET (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR2_STOP (1<<8)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR3_INT (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR3_RESET (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR3_STOP (1<<11)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR4_INT (1<<12)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR4_RESET (1<<13)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR4_STOP (1<<14)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR5_INT (1<<15)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR5_RESET (1<<16)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR5_STOP (1<<17)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR6_INT (1<<18)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR6_RESET (1<<19)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR6_STOP (1<<20)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR0 0x0018
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR1 0x001C
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR2 0x0020
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR3 0x0024
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR4 0x0040
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR5 0x0044
+#define CYGARC_HAL_LPC2XXX_REG_PWMMR6 0x0048
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR 0x004C
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL1 (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL2 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL3 (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL4 (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL5 (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL6 (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA1 (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA2 (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA3 (1<<11)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA4 (1<<12)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA5 (1<<13)
+#define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA6 (1<<14)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER 0x0050
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M0_ENA (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M1_ENA (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M2_ENA (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M3_ENA (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M4_ENA (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M5_ENA (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_PWMLER_M6_ENA (1<<6)
+
+//=============================================================================
+// I2C (I2)
+
+#define CYGARC_HAL_LPC2XXX_REG_I2_BASE 0xE001C000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_I2CONSET 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_I2CONSET_AA (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONSET_SI (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONSET_STO (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONSET_STA (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONSET_I2EN (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_I2STAT 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_I2STAT_SHIFT 3
+#define CYGARC_HAL_LPC2XXX_REG_I2DAT 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_I2ADR 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_I2ADR_GC (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_I2SCLH 0x0010
+#define CYGARC_HAL_LPC2XXX_REG_I2SCLL 0x0014
+#define CYGARC_HAL_LPC2XXX_REG_I2CONCLR 0x0018
+#define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_AAC (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_SIC (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_STAC (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_I2ENC (1<<6)
+
+//=============================================================================
+// SPI (S)
+
+#define CYGARC_HAL_LPC2XXX_REG_SPI0_BASE 0xE0020000
+#define CYGARC_HAL_LPC2XXX_REG_SPI1_BASE 0xE0030000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_CPHA (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_CPOL (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_MSTR (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_LSBF (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_SPIE (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_ABRT (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_MODF (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_ROVR (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_WCOL (1<<6)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_SPIF (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPDR 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPCCR 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_SPI_SPINT 0x001C
+
+
+//=============================================================================
+// RTC
+
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE 0xE0024000
+
+// Registers are offsets from base of this subsystem
+
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ILR 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ILR_CIF (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ILR_ALF (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CTC 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CCR 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CCR_CLKEN (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CCR_CTCRST (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CIIR 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_RTC_AMR 0x0010
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CTIME0 0x0014
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CTIME1 0x0018
+#define CYGARC_HAL_LPC2XXX_REG_RTC_CTIME2 0x001C
+#define CYGARC_HAL_LPC2XXX_REG_RTC_SEC 0x0020
+#define CYGARC_HAL_LPC2XXX_REG_RTC_MIN 0x0024
+#define CYGARC_HAL_LPC2XXX_REG_RTC_HOUR 0x0028
+#define CYGARC_HAL_LPC2XXX_REG_RTC_DOM 0x002C
+#define CYGARC_HAL_LPC2XXX_REG_RTC_DOW 0x0030
+#define CYGARC_HAL_LPC2XXX_REG_RTC_DOY 0x0034
+#define CYGARC_HAL_LPC2XXX_REG_RTC_MONTH 0x0038
+#define CYGARC_HAL_LPC2XXX_REG_RTC_YEAR 0x003C
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALSEC 0x0060
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALMIN 0x0064
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALHOUR 0x0068
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALDOM 0x006C
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALDOW 0x0070
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALDOY 0x0074
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALMON 0x0078
+#define CYGARC_HAL_LPC2XXX_REG_RTC_ALYEAR 0x007C
+#define CYGARC_HAL_LPC2XXX_REG_RTC_PREINT 0x0080
+#define CYGARC_HAL_LPC2XXX_REG_RTC_PREFRAC 0x0084
+
+//=============================================================================
+// GPIO (IO)
+
+#define CYGARC_HAL_LPC2XXX_REG_IO_BASE 0xE0028000
+
+
+#if defined(CYGHWR_HAL_ARM_LPC2XXX_LPC210x)
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_IOPIN 0x000
+#define CYGARC_HAL_LPC2XXX_REG_IOSET 0x004
+#define CYGARC_HAL_LPC2XXX_REG_IODIR 0x008
+#define CYGARC_HAL_LPC2XXX_REG_IOCLR 0x00C
+
+#else
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_IO0PIN 0x000
+#define CYGARC_HAL_LPC2XXX_REG_IO0SET 0x004
+#define CYGARC_HAL_LPC2XXX_REG_IO0DIR 0x008
+#define CYGARC_HAL_LPC2XXX_REG_IO0CLR 0x00C
+
+#define CYGARC_HAL_LPC2XXX_REG_IO1PIN 0x010
+#define CYGARC_HAL_LPC2XXX_REG_IO1SET 0x014
+#define CYGARC_HAL_LPC2XXX_REG_IO1DIR 0x018
+#define CYGARC_HAL_LPC2XXX_REG_IO1CLR 0x01C
+
+#define CYGARC_HAL_LPC2XXX_REG_IO2PIN 0x020
+#define CYGARC_HAL_LPC2XXX_REG_IO2SET 0x024
+#define CYGARC_HAL_LPC2XXX_REG_IO2DIR 0x028
+#define CYGARC_HAL_LPC2XXX_REG_IO2CLR 0x02C
+
+#define CYGARC_HAL_LPC2XXX_REG_IO3PIN 0x030
+#define CYGARC_HAL_LPC2XXX_REG_IO3SET 0x034
+#define CYGARC_HAL_LPC2XXX_REG_IO3DIR 0x038
+#define CYGARC_HAL_LPC2XXX_REG_IO3CLR 0x03C
+
+#endif
+
+//=============================================================================
+// Pin Connect Block (PIN)
+
+#define CYGARC_HAL_LPC2XXX_REG_PIN_BASE 0xE002C000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_PINSEL0 0x000
+#define CYGARC_HAL_LPC2XXX_REG_PINSEL1 0x004
+#define CYGARC_HAL_LPC2XXX_REG_PINSEL2 0x014
+
+//=============================================================================
+// ADC (AD)
+
+#define CYGARC_HAL_LPC2XXX_REG_AD_BASE 0xE0034000
+
+// Registers are offsets from base of this subsystem
+#define CYGARC_HAL_LPC2XXX_REG_ADCR 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_ADCR_BURST (1<<16)
+#define CYGARC_HAL_LPC2XXX_REG_ADCR_PDN (1<<21)
+#define CYGARC_HAL_LPC2XXX_REG_ADCR_EDGE (1<<27)
+#define CYGARC_HAL_LPC2XXX_REG_ADDR 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_ADDR_OVERRUN (1<<30)
+#define CYGARC_HAL_LPC2XXX_REG_ADDR_DONE (1<<31)
+
+//=============================================================================
+// System Control Block
+
+#define CYGARC_HAL_LPC2XXX_REG_SCB_BASE 0xE01FC000
+
+// Registers are offsets from base of this subsystem
+
+// Memory accelerator module
+#define CYGARC_HAL_LPC2XXX_REG_MAMCR 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_MAMCR_DISABLED 0x00
+#define CYGARC_HAL_LPC2XXX_REG_MAMCR_PARTIAL 0x01
+#define CYGARC_HAL_LPC2XXX_REG_MAMCR_FULL 0x02
+#define CYGARC_HAL_LPC2XXX_REG_MAMTIM 0x0004
+
+// Memory mapping control
+#define CYGARC_HAL_LPC2XXX_REG_MEMMAP 0x0040
+
+// PLL
+#define CYGARC_HAL_LPC2XXX_REG_PLLCON 0x0080
+#define CYGARC_HAL_LPC2XXX_REG_PLLCON_PLLE (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_PLLCON_PLLC (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PLLCFG 0x0084
+#define CYGARC_HAL_LPC2XXX_REG_PLLSTAT 0x0088
+#define CYGARC_HAL_LPC2XXX_REG_PLLSTAT_PLLE 0x100 // (1<<8)
+#define CYGARC_HAL_LPC2XXX_REG_PLLSTAT_PLLC 0x200 // (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_PLLSTAT_PLOCK 0x400 // (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_PLLFEED 0x008C
+
+// Power Control
+#define CYGARC_HAL_LPC2XXX_REG_PCON 0x00C0
+#define CYGARC_HAL_LPC2XXX_REG_PCON_IDL (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_PCON_PD (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP 0x00C4
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_TIM0 (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_TIM1 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_URT0 (1<<3)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_URT1 (1<<4)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_PWM0 (1<<5)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_I2C (1<<7)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_SPI0 (1<<8)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_RTC (1<<9)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_SPI1 (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_PCONP_AD (1<<12)
+
+// VPB Divider
+#define CYGARC_HAL_LPC2XXX_REG_VPBDIV 0x0100
+
+// External interrupt inputs
+#define CYGARC_HAL_LPC2XXX_REG_EXTINT 0x0140
+#define CYGARC_HAL_LPC2XXX_REG_EXTWAKE 0x0144
+#define CYGARC_HAL_LPC2XXX_REG_EXTMODE 0x0148
+#define CYGARC_HAL_LPC2XXX_REG_EXTPOLAR 0x014C
+
+#define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT0 (1<<0)
+#define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT1 (1<<1)
+#define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT2 (1<<2)
+#define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT3 (1<<3)
+
+
+//=============================================================================
+// External Memory Controller
+
+#if defined(CYGHWR_HAL_ARM_LPC2XXX_LPC2212) || \
+ defined(CYGHWR_HAL_ARM_LPC2XXX_LPC2214)
+
+#define CYGARC_HAL_LPC2XXX_REG_BCFG0 0xFFE00000
+#define CYGARC_HAL_LPC2XXX_REG_BCFG1 0xFFE00004
+#define CYGARC_HAL_LPC2XXX_REG_BCFG2 0xFFE00008
+#define CYGARC_HAL_LPC2XXX_REG_BCFG3 0xFFE0000C
+
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_RBLE (1<<10)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_BUSERR (1<<24)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_WPERR (1<<25)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_WP (1<<26)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_BM (1<<27)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_MW_8BIT (0x00000000)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_MW_16BIT (0x10000000)
+#define CYGARC_HAL_LPC2XXX_REG_BCFGx_MW_32BIT (0x20000000)
+
+#endif
+
+//=============================================================================
+// Vectored Interrupt Controller (VIC)
+
+#define CYGARC_HAL_LPC2XXX_REG_VIC_BASE 0xFFFFF000
+
+// Registers are offsets from base of this subsystem
+
+#define CYGARC_HAL_LPC2XXX_REG_VICIRQSTAT 0x0000
+#define CYGARC_HAL_LPC2XXX_REG_VICFIQSTAT 0x0004
+#define CYGARC_HAL_LPC2XXX_REG_VICRAWINTR 0x0008
+#define CYGARC_HAL_LPC2XXX_REG_VICINTSELECT 0x000C
+#define CYGARC_HAL_LPC2XXX_REG_VICINTENABLE 0x0010
+#define CYGARC_HAL_LPC2XXX_REG_VICINTENCLEAR 0x0014
+#define CYGARC_HAL_LPC2XXX_REG_VICSOFTINT 0x0018
+#define CYGARC_HAL_LPC2XXX_REG_VICSOFTINTCLEAR 0x001C
+#define CYGARC_HAL_LPC2XXX_REG_VICPROTECTION 0x0020
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR 0x0030
+#define CYGARC_HAL_LPC2XXX_REG_VICDEFVECTADDR 0x0034
+
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR0 0x0100
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR1 0x0104
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR2 0x0108
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR3 0x010C
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR4 0x0110
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR5 0x0114
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR6 0x0118
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR7 0x011C
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR8 0x0120
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR9 0x0124
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR10 0x0128
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR11 0x012C
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR12 0x0130
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR13 0x0134
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR14 0x0138
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR15 0x013C
+
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL0 0x0200
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL1 0x0204
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL2 0x0208
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL3 0x020C
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL4 0x0210
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL5 0x0214
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL6 0x0218
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL7 0x021C
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL8 0x0220
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL9 0x0224
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL10 0x0228
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL11 0x022C
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL12 0x0230
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL13 0x0234
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL14 0x0238
+#define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL15 0x023C
+
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/src/hal_diag.c
@@ -0,0 +1,318 @@
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors:jskov, gthomas
+// Date: 2001-07-12
+// Purpose: HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+
+#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // interface API
+#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h> // USART registers
+
+//-----------------------------------------------------------------------------
+typedef struct {
+ cyg_uint8* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
+} channel_data_t;
+
+//-----------------------------------------------------------------------------
+static void
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8* base = chan->base;
+ cyg_uint16 divider = CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR(chan->baud_rate);
+ //Set baudrate
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxLCR, CYGARC_HAL_LPC2XXX_REG_UxLCR_DLAB);
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxDLM, divider >> 8);
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxDLL, divider & 0xFF);
+
+ // 8-1-no parity.
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxLCR, CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_8 |
+ CYGARC_HAL_LPC2XXX_REG_UxLCR_STOP_1);
+
+ // Reset and enable FIFO
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxFCR, CYGARC_HAL_LPC2XXX_REG_UxFCR_FIFO_ENA |
+ CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_FIFO_RESET | CYGARC_HAL_LPC2XXX_REG_UxFCR_TX_FIFO_RESET);
+}
+
+void
+cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+ cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+ cyg_uint8 stat;
+ CYGARC_HAL_SAVE_GP();
+
+ do {
+ HAL_READ_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxLSR, stat);
+ } while ((stat & CYGARC_HAL_LPC2XXX_REG_UxLSR_THRE) == 0);
+
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxTHR, c);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8* base = chan->base;
+ cyg_uint8 stat;
+
+ HAL_READ_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxLSR, stat);
+ if ((stat & CYGARC_HAL_LPC2XXX_REG_UxLSR_RDR) == 0)
+ return false;
+
+ HAL_READ_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxRBR, *ch);
+
+ return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
+
+ while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
+}
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+ for(;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+ int ret = 0;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ cyg_hal_plf_serial_init_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxIER, CYGARC_HAL_LPC2XXX_REG_UxIER_RXDATA_INT);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ HAL_WRITE_UINT32(base+CYGARC_HAL_LPC2XXX_REG_UxIER, 0);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ default:
+ break;
+ }
+
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ int res = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint8 c;
+ cyg_uint8 stat;
+ CYGARC_HAL_SAVE_GP();
+
+ *__ctrlc = 0;
+ HAL_READ_UINT32(chan->base+CYGARC_HAL_LPC2XXX_REG_UxLSR, stat);
+ if ( (stat & CYGARC_HAL_LPC2XXX_REG_UxLSR_RDR) != 0 ) {
+
+ HAL_READ_UINT32(chan->base+CYGARC_HAL_LPC2XXX_REG_UxRBR, c);
+ if( cyg_hal_is_break( &c , 1 ) )
+ *__ctrlc = 1;
+
+ res = CYG_ISR_HANDLED;
+ }
+
+ HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+static channel_data_t lpc2xxx_ser_channels[2] = {
+ { (cyg_uint8*)CYGARC_HAL_LPC2XXX_REG_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ { (cyg_uint8*)CYGARC_HAL_LPC2XXX_REG_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}
+};
+
+void
+cyg_hal_plf_serial_init(void)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur;
+
+ cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+ // Init channels
+ cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[0]);
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+ cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[1]);
+#endif
+
+ // Setup procs in the vector table
+
+ // Set channel 0
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[0]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+ // Set channel 1
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[1]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+hal_diag_led(int mask)
+{
+ hal_lpc2xxx_set_leds(mask);
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-31--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
@@ -0,0 +1,304 @@
+/*==========================================================================
+//
+// lpc_misc.c
+//
+// HAL misc variant support code for Philips LPC2xxx
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+// Copyright (C) 2004 eCosCentric Limited
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jani
+// Contributors: gthomas, jskov, nickg, tkoeller
+// Date: 2001-07-12
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // necessary?
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h> // calling interface
+#include <cyg/hal/hal_misc.h> // helper functions
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+#include <cyg/hal/drv_api.h> // HAL ISR support
+#endif
+#include <cyg/hal/var_io.h> // platform registers
+
+static cyg_uint32 lpc_cclk; //CPU clock frequency
+static cyg_uint32 lpc_pclk; //peripheral devices clock speed (equal to, half, or quarter of CPU clock)
+
+cyg_uint32 hal_lpc_get_pclk(void)
+{
+ return lpc_pclk;
+}
+// -------------------------------------------------------------------------
+// Clock support
+// Use TIMER0
+static cyg_uint32 _period;
+
+void hal_clock_initialize(cyg_uint32 period)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+
+ period = period/(lpc_cclk/lpc_pclk);
+
+ // Disable and reset counter
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
+
+ //set prescale register to 0
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxPR, 0);
+
+ // Set up match register
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMR0, period);
+
+ //Reset and generate interrupt on match
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMCR, CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_INT | CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET);
+
+ // Enable counter
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 1);
+}
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxIR, CYGARC_HAL_LPC2XXX_REG_TxIR_MR0); // Clear interrupt
+
+ if (period != _period) {
+ hal_clock_initialize(period);
+ }
+ _period = period;
+
+}
+
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+ cyg_uint32 val;
+
+ HAL_READ_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTC, val);
+ *pvalue = val;
+}
+
+// -------------------------------------------------------------------------
+//
+// Delay for some number of micro-seconds
+// use TIMER1
+//
+void hal_delay_us(cyg_int32 usecs)
+{
+ CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE;
+ cyg_uint32 stat;
+ cyg_uint64 ticks;
+
+ // Calculate how many timer ticks the required number of
+ // microseconds equate to. We do this calculation in 64 bit
+ // arithmetic to avoid overflow.
+ ticks = (((cyg_uint64)usecs) * ((cyg_uint64)lpc_pclk))/1000000LL;
+
+ // Disable and reset counter
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
+
+ //Stop on match
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMR0, ticks);
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMCR, CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_STOP | CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET);
+
+ //set prescale register to 0
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxPR, 0);
+
+ // Enable counter
+ HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 1);
+
+ // Wait for the match
+ do {
+ HAL_READ_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTC, stat);
+ } while (stat < ticks);
+}
+
+// -------------------------------------------------------------------------
+// Hardware init
+
+//Return value of VPBDIV register. According to errata doc
+//we need to read twice consecutively to get correct value
+cyg_uint32 lpc_get_vpbdiv(void)
+{
+ cyg_uint32 div;
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_VPBDIV, div);
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_VPBDIV, div);
+
+ return div;
+}
+
+//Set the two bits in VPBDIV which control peripheral clock division
+//div must be 1,2 or 4
+void lpc_set_vpbdiv(int div)
+{
+ cyg_uint8 orig = lpc_get_vpbdiv();
+
+ //update VPBDIV register
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_VPBDIV, (div % 4) | (orig & 0xFC));
+
+ lpc_pclk = lpc_cclk/div;
+}
+
+void hal_hardware_init(void)
+{
+ lpc_cclk = CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED;
+ lpc_set_vpbdiv(4);
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+}
+
+// -------------------------------------------------------------------------
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+ cyg_uint32 irq_num,irq_stat;
+ // Find out which interrupt caused the IRQ
+ // picks the lowest if there are more.
+ // FIXME:try to make use of the VIC for better latency.
+ // That will probably need changes to vectors.S and other int-related code
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE + CYGARC_HAL_LPC2XXX_REG_VICIRQSTAT, irq_stat);
+ for (irq_num = 0; irq_num < 32; irq_num++)
+ if (irq_stat & (1<<irq_num)) break;
+ // No valid interrrupt source, treat as spurious interrupt
+ if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
+ irq_num = CYGNUM_HAL_INTERRUPT_NONE;
+
+ return irq_num;
+}
+
+// -------------------------------------------------------------------------
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE + CYGARC_HAL_LPC2XXX_REG_VICINTENCLEAR, 1<<vector);
+}
+
+void hal_interrupt_unmask(int vector)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE + CYGARC_HAL_LPC2XXX_REG_VICINTENABLE, 1<<vector);
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE + CYGARC_HAL_LPC2XXX_REG_VICVECTADDR, 0);
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+ cyg_uint32 mode;
+ cyg_uint32 pol;
+ //only external interrupts are configurable
+ CYG_ASSERT(vector <= CYGNUM_HAL_INTERRUPT_EINT3 &&
+ vector >= CYGNUM_HAL_INTERRUPT_EINT0 , "Invalid vector");
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+ //Errata sheet says VPBDIV is corrupted when accessing EXTPOL or EXTMOD
+ //Must be written as 0 and at the end restored to original value
+
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_VPBDIV, 0);
+#endif
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_EXTMODE, mode);
+ HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, pol);
+
+ //map int vector to corresponding bit (0..3)
+ vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+
+ //level or edge
+ if (level) {
+ mode &= ~vector;
+ } else {
+ mode |= vector;
+ }
+
+ //high/low or falling/rising
+ if (up) {
+ pol |= vector;
+ } else {
+ pol &= ~vector;
+ }
+
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_EXTMODE, mode);
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, pol);
+
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+ //we know this was the original value
+ lpc_set_vpbdiv(lpc_cclk/lpc_pclk);
+#endif
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+ CYG_ASSERT(level >= 0 && level <= 15, "Invalid level");
+
+}
+
+// Use the watchdog to generate a reset
+void hal_lpc_watchdog_reset(void)
+{
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE + CYGARC_HAL_LPC2XXX_REG_WDTC, 0xFF);
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE + CYGARC_HAL_LPC2XXX_REG_WDMOD,
+ CYGARC_HAL_LPC2XXX_REG_WDMOD_WDEN | CYGARC_HAL_LPC2XXX_REG_WDMOD_WDRESET);
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE + CYGARC_HAL_LPC2XXX_REG_WDFEED, CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC1); //feed WD with the two magic values
+ HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE + CYGARC_HAL_LPC2XXX_REG_WDFEED, CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC2);
+
+ while(1);
+}
+
+//--------------------------------------------------------------------------
+// EOF lpc_misc.c