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New FR-V ports


Added hal/frv/mb93091 and hal/frv/mb93093 in addition to attached
patch.

--Mark

Index: packages/ecos.db
===================================================================
RCS file: /cvs/ecos/ecos/packages/ecos.db,v
retrieving revision 1.129
diff -u -p -5 -r1.129 ecos.db
--- packages/ecos.db	24 Aug 2004 21:22:49 -0000	1.129
+++ packages/ecos.db	5 Sep 2004 20:50:05 -0000
@@ -708,10 +708,20 @@ package CYGPKG_DEVS_FLASH_FRV_FRV400 {
         description "
            This package contains hardware support for FLASH memory
            on the Fujitsu FRV400 platform."
 }
 
+package CYGPKG_DEVS_FLASH_FRV_PDK403 {
+        alias           { "Fujitsu MB93093 FLASH memory support" flash_mb93093 }
+        directory       devs/flash/frv/pdk403
+        script          flash_frv_pdk403.cdl
+        hardware
+        description "
+           This package contains hardware support for FLASH memory
+           on the Fujitsu MB93093-PD00 Portable Development Kit."
+}
+
 package CYGPKG_DEVS_TOUCH_IPAQ {
 	alias 		{ "Touch screen support for iPAQ" touch_ipaq }
 	directory	devs/touch/arm/ipaq
 	script		touch_ipaq.cdl
 	hardware
@@ -3735,19 +3745,50 @@ package CYGPKG_HAL_FRV_FRV400 {
         description "
 The FRV400 HAL package provides the support needed to run eCos on a FUJITSU
 MB93091 (FR-V 400) eval board."
 }
 
+package CYGPKG_HAL_FRV_MB93091 {
+	alias		{ "FUJITSU development board (FR-V)" mb93091 }
+	directory	hal/frv/mb93091
+	script		hal_frv_mb93091.cdl
+	hardware
+        description "
+The FRV Generic HAL package provides the support needed to run eCos on 
+various FUJITSU FR-V eval boards."
+}
+
+package CYGPKG_HAL_FRV_MB93093 {
+	alias		{ "FUJITSU MB93093-PD00 Portable Development Kit (FR-V)" mb93093 }
+	directory	hal/frv/mb93093
+	script		hal_frv_mb93093.cdl
+	hardware
+        description "
+The MB93093 HAL package provides the support needed to run eCos on 
+the Fujitsu MB93093-PD00 Portable Development Kit board."
+}
+
 package CYGPKG_DEVS_ETH_FRV_FRV400 {
 	alias 		{ "Fujitsu FR-V 400 with 82559 ethernet driver"
 			   devs_eth_frv_frv400 frv400_eth_driver }
 	hardware
 	directory	devs/eth/frv/frv400
 	script		frv400_eth_drivers.cdl
         description     "Ethernet driver for Fujitsu FR-V 400 with Intel
                          i82559 ethernet interfaces."
 }
+
+package CYGPKG_DEVS_ETH_FRV_PDK403 {
+	alias 		{ "Fujitsu MB93093-PD00 with AXL88796 ethernet driver"
+			   devs_eth_frv_pdk403 pdk403_eth_driver }
+	hardware
+	directory	devs/eth/frv/pdk403
+	script		pdk403_eth_drivers.cdl
+        description     "Ethernet driver for Fujitsu MB93093-PD00 Portable
+			 Demonstration Kit with AXL88796 Ethernet device"
+}
+
 # --------------------------------------------------------------------------
 
 # ==========================================================================
 
 # --------------------------------------------------------------------------
@@ -3765,10 +3806,40 @@ target frv400 {
         description "
 The frv400 target provides the packages needed to run eCos on a Fujistu
 development board (FR-V 400)."
 }
 
+target mb93091 {
+	alias { "Fujitsu MB93091 development board (FR-V 4xx,5xx)" MB93091 }
+	packages { CYGPKG_HAL_FRV
+                   CYGPKG_HAL_FRV_MB93091
+                   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_FRV_FRV400
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_ETH_FRV_CB70
+                   CYGPKG_DEVS_FLASH_FRV_FRV400
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+The MB93091 target provides the packages needed to run eCos on a Fujitsu
+MB93091 development board (FR-V 400 etc.)."
+}
+
+target mb93093 {
+	alias { "Fujitsu development board (FR-V 400)" MB93093 }
+	packages { CYGPKG_HAL_FRV
+                   CYGPKG_HAL_FRV_MB93093
+                   CYGPKG_DEVS_ETH_FRV_PDK403
+                   CYGPKG_DEVS_ETH_NS_DP83902A
+                   CYGPKG_DEVS_FLASH_FRV_PDK403
+                   CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+        }
+        description "
+The MB93093 target provides the packages needed to run eCos on a Fujitsu
+MB93090-PD00 Portable Development Kit."
+}
+
 
 
 # --------------------------------------------------------------------------
 # ARM Targets
 
Index: packages/devs/eth/frv/frv400/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/frv/frv400/current/ChangeLog,v
retrieving revision 1.3
diff -u -p -5 -r1.3 ChangeLog
--- packages/devs/eth/frv/frv400/current/ChangeLog	31 May 2002 01:05:54 -0000	1.3
+++ packages/devs/eth/frv/frv400/current/ChangeLog	5 Sep 2004 20:50:07 -0000
@@ -1,5 +1,13 @@
+2004-09-05  Mark Salter      <msalter@redhat.com>
+            David Woodhouse  <dwmw2@redhat.com>
+
+	* include/devs_eth_frv400.inl: Use unsigned char for printing. Check
+	for no MAC address being given.
+	* include/devs_eth_frv400.inl: Read MAC address from ID PROM bytewise.
+	Add 'setmac' RedBoot command for setting the MAC address in the EEPROM.
+
 2002-05-30  Jonathan Larmour  <jlarmour@redhat.com>
 
 	* include/devs_eth_frv400.inl: Use CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
 	instead of CYGPKG_NET where required.
 
Index: packages/devs/eth/frv/frv400/current/include/devs_eth_frv400.inl
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/frv/frv400/current/include/devs_eth_frv400.inl,v
retrieving revision 1.3
diff -u -p -5 -r1.3 devs_eth_frv400.inl
--- packages/devs/eth/frv/frv400/current/include/devs_eth_frv400.inl	31 May 2002 01:05:54 -0000	1.3
+++ packages/devs/eth/frv/frv400/current/include/devs_eth_frv400.inl	5 Sep 2004 20:50:07 -0000
@@ -141,11 +141,11 @@ _frv400_eth_init(dp83902a_priv_data_t *d
         if (esa_ok) {
             memcpy(dp->esa, _esa, sizeof(_esa));
         }
 #else
         // Read ESA from EEPROM
-        DP_OUT(dp->base, DP_DCR, 0x49);  // Wordwide access
+        DP_OUT(dp->base, DP_DCR, 0x48);  // Bytewide access
         DP_OUT(dp->base, DP_RBCH, 0);    // Remote byte count
         DP_OUT(dp->base, DP_RBCL, 0);
         DP_OUT(dp->base, DP_ISR, 0xFF);  // Clear any pending interrupts
         DP_OUT(dp->base, DP_IMR, 0x00);  // Mask all interrupts 
         DP_OUT(dp->base, DP_RCR, 0x20);  // Monitor
@@ -217,10 +217,174 @@ ETH_DRV_SC(dp83902a_sc,
 NETDEVTAB_ENTRY(dp83902a_netdev, 
                 "dp83902a_" CYGDAT_DEVS_ETH_FRV400_ETH0_NAME,
                 dp83902a_init, 
                 &dp83902a_sc);
 
+
+#ifdef CYGPKG_REDBOOT
+
+
+#define EECS (0x80|(1<<3))
+#define EESK (1<<2)
+#define EEDI (1<<1)
+#define EEDO (1<<0)
+#define dprintf(x...) do { } while(0)
+
+
+static int eeprom_cmd(dp83902a_priv_data_t *dp, int cmd, int cmd_len)
+{
+	unsigned retval = 0;
+
+        DP_OUT(dp->base, 1, EECS);
+	CYGACC_CALL_IF_DELAY_US(2000);
+
+	dprintf("Enabled for %08x (%d bits)\n", cmd, cmd_len);
+
+        DP_OUT(dp->base, 1, EECS | EESK);
+	CYGACC_CALL_IF_DELAY_US(2000);
+
+	dprintf("Clock\n");
+
+	/* Shift the command bits out. */
+        do {
+                short databit = (cmd & (1 << cmd_len)) ? EEDI : 0;
+		unsigned char tmp, tmp2;
+                DP_OUT(dp->base, 1, EECS | databit); 
+		CYGACC_CALL_IF_DELAY_US(2000);
+		dprintf("Bit %d ... ", !!(cmd&(1<<cmd_len)));
+                DP_OUT(dp->base, 1, EECS | databit | EESK);
+		CYGACC_CALL_IF_DELAY_US(2000);
+		dprintf(" \b");
+		DP_IN(dp->base, 0, tmp2);
+		DP_IN(dp->base, 1, tmp);
+		CYGACC_CALL_IF_DELAY_US(2000);
+                retval = (retval << 1) | !!(tmp & EEDO);
+		dprintf(" \b");
+		dprintf("Got bit %d (%02x %02x)\n", retval & 1, tmp2, tmp);
+        } while (--cmd_len >= 0);
+        DP_OUT(dp->base, 1, EECS);
+	CYGACC_CALL_IF_DELAY_US(2000);
+	dprintf("Last enb...\n");
+
+        /* Terminate the EEPROM access. */
+        DP_OUT(dp->base, 1, 0x80);
+	CYGACC_CALL_IF_DELAY_US(2000);
+	dprintf("Bye. retval %x\n", retval);
+        return retval;
+}
+
+static void setmac(dp83902a_priv_data_t *dp, unsigned short *newmac)
+{
+	unsigned char old_cr, old_ee;
+	int i;
+
+	DP_IN(dp->base, DP_CR, old_cr);
+	DP_OUT(dp->base, DP_CR, old_cr | 0xc0); // Select page 3.
+	CYGACC_CALL_IF_DELAY_US(2000);
+
+	DP_IN(dp->base, 1, old_ee);
+	DP_OUT(dp->base, 1, 0x80);
+	CYGACC_CALL_IF_DELAY_US(2000);
+
+	/* Write enable */
+	eeprom_cmd(dp, (4<<6) + (0x30), 8);
+
+	for (i=0; i<3; i++) {
+		unsigned adr = i+1;
+		/* Erase word */
+//		eeprom_cmd(dp, (7<<6) + (adr), 8);
+		/* Write word */
+		eeprom_cmd(dp, (5<<22) + (adr<<16) + newmac[i], 24);
+	}
+
+	/* Write disable */
+	eeprom_cmd(dp, (4<<6), 8);
+
+#if 0
+	unsigned long words[16];
+	for (i=0; i<15; i++) {
+		unsigned long cmd = (6<<22) + (i<<16);
+		words[i] = eeprom_cmd(dp, cmd /*6<<23 + (i<<16)*/, 24);
+	}
+
+	for (i=0; i<15; i++) {
+		diag_printf("Words[%d] %08x\n", i, words[i]);
+	}
+#endif
+	DP_OUT(dp->base, 1, old_ee);
+	CYGACC_CALL_IF_DELAY_US(2000);
+	DP_OUT(dp->base, DP_CR, old_cr);
+	CYGACC_CALL_IF_DELAY_US(2000);
+}
+
+
+#include <redboot.h>
+static void do_setmac(int argc, char *argv[]);
+RedBoot_cmd("setmac", 
+            "Set Ethernet MAC address", 
+            "<xx:xx:xx:xx:xx:xx>",
+            do_setmac
+    );
+
+static void 
+do_setmac(int argc, char *argv[])
+{
+	unsigned char *mac = NULL;
+	unsigned char mac_nybble[12];
+	unsigned short mac_word[3];
+	int c, n;
+
+	if (!scan_opts(argc, argv, 1, NULL, 0, (void *)&mac,
+		       OPTION_ARG_TYPE_STR, "<MAC address>"))
+		return;
+
+	if (!mac) {
+		diag_printf("Must supply MAC address\n");
+		return;
+	}
+	for (c=n=0; n<12; c++) {
+		if (mac[c] == ':' && !((c+1) % 3))
+			/* Colon in an allowed place */
+			continue;
+
+		if (mac[c] >= '0' && mac[c] <= '9')
+			mac_nybble[n] = mac[c] - '0';
+ 		else if (mac[c] >= 'A' && mac[c] <= 'F')
+			mac_nybble[n] = mac[c] - 'A' + 10;
+ 		else if (mac[c] >= 'a' && mac[c] <= 'f')
+			mac_nybble[n] = mac[c] - 'a' + 10;
+		else {
+			diag_printf("Invalid MAC address bad char %x\n", mac[c]);
+			return;
+		}
+
+		n++;
+	}
+	if (mac[c] || n!=12 || (mac_nybble[1]&1)) {
+		diag_printf("Invalid MAC address\n");
+		return;
+	}
+	mac_word[0] = (mac_nybble[2] << 12) |
+		      (mac_nybble[3] << 8) |
+		      (mac_nybble[0] << 4) |
+		      (mac_nybble[1]);
+	mac_word[1] = (mac_nybble[6] << 12) |
+		      (mac_nybble[7] << 8) |
+		      (mac_nybble[4] << 4) |
+		      (mac_nybble[5]);
+	mac_word[2] = (mac_nybble[10] << 12) |
+		      (mac_nybble[11] << 8) |
+		      (mac_nybble[8] << 4) |
+		      (mac_nybble[9]);
+
+	diag_printf("Setting MAC address...");
+
+	setmac(&dp83902a_eth0_priv_data, mac_word);
+	diag_printf("... done. Reset to take effect.\n");
+	return;
+}
+#endif /* CYGPKG_REDBOOT */
 #endif // CYGPKG_DEVS_ETH_FRV400_ETH0
 
 #endif // __WANT_DEVS
 
 // --------------------------------------------------------------
Index: packages/devs/eth/frv/pdk403/current/ChangeLog
===================================================================
RCS file: packages/devs/eth/frv/pdk403/current/ChangeLog
diff -N packages/devs/eth/frv/pdk403/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/eth/frv/pdk403/current/ChangeLog	5 Sep 2004 20:50:07 -0000
@@ -0,0 +1,40 @@
+2004-09-09  David Woodhouse  <dwmw2@redhat.com>
+
+	* include/devs_eth_pdk403.inl, src/pdk403_eth_init.c,
+ 	cdl/pdk403_eth_drivers.cdl: New device driver for onboard LAN,
+	based on AX88796 which is (almost) the same as DP8390 (NE2000).
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: packages/devs/eth/frv/pdk403/current/cdl/pdk403_eth_drivers.cdl
===================================================================
RCS file: packages/devs/eth/frv/pdk403/current/cdl/pdk403_eth_drivers.cdl
diff -N packages/devs/eth/frv/pdk403/current/cdl/pdk403_eth_drivers.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/eth/frv/pdk403/current/cdl/pdk403_eth_drivers.cdl	5 Sep 2004 20:50:07 -0000
@@ -0,0 +1,133 @@
+# ====================================================================
+#
+#      pdk403_eth_drivers.cdl
+#
+#      Ethernet drivers - support for AXL88796 Ethernet controller
+#      on the Fujitsu MB93093-PD01 Portable Demonstration Kit.
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      jskov
+# Contributors:   jskov, hmt, gthomas
+# Date:           2001-02-28
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_FRV_PDK403 {
+    display       "PDK403 ethernet driver"
+    description   "
+	Ethernet drivers for Fujitsu MB93093-PD01 PDK."
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_IO_ETH_DRIVERS
+    requires      CYGPKG_DEVS_ETH_NS_DP83902A
+
+    implements    CYGHWR_NET_DRIVER_ETH0
+    include_dir   cyg/io
+
+    compile       -library=libextras.a pdk403_eth_init.c
+
+    # FIXME: This really belongs in the NS DP83902A package
+    cdl_interface CYGINT_DEVS_ETH_NS_DP83902A_REQUIRED {
+        display   "NS DP83902A ethernet driver required"
+    }
+	
+    define_proc {
+        puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_NS_DP83902A_INL <cyg/io/devs_eth_pdk403.inl>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_NS_DP83902A_CFG <pkgconf/devs_eth_frv_pdk403.h>"
+        puts $::cdl_system_header "/*****  ethernet driver proc output end  *****/"
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_PDK403_ETH0 {
+        display       "AXL88796 ethernet port driver"
+        flavor        bool
+        default_value 1
+        description   "
+            This option includes the ethernet device driver for the
+            AXL88796 Ethernet port on the PDK403 board."
+
+        implements CYGINT_DEVS_ETH_NS_DP83902A_REQUIRED
+
+        cdl_option CYGDAT_DEVS_ETH_PDK403_ETH0_NAME {
+            display       "Device name for the ETH0 ethernet driver"
+            flavor        data
+            default_value {"\"eth0\""}
+            description   "
+                This option sets the name of the ethernet device."
+        }
+
+        cdl_component CYGSEM_DEVS_ETH_PDK403_ETH0_SET_ESA {
+            display       "Set the ethernet station address"
+            flavor        bool
+            default_value 0
+            description   "Enabling this option will allow the ethernet
+            station address to be forced to the value set by the
+            configuration.  This may be required if the hardware does
+            not include a serial EEPROM for the ESA."
+            
+            cdl_option CYGDAT_DEVS_ETH_PDK403_ETH0_ESA {
+                display       "The ethernet station address"
+                flavor        data
+                default_value {"{0x08, 0x88, 0x12, 0x34, 0x56, 0x78}"}
+                description   "The ethernet station address"
+            }
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_PDK403_OPTIONS {
+        display "PCMCIA ethernet driver build options"
+        flavor  none
+	no_define
+
+        cdl_option CYGPKG_DEVS_ETH_PDK403_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-D_KERNEL -D__ECOS" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the PCMCIA ethernet driver package.
+                These flags are used in addition
+                to the set of global flags."
+        }
+    }
+}
+
+# EOF pdk403_eth_drivers.cdl
Index: packages/devs/eth/frv/pdk403/current/include/devs_eth_pdk403.inl
===================================================================
RCS file: packages/devs/eth/frv/pdk403/current/include/devs_eth_pdk403.inl
diff -N packages/devs/eth/frv/pdk403/current/include/devs_eth_pdk403.inl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/eth/frv/pdk403/current/include/devs_eth_pdk403.inl	5 Sep 2004 20:50:07 -0000
@@ -0,0 +1,135 @@
+//==========================================================================
+//
+//      devs/eth/frv/pdk403/..../include/devs_eth_pdk403.inl
+//
+//      PDK403 ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jskov, hmt, gthomas
+// Contributors: jskov
+// Date:         2001-02-28
+// Purpose:      PDK403 ethernet defintions
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <cyg/hal/hal_intr.h>           // CYGNUM_HAL_INTERRUPT_ETHR
+#include <cyg/hal/hal_if.h>
+
+#ifdef __WANT_CONFIG
+
+#define CYGHWR_NS_DP83902A_PLF_16BIT_DATA
+#define CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+
+#define CYGHWR_NS_DP83902A_PLF_INIT(dp) cyg_ax88796_eth_init(dp)
+
+#ifndef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+#define CYGHWR_NS_DP83902A_PLF_INT_CLEAR(dp) \
+		cyg_drv_interrupt_acknowledge((dp)->interrupt)
+#endif
+
+#endif // __WANT_CONFIG
+
+#ifdef __WANT_DEVS
+
+#if defined(CYGSEM_DEVS_ETH_PDK403_ETH0_SET_ESA) 
+#if defined(CYGPKG_REDBOOT) 
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+RedBoot_config_option("Network hardware address [MAC]",
+                      lan_esa,
+                      ALWAYS_ENABLED, true,
+                      CONFIG_ESA, 0
+    );
+#endif  // CYGSEM_REDBOOT_FLASH_CONFIG
+#endif  // CYGPKG_REDBOOT
+#include <cyg/hal/hal_if.h>
+#ifndef CONFIG_ESA
+#define CONFIG_ESA 6
+#endif
+#endif
+
+extern void cyg_ax88796_eth_init(dp83902a_priv_data_t *dp);
+
+
+#ifdef CYGPKG_DEVS_ETH_PDK403_ETH0
+
+static dp83902a_priv_data_t dp83902a_eth0_priv_data = { 
+    base : (cyg_uint8*) 0x10000200,  //
+    data : (cyg_uint8*) 0x10000210,  // Filled in at runtime
+    reset: (cyg_uint8*) 0x1000021f,  //
+    interrupt: CYGNUM_HAL_INTERRUPT_LAN,           //
+    tx_buf1: 0x40,          // 
+    tx_buf2: 0x48,          // Buffer layout - change with care
+    rx_buf_start: 0x50,     //
+    rx_buf_end: 0x80,       //
+#ifdef CYGSEM_DEVS_ETH_PDK403_ETH0_SET_ESA
+    esa : CYGDAT_DEVS_ETH_PDK403_ETH0_ESA,
+    hardwired_esa : true,
+#else
+    hardwired_esa : false,
+#endif
+};
+
+ETH_DRV_SC(dp83902a_sc,
+           &dp83902a_eth0_priv_data, // Driver specific data
+           CYGDAT_DEVS_ETH_PDK403_ETH0_NAME,
+           dp83902a_start,
+           dp83902a_stop,
+           dp83902a_control,
+           dp83902a_can_send,
+           dp83902a_send,
+           dp83902a_recv,
+           dp83902a_deliver,     // "pseudoDSR" called from fast net thread
+           dp83902a_poll,        // poll function, encapsulates ISR and DSR
+           dp83902a_int_vector);
+
+NETDEVTAB_ENTRY(dp83902a_netdev, 
+                "dp83902a_" CYGDAT_DEVS_ETH_PDK403_ETH0_NAME,
+                dp83902a_init, 
+                &dp83902a_sc);
+
+#endif // CYGPKG_DEVS_ETH_PDK403_ETH0
+
+#endif // __WANT_DEVS
+
+// --------------------------------------------------------------
+
+// EOF devs_eth_pdk403.inl
Index: packages/devs/eth/frv/pdk403/current/src/pdk403_eth_init.c
===================================================================
RCS file: packages/devs/eth/frv/pdk403/current/src/pdk403_eth_init.c
diff -N packages/devs/eth/frv/pdk403/current/src/pdk403_eth_init.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/eth/frv/pdk403/current/src/pdk403_eth_init.c	5 Sep 2004 20:50:07 -0000
@@ -0,0 +1,189 @@
+//==========================================================================
+//
+//      pdk403_eth_init.c
+//
+//      Ethernet device driver for NS DP83902a ethernet controller
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####BSDCOPYRIGHTBEGIN####
+//
+// -------------------------------------------
+//
+// Portions of this software may have been derived from OpenBSD or other sources,
+// and are covered by the appropriate copyright disclaimers included herein.
+//
+// -------------------------------------------
+//
+//####BSDCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    dwmw2
+// Contributors: 
+// Date:         2003-11-17
+// Purpose:      
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/io_eth_drivers.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/infra/diag.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/io/eth/eth_drv.h>
+#include <cyg/io/eth/netdev.h>
+
+#include <cyg/io/dp83902a.h>
+
+#define _EECLK	0x80
+#define _EEO	0x40
+#define _EEI	0x20
+#define _EECS	0x10
+
+void cyg_ax88796_eth_init(dp83902a_priv_data_t *dp)
+{
+	int i;
+	unsigned char x;
+#if defined(CYGSEM_DEVS_ETH_PDK403_ETH0_SET_ESA) 
+	cyg_bool esa_ok;
+	unsigned char _esa[6];
+#endif
+    
+	/* Reset */
+	DP_IN(dp->base, 0x1f, x);
+
+	/* Wait (but not indefinitely) for RST bit in ISR */
+	for (i=0; i < 10000; i++) {
+		DP_IN(dp->base, DP_ISR, x);
+		if (x & DP_ISR_RESET)
+			goto ready;
+		CYGACC_CALL_IF_DELAY_US(1);
+	}
+	diag_printf("AX88796 at %p not ready after 10ms. Giving up\n",
+		    dp->base);
+	dp->base = 0;
+	return;
+
+ ready:
+	diag_printf("AX88796 at %p, interrupt: %x\n", dp->base, dp->interrupt);
+
+	/* Wait for 2s for link, else power cycle the PHY */
+	for (i=0; i<2000; i++) {
+		DP_IN(dp->base, 0x17, x);
+		if (x&1) {
+			diag_printf("Link OK: %dMbps %s duplex (after %d ms)\n",
+				    x&4?100:10, x&2?"full":"half", i);
+			goto link_ok;
+		}
+		CYGACC_CALL_IF_DELAY_US(1000);
+	}
+	diag_printf("No Ethernet link after 2s, power cycle PHY...");
+
+	// Assert PPDSET to turn off internal PHY, wait 2s, turn it back on again.
+	DP_OUT(dp->base, 0x17, 0x40);
+	CYGACC_CALL_IF_DELAY_US(2000000);
+	DP_OUT(dp->base, 0x17, 0x00);
+	diag_printf("done.\n");
+
+	// Maybe we're not actually connected. Don't wait.
+ link_ok:
+
+#if defined(CYGSEM_DEVS_ETH_PDK403_ETH0_SET_ESA) 
+	esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,         
+					     "lan_esa", _esa, CONFIG_ESA);
+	if (esa_ok) {
+		memcpy(dp->esa, _esa, sizeof(_esa));
+	}
+#else
+	// Send 13 bits of EEPROM read command 0.0110.0000.0000.
+	for (i=0; i < 13; i++) {
+		x = _EECS;
+		if (i == 2 || i == 3)
+			x |= _EEI;
+
+		DP_OUT(dp->base, 0x14, x);
+		CYGACC_CALL_IF_DELAY_US(10);
+
+		DP_OUT(dp->base, 0x14, x | _EECLK);
+		CYGACC_CALL_IF_DELAY_US(10);
+	}
+
+	// Read MAC address
+	for (i=0; i<6; i++) {
+		int j;
+
+		dp->esa[i] = 0;
+		for (j=0; j<8; j++) {
+			DP_OUT(dp->base, 0x14, _EECS);
+			CYGACC_CALL_IF_DELAY_US(10);
+			   
+			DP_OUT(dp->base, 0x14, _EECS | _EECLK);
+			CYGACC_CALL_IF_DELAY_US(10);
+			   
+			DP_IN(dp->base, 0x14, x);
+			   
+			dp->esa[i] <<= 1;
+			dp->esa[i] |= !!(x & _EEO);
+		}
+	}
+	DP_OUT(dp->base, 0x14, _EECS);
+	CYGACC_CALL_IF_DELAY_US(20);
+	DP_OUT(dp->base, 0x14, 0);
+	CYGACC_CALL_IF_DELAY_US(20);
+	if (dp->esa[0] != 0 || dp->esa[1] != 0x0e ||
+	    dp->esa[2] != 0 || dp->esa[3] != 0x50) {
+		/* Bad MAC address. PDK docs say these four bytes should always
+		   be as above */
+		diag_printf("Bad EEPROM MAC address %02x:02x:%02x:%02x:%02x:%02x. Disabling AX88796\n",
+			    dp->esa[0], dp->esa[1], dp->esa[2], dp->esa[3], dp->esa[4], dp->esa[5]);
+		// Turn off PHY and stop chip
+		DP_OUT(dp->base, 0x17, 0x40);
+		dp->base = 0;
+		return;
+	}
+
+	// Set ESA into chip
+	DP_OUT(dp->base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);  // Select page 1
+	for (i = 0; i < 6; i++)
+		DP_OUT(dp->base, DP_P1_PAR0+i, dp->esa[i]);
+
+	DP_OUT(dp->base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);  // Select page 0
+#endif
+}
Index: packages/devs/flash/frv/frv400/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/flash/frv/frv400/current/ChangeLog,v
retrieving revision 1.2
diff -u -p -5 -r1.2 ChangeLog
--- packages/devs/flash/frv/frv400/current/ChangeLog	23 May 2002 23:01:01 -0000	1.2
+++ packages/devs/flash/frv/frv400/current/ChangeLog	5 Sep 2004 20:50:08 -0000
@@ -1,10 +1,15 @@
+2004-09-05  Mark Salter  <msalter@redhat.com>	
+            David Woodhouse  <dwmw2@redhat.com>
+
+	* cdl/flash_frv_frv400.cdl: Build on frvgen too.
+
 //===========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
Index: packages/devs/flash/frv/frv400/current/cdl/flash_frv_frv400.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/flash/frv/frv400/current/cdl/flash_frv_frv400.cdl,v
retrieving revision 1.2
diff -u -p -5 -r1.2 flash_frv_frv400.cdl
--- packages/devs/flash/frv/frv400/current/cdl/flash_frv_frv400.cdl	23 May 2002 23:01:01 -0000	1.2
+++ packages/devs/flash/frv/frv400/current/cdl/flash_frv_frv400.cdl	5 Sep 2004 20:50:08 -0000
@@ -52,11 +52,11 @@
 cdl_package CYGPKG_DEVS_FLASH_FRV_FRV400 {
     display       "Fujitsu FRV400 FLASH memory support"
 
     parent        CYGPKG_IO_FLASH
     active_if	  CYGPKG_IO_FLASH
-    requires	  CYGPKG_HAL_FRV_FRV400
+    requires	  CYGPKG_HAL_FRV_FRV400 || CYGPKG_HAL_FRV_MB93091
 
     implements    CYGHWR_IO_FLASH_DEVICE
 
     compile       frv400_flash.c
 
Index: packages/devs/flash/frv/pdk403/current/ChangeLog
===================================================================
RCS file: packages/devs/flash/frv/pdk403/current/ChangeLog
diff -N packages/devs/flash/frv/pdk403/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/flash/frv/pdk403/current/ChangeLog	5 Sep 2004 20:50:08 -0000
@@ -0,0 +1,38 @@
+2004-09-05  David Woodhouse  <dwmw2@redhat.com>
+
+	* cdl/flash_frv_pdk403.cdl, src/pdk403_flash.c: New port.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: packages/devs/flash/frv/pdk403/current/cdl/flash_frv_pdk403.cdl
===================================================================
RCS file: packages/devs/flash/frv/pdk403/current/cdl/flash_frv_pdk403.cdl
diff -N packages/devs/flash/frv/pdk403/current/cdl/flash_frv_pdk403.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/flash/frv/pdk403/current/cdl/flash_frv_pdk403.cdl	5 Sep 2004 20:50:08 -0000
@@ -0,0 +1,71 @@
+# ====================================================================
+#
+#      flash_frv_pdk403.cdl
+#
+#      FLASH memory - Hardware support on Fujitsu PDK403
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      jskov, gthomas
+# Original data:  jskov
+# Contributors:
+# Date:           2001-09-26
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_FRV_PDK403 {
+    display       "Fujitsu PDK403 FLASH memory support"
+
+    parent        CYGPKG_IO_FLASH
+    active_if	  CYGPKG_IO_FLASH
+    requires	  CYGPKG_HAL_FRV_MB93093
+
+    implements    CYGHWR_IO_FLASH_DEVICE
+
+    compile       pdk403_flash.c
+
+    # Arguably this should do in the generic package
+    # but then there is a logic loop so you can never enable it.
+    cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED {
+        display   "Generic AMD flash driver required"
+    }
+
+    implements    CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
+    requires      CYGHWR_DEVS_FLASH_AMD_AM29LV640
+}
Index: packages/devs/flash/frv/pdk403/current/src/pdk403_flash.c
===================================================================
RCS file: packages/devs/flash/frv/pdk403/current/src/pdk403_flash.c
diff -N packages/devs/flash/frv/pdk403/current/src/pdk403_flash.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/devs/flash/frv/pdk403/current/src/pdk403_flash.c	5 Sep 2004 20:50:08 -0000
@@ -0,0 +1,74 @@
+//==========================================================================
+//
+//      pdk403_flash.c
+//
+//      Flash programming for Fujitsu/AMD device on Fujitsu PDK403
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jskov, gthomas
+// Contributors: jskov
+// Date:         2001-09-26
+// Purpose:      
+// Description:  
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//--------------------------------------------------------------------------
+// Device properties
+
+#define CYGNUM_FLASH_INTERLEAVE	(1)
+#define CYGNUM_FLASH_SERIES	(2)
+#define CYGNUM_FLASH_WIDTH      (16)
+#define CYGNUM_FLASH_BASE 	(0xFF000000)
+
+//static cyg_uint32 plf_flash_base;
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+#define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT  // This feature fails :-(
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_am29xxxxx.inl"
+
+// ------------------------------------------------------------------------
+// EOF pdk403_flash.c
Index: packages/hal/frv/arch/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/arch/current/ChangeLog,v
retrieving revision 1.5
diff -u -p -5 -r1.5 ChangeLog
--- packages/hal/frv/arch/current/ChangeLog	22 Apr 2004 15:26:33 -0000	1.5
+++ packages/hal/frv/arch/current/ChangeLog	5 Sep 2004 20:50:13 -0000
@@ -1,5 +1,34 @@
+2004-09-03  Mark Salter  <msalter@redhat.com>
+2004-09-03  David Woodhouse  <dwmw2@redhat.com>
+
+	* src/vectors.S (reset_vector): Add some debug-only led setting code.
+	* src/redboot_linux_exec.c: Rename auto-variable for clarity.
+	* include/fr-v.h: Add defines for baud clock prescaler.
+	* src/vectors.S: Fix check for PDM bits in potential resume.
+	* src/vectors.S: Handle resume from sleep modes.
+	* src/redboot_linux_exec.c: Fix argv parsing for exec() command.
+	* include/hal_diag.h src/hal_diag.c: Move support for the built-in
+	16550-like chips found on all known implementations of these CPUs 
+	into the arch directory to avoid duplication.
+	* include/fr400.h include/fr500.h include/fr-v.h: Likewise many
+	other register definitions.
+	* src/hal_breakpoint.c: Likewise breakpoint/watchpoint stuff.
+	* cdl/hal_frv.cdl: Changes to reflect the above.
+	* src/vectors.S: Install exception vectors if not defined
+	CYGSEM_HAL_USE_ROM_MONITOR. This way, syscalls and GDB work
+	in RAM RedBoot.
+	* cdl/hal_frv.cdl, src/redboot_linux_exec.c: Exec command.
+	* src/vectors.S, src/context.S, include/hal_arch.h: Save extra GP
+	and FP regs only when they're actually available on this CPU, if
+	multiple CPUs are supported.
+	* cdl/hal_frv.cdl: Disable use of break insn for trap. Remove 
+		seemingly unnecessary option for hardware debugging.
+	* include/hal_arch.h: Add _PSR_CM bit. It's not always hardwired.
+	* src/hal_mk_defs.c: Ditto. Rename _HAL_THREAD_INIT_CONTEXT
+	* src/vectors.S: Some ifdef cleanup, enable _PSR_CM
+	
 2004-04-22  Jani Monoses <jani@iv.ro>
 
 	 * cdl/hal_frv.cdl :
 	 Invoke tail with stricter syntax that works in latest coreutils. 
 
Index: packages/hal/frv/arch/current/cdl/hal_frv.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/arch/current/cdl/hal_frv.cdl,v
retrieving revision 1.3
diff -u -p -5 -r1.3 hal_frv.cdl
--- packages/hal/frv/arch/current/cdl/hal_frv.cdl	22 Apr 2004 15:26:34 -0000	1.3
+++ packages/hal/frv/arch/current/cdl/hal_frv.cdl	5 Sep 2004 20:50:13 -0000
@@ -58,11 +58,11 @@ cdl_package CYGPKG_HAL_FRV {
         The FUJITSU architecture HAL package provides generic
         support for this processor architecture. It is also
         necessary to select a specific target platform HAL
         package."
 
-    compile       hal_misc.c context.S frv_stub.c hal_syscall.c
+    compile       hal_diag.c hal_misc.c context.S frv_stub.c hal_syscall.c
 
     # special rule used to build any include files, etc, used by assembly code
     make -priority 1 {
         frv.inc : <PACKAGE>/src/hal_mk_defs.c
         $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,frv.tmp -o hal_mk_defs.tmp -S $<
@@ -128,30 +128,56 @@ cdl_package CYGPKG_HAL_FRV {
 
     cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
         display       "Number of breakpoints supported by the HAL."
         flavor        data
         default_value 32
+	compile       hal_breakpoint.c
         active_if     CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
         description   "
             This option determines the number of breakpoints supported by the HAL."
     }
 
     cdl_option CYGSEM_HAL_FRV_USE_BREAK_INSTRUCTION {
         display       "Use 'break' for breakpoints."
         flavor        bool
-        default_value 1
+        default_value 0
 	active_if     { CYGINT_HAL_FRV_ARCH_FR500 != 0 }
         requires      CYGNUM_HAL_BREAKPOINT_LIST_SIZE 
         description   "
             Select this option to use the 'break' instruction for breakpoints.
             This option can only be used if the GDB stubs use local breakpoints."
     }
 
-    cdl_option CYGSEM_HAL_FRV_HW_DEBUG {
-        display       "Hardware debug features available"
-        flavor        bool
-        default_value 1
-	active_if     { CYGINT_HAL_FRV_ARCH_FR500 != 0 }
+    cdl_component CYGPKG_REDBOOT_FRV_OPTIONS {
+        display       "Redboot for FR-V options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
         description   "
-            Select this option to enable the use of a hardware debug unit."
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+                                                                                                                           
+        cdl_component CYGSEM_REDBOOT_FRV_LINUX_BOOT {
+            active_if      CYGBLD_BUILD_REDBOOT_WITH_EXEC
+            display        "Support booting Linux via RedBoot"
+            flavor         bool
+            default_value  1
+            description    "
+               This option allows RedBoot to support booting of a Linux kernel."
+            compile -library=libextras.a redboot_linux_exec.c
+ 
+            cdl_option CYGDAT_REDBOOT_FRV_LINUX_BOOT_ENTRY {
+                display        "Default kernel entry address"
+                flavor         data
+                default_value  0xff040000
+            }
+ 
+            cdl_option CYGDAT_REDBOOT_FRV_LINUX_BOOT_COMMAND_LINE {
+                display        "Default COMMAND_LINE"
+                flavor         data
+                default_value  { "" }
+            }
+        }
     }
+
 }
Index: packages/hal/frv/arch/current/include/fr-v.h
===================================================================
RCS file: packages/hal/frv/arch/current/include/fr-v.h
diff -N packages/hal/frv/arch/current/include/fr-v.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/include/fr-v.h	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,183 @@
+//==========================================================================
+//
+//      fr-v.h
+//
+//      HAL misc board support definitions for Fujitsu FR-V chips
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-09-07
+// Purpose:      Platform register definitions
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#ifndef __HAL_FRV_H__
+#define __HAL_FRV_H__ 1
+
+// Common
+
+#if 0
+// Processor status register
+#define _PSR_PIVL_SHIFT 3
+#define _PSR_PIVL_MASK  (0xF<<(_PSR_PIVL_SHIFT))  // Interrupt mask level
+#define _PSR_S          (1<<2)                    // Supervisor state
+#define _PSR_PS         (1<<1)                    // Previous supervisor state
+#define _PSR_ET         (1<<0)                    // Enable interrupts
+#define _PSR_CM		(1<<12)			  // Enable conditionals
+
+// Hardware status register
+#define _HSR0_ICE       (1<<31)                   // Instruction cache enable
+#define _HSR0_DCE       (1<<30)                   // Data cache enable
+#define _HSR0_IMMU      (1<<26)                   // Instruction MMU enable
+#define _HSR0_DMMU      (1<<25)                   // Data MMU enable
+#endif
+// Debug Control Register
+#define _DCR_EBE        (1 << 30) // Exception break enable bit 
+#define _DCR_SE         (1 << 29) // Single-step break enable bit 
+#define _DCR_IBM        (1 << 28) // Instruction Break Mask (disable bit)
+#define _DCR_DRBE0      (1 << 19) // READ dbar0
+#define _DCR_DWBE0      (1 << 18) // WRITE dbar0
+#define _DCR_DDBE0      (1 << 17) // Data-match for access to dbar0
+#define _DCR_DBASE0     (1 << 17) // offset
+#define _DCR_DRBE1      (1 << 16)
+#define _DCR_DWBE1      (1 << 15)
+#define _DCR_DDBE1      (1 << 14)
+#define _DCR_DBASE1     (1 << 14)
+//#define _DCR_DRBE2      (1 << 13) // 2 and 3 not supported in real hardware
+//#define _DCR_DWBE2      (1 << 12)
+//#define _DCR_DDBE2      (1 << 11)
+//#define _DCR_DRBE3      (1 << 10)
+//#define _DCR_DWBE3      (1 << 9)
+//#define _DCR_DDBE3      (1 << 8)
+#define _DCR_IBE0       (1 << 7)
+#define _DCR_IBCE0      (1 << 6)
+#define _DCR_IBE1       (1 << 5)
+#define _DCR_IBCE1      (1 << 4)
+#define _DCR_IBE2       (1 << 3)
+#define _DCR_IBCE2      (1 << 2)
+#define _DCR_IBE3       (1 << 1)
+#define _DCR_IBCE3      (1 << 0)
+
+// Break PSR Save Register
+#define _BPSR_BS	(1 << 12)
+#define _BPSR_BET	(1 << 0)
+
+// Break Request Register
+#define _BRR_EB         (1 << 30)
+#define _BRR_CB         (1 << 29)
+#define _BRR_TB         (1 << 28)
+#define _BRR_DB0        (1 << 11)
+#define _BRR_DB1        (1 << 10)
+#define _BRR_IB0        (1 << 7)
+#define _BRR_IB1        (1 << 6)
+#define _BRR_IB2        (1 << 5)
+#define _BRR_IB3        (1 << 4)
+#define _BRR_CBB        (1 << 3)
+#define _BRR_BB         (1 << 2)
+#define _BRR_SB         (1 << 1)
+#define _BRR_ST         (1 << 0)
+
+// Programmable timers
+#define _FRVGEN_TCSR0   0xFEFF9400                // Timer 0 control/status
+#define _FRVGEN_TCSR1   0xFEFF9408                // Timer 1 control/status
+#define _FRVGEN_TCSR2   0xFEFF9410                // Timer 2 control/status
+#define _FRVGEN_TCxSR_TOUT 0x80                     // Status - TOUT signal 
+#define _FRVGEN_TCTR    0xFEFF9418                // Timer control
+#define _FRVGEN_TCTR_SEL0 (0<<6)                    // Select timer 0
+#define _FRVGEN_TCTR_SEL1 (1<<6)                    // Select timer 1
+#define _FRVGEN_TCTR_SEL2 (2<<6)                    // Select timer 2
+#define _FRVGEN_TCTR_RB   (3<<6)                    // Timer read back
+#define _FRVGEN_TCTR_RB_NCOUNT   (1<<5)                    // Count data suppress
+#define _FRVGEN_TCTR_RB_NSTATUS  (1<<4)                    // Status data suppress
+#define _FRVGEN_TCTR_RB_CTR2     (1<<3)                    // Read data for counter #2
+#define _FRVGEN_TCTR_RB_CTR1     (1<<2)                    // Read data for counter #1
+#define _FRVGEN_TCTR_RB_CTR0     (1<<1)                    // Read data for counter #0
+#define _FRVGEN_TCTR_LATCH (0<<4)                   // Counter latch command
+#define _FRVGEN_TCTR_R8LO  (1<<4)                   // Read low 8 bits
+#define _FRVGEN_TCTR_R8HI  (2<<4)                   // Read high 8 bits
+#define _FRVGEN_TCTR_RLOHI (3<<4)                   // Read/write 8 lo then 8 hi
+#define _FRVGEN_TCTR_MODE0 (0<<1)                   // Mode 0 - terminal interrupt count
+#define _FRVGEN_TCTR_MODE2 (2<<1)                   // Mode 2 - rate generator
+#define _FRVGEN_TCTR_MODE4 (4<<1)                   // Mode 4 - software trigger strobe
+#define _FRVGEN_TCTR_MODE5 (5<<1)                   // Mode 5 - hardware trigger strobe
+#define _FRVGEN_TPRV    0xFEFF9420                // Timer prescale
+#define _FRVGEN_TPRCKSL 0xFEFF9428                // Prescale clock
+#define _FRVGEN_TCKSL0  0xFEFF9430                // Timer 0 clock select
+#define _FRVGEN_TCKSL1  0xFEFF9438                // Timer 1 clock select
+#define _FRVGEN_TCKSL2  0xFEFF9440                // Timer 2 clock select
+
+// Interrupt & clock control
+#define _FRVGEN_CLK_CTRL 0xFEFF9A00               // Clock control
+#define _FRVGEN_CLK_CTRL_P0 (1<<8)                   // division rate of bus and resource clocks
+#define _FRVGEN_IRC_TM0  0xFEFF9800               // Trigger mode 0 register (unused)
+#define _FRVGEN_IRC_TM1  0xFEFF9808               // Trigger mode 1 register
+#define _FRVGEN_IRC_RS   0xFEFF9810               // Request sense
+#define _FRVGEN_IRC_RC   0xFEFF9818               // Request clear
+#define _FRVGEN_IRC_MASK 0xFEFF9820               // Mask
+#define _FRVGEN_IRC_IRL  0xFEFF9828               // Interrupt level read (encoded)
+#define _FRVGEN_IRC_IRR0 0xFEFF9840               // Interrupt routing #0 (unused)
+#define _FRVGEN_IRC_IRR1 0xFEFF9848               // Interrupt routing #1 (unused)
+#define _FRVGEN_IRC_IRR2 0xFEFF9850               // Interrupt routing #2 (unused)
+#define _FRVGEN_IRC_IRR3 0xFEFF9858               // Interrupt routing #3
+#define _FRVGEN_IRC_IRR4 0xFEFF9860               // Interrupt routing #4
+#define _FRVGEN_IRC_IRR5 0xFEFF9868               // Interrupt routing #5
+#define _FRVGEN_IRC_IRR6 0xFEFF9870               // Interrupt routing #6
+#define _FRVGEN_IRC_IRR7 0xFEFF9878               // Interrupt routing #7
+#define _FRVGEN_IRC_ITM0 0xFEFF9880               // Internal trigger mode #0
+#define _FRVGEN_IRC_ITM1 0xFEFF9888               // Internal trigger mode #1
+
+// Serial ports - 16550 compatible
+#define _FRVGEN_UART0   0xFEFF9C00
+#define _FRVGEN_UART1   0xFEFF9C40
+
+// Serial port prescaler
+#define _FRVGEN_UCPSR   0xFEFF9C90
+#define _FRVGEN_UCPVR   0xFEFF9C98
+
+// Reset register
+#define _FRVGEN_HW_RESET_STAT_P (1<<10)              // Last reset was power-on
+#define _FRVGEN_HW_RESET_STAT_H (1<<9)               // Last reset was hard reset
+#define _FRVGEN_HW_RESET_STAT_S (1<<8)               // Last reset was soft reset
+#define _FRVGEN_HW_RESET_HR     (1<<1)               // Force hard reset
+#define _FRVGEN_HW_RESET_SR     (1<<0)               // Force soft reset
+
+#endif // __HAL_FRV_H__
Index: packages/hal/frv/arch/current/include/fr400.h
===================================================================
RCS file: packages/hal/frv/arch/current/include/fr400.h
diff -N packages/hal/frv/arch/current/include/fr400.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/include/fr400.h	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,108 @@
+//==========================================================================
+//
+//      fr400.h
+//
+//      HAL misc board support definitions for Fujitsu FR4xx chips
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-09-07
+// Purpose:      Platform register definitions
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#ifndef __HAL_FR400_H__
+#define __HAL_FR400_H__ 1
+
+// SDRAM Controller
+#define _FRV400_SDRAM_CP  0xFE000400              // Controller protect
+#define _FRV400_SDRAM_CFG 0xFE000410              // Configuration
+#define _FRV400_SDRAM_CTL 0xFE000418              // Control
+#define _FRV400_SDRAM_MS  0xFE000420              // Mode select
+#define _FRV400_SDRAM_STS 0xFE000428              // Status
+#define _FRV400_SDRAM_RCN 0xFE000430              // Refresh control
+#define _FRV400_SDRAM_ART 0xFE000438              // Auto-refresh timer
+#define _FRV400_SDRAM_AN0 0xFE000500              // Address #0
+#define _FRV400_SDRAM_AN1 0xFE000508              // Address #1
+#define _FRV400_SDRAM_BR0 0xFE000E00              // Base register #0
+#define _FRV400_SDRAM_BR1 0xFE000E08              // Base register #1
+#define _FRV400_SDRAM_AM0 0xFE000F00              // Address mask #0
+#define _FRV400_SDRAM_AM1 0xFE000F08              // Address mask #1
+
+// Local bus control
+#define _FRV400_LBUS_CP   0xFE000000              // Controller protect
+#define _FRV400_LBUS_GCR  0xFE000010		  // General Configuration
+#define _FRV400_LBUS_EST  0xFE000020              // Error status
+#define _FRV400_LBUS_EAD  0xFE000028              // Error address
+#define _FRV400_LBUS_CR0  0xFE000100              // Configuration - space #0
+#define _FRV400_LBUS_CR1  0xFE000108              // Configuration - space #1
+#define _FRV400_LBUS_CR2  0xFE000110              // Configuration - space #2
+#define _FRV400_LBUS_CR3  0xFE000118              // Configuration - space #3
+#define _FRV400_LBUS_CR4  0xFE000120              // Configuration - space #4
+#define _FRV400_LBUS_CR5  0xFE000128              // Configuration - space #5
+#define _FRV400_LBUS_CR6  0xFE000130              // Configuration - space #6
+#define _FRV400_LBUS_CR7  0xFE000138              // Configuration - space #7
+#define _FRV400_LBUS_BR0  0xFE000C00              // Slave - base address #0
+#define _FRV400_LBUS_BR1  0xFE000C08              // Slave - base address #1
+#define _FRV400_LBUS_BR2  0xFE000C10              // Slave - base address #2
+#define _FRV400_LBUS_BR3  0xFE000C18              // Slave - base address #3
+#define _FRV400_LBUS_BR4  0xFE000C20              // Slave - base address #4
+#define _FRV400_LBUS_BR5  0xFE000C28              // Slave - base address #5
+#define _FRV400_LBUS_BR6  0xFE000C30              // Slave - base address #6
+#define _FRV400_LBUS_BR7  0xFE000C38              // Slave - base address #7
+#define _FRV400_LBUS_AM0  0xFE000D00              // Slave - address mask #0
+#define _FRV400_LBUS_AM1  0xFE000D08              // Slave - address mask #1
+#define _FRV400_LBUS_AM2  0xFE000D10              // Slave - address mask #2
+#define _FRV400_LBUS_AM3  0xFE000D18              // Slave - address mask #3
+#define _FRV400_LBUS_AM4  0xFE000D20              // Slave - address mask #4
+#define _FRV400_LBUS_AM5  0xFE000D28              // Slave - address mask #5
+#define _FRV400_LBUS_AM6  0xFE000D30              // Slave - address mask #6
+#define _FRV400_LBUS_AM7  0xFE000D38              // Slave - address mask #7
+
+// Reset register
+#define _FRV400_HW_RESET 0xFEFF0500               // Hardware reset
+
+// Some GPIO magic
+#define	_FRV400_GPIO_SIR 0xFEFF0410               // Special input signals
+#define	_FRV400_GPIO_SOR 0xFEFF0418               // Special output signals
+
+#endif // __HAL_FR400_H__
Index: packages/hal/frv/arch/current/include/fr500.h
===================================================================
RCS file: packages/hal/frv/arch/current/include/fr500.h
diff -N packages/hal/frv/arch/current/include/fr500.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/include/fr500.h	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,116 @@
+//==========================================================================
+//
+//      fr500.h
+//
+//      HAL misc board support definitions for Fujitsu FR5xx chips
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-09-07
+// Purpose:      Platform register definitions
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#ifndef __HAL_FR500_H__
+#define __HAL_FR500_H__ 1
+
+
+// SDRAM Controller
+#define _FRV550_SDRAM_CTL  0xFEFF0200              // Control
+#define _FRV550_SDRAM_AMC  0xFEFF0204              // Access mode control
+#define _FRV550_SDRAM_MS   0xFEFF0208              // Mode select
+#define _FRV550_SDRAM_CFG  0xFEFF020C              // Configuration
+#define _FRV550_SDRAM_AN   0xFEFF0210              // Address number
+#define _FRV550_SDRAM_STS  0xFEFF0214              // Status
+#define _FRV550_SDRAM_RCN  0xFEFF0218              // Refresh control
+#define _FRV550_SDRAM_ART  0xFEFF021C              // Auto-refresh timer
+
+#define _FRV550_SDRAM_ARS0 0xFEFF0100              // Address #0
+#define _FRV550_SDRAM_ARS1 0xFEFF0104              // Address #1
+#define _FRV550_SDRAM_ARS2 0xFEFF0108              // Address #2
+#define _FRV550_SDRAM_ARS3 0xFEFF010C              // Address #3
+#define _FRV550_SDRAM_AMK0 0xFEFF0110              // Address mask #0
+#define _FRV550_SDRAM_AMK1 0xFEFF0114              // Address mask #1
+#define _FRV550_SDRAM_AMK2 0xFEFF0118              // Address mask #2
+#define _FRV550_SDRAM_AMK3 0xFEFF011C              // Address mask #3
+
+// Local bus control
+#define _FRV550_LBUS_CP    0xFEFF1000              // Controller protect
+#define _FRV550_LBUS_GCR   0xFEFF1010              // General configuration
+#define _FRV550_LBUS_EST   0xFEFF1020              // Error status
+#define _FRV550_LBUS_EAD   0xFEFF1028              // Error address
+#define _FRV550_LBUS_MAICR 0xFEFF1030              // Master access interval control
+#define _FRV550_LBUS_EMBR  0xFEFF1040              // External master base
+#define _FRV550_LBUS_EMAM  0xFEFF1048              // External master address mask
+#define _FRV550_LBUS_CR0   0xFEFF1100              // Configuration - space #0
+#define _FRV550_LBUS_CR1   0xFEFF1108              // Configuration - space #1
+#define _FRV550_LBUS_CR2   0xFEFF1110              // Configuration - space #2
+#define _FRV550_LBUS_CR3   0xFEFF1118              // Configuration - space #3
+#define _FRV550_LBUS_CR4   0xFEFF1120              // Configuration - space #4
+#define _FRV550_LBUS_CR5   0xFEFF1128              // Configuration - space #5
+#define _FRV550_LBUS_CR6   0xFEFF1130              // Configuration - space #6
+#define _FRV550_LBUS_CR7   0xFEFF1138              // Configuration - space #7
+#define _FRV550_LBUS_BR0   0xFEFF1C00              // Slave - base address #0
+#define _FRV550_LBUS_BR1   0xFEFF1C08              // Slave - base address #1
+#define _FRV550_LBUS_BR2   0xFEFF1C10              // Slave - base address #2
+#define _FRV550_LBUS_BR3   0xFEFF1C18              // Slave - base address #3
+#define _FRV550_LBUS_BR4   0xFEFF1C20              // Slave - base address #4
+#define _FRV550_LBUS_BR5   0xFEFF1C28              // Slave - base address #5
+#define _FRV550_LBUS_BR6   0xFEFF1C30              // Slave - base address #6
+#define _FRV550_LBUS_BR7   0xFEFF1C38              // Slave - base address #7
+#define _FRV550_LBUS_AM0   0xFEFF1D00              // Slave - address mask #0
+#define _FRV550_LBUS_AM1   0xFEFF1D08              // Slave - address mask #1
+#define _FRV550_LBUS_AM2   0xFEFF1D10              // Slave - address mask #2
+#define _FRV550_LBUS_AM3   0xFEFF1D18              // Slave - address mask #3
+#define _FRV550_LBUS_AM4   0xFEFF1D20              // Slave - address mask #4
+#define _FRV550_LBUS_AM5   0xFEFF1D28              // Slave - address mask #5
+#define _FRV550_LBUS_AM6   0xFEFF1D30              // Slave - address mask #6
+#define _FRV550_LBUS_AM7   0xFEFF1D38              // Slave - address mask #7
+
+// Reset register
+#define _FRV550_HW_RESET 0xFEFFF500               // Hardware reset
+
+// Some GPIO magic
+#define _FRV550_GPIO_SIR 0xFEFFF410               // Special input signals
+#define _FRV550_GPIO_SOR 0xFEFFF418               // Special output signals
+
+#endif // __HAL_FR500_H__
Index: packages/hal/frv/arch/current/include/hal_arch.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/arch/current/include/hal_arch.h,v
retrieving revision 1.2
diff -u -p -5 -r1.2 hal_arch.h
--- packages/hal/frv/arch/current/include/hal_arch.h	23 May 2002 23:02:52 -0000	1.2
+++ packages/hal/frv/arch/current/include/hal_arch.h	5 Sep 2004 20:50:13 -0000
@@ -9,11 +9,11 @@
 //
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -55,20 +55,17 @@
 //==========================================================================
 
 #include <pkgconf/hal.h>         // To decide on stack usage
 #include <cyg/infra/cyg_type.h>
 
-#if CYGINT_HAL_FRV_ARCH_FR400 != 0
-#define _NGPR 32
-#define _NFPR 32
-#endif
 #if CYGINT_HAL_FRV_ARCH_FR500 != 0
 #define _NGPR 64
 #define _NFPR 64
-#endif
-
-#ifndef _NGPR
+#elif CYGINT_HAL_FRV_ARCH_FR400 != 0
+#define _NGPR 32
+#define _NFPR 32
+#else
 #error No architecture defined?
 #endif
 
 //--------------------------------------------------------------------------
 // Common "special" register definitions
@@ -77,14 +74,17 @@
 #define _PSR_PIVL_SHIFT 3
 #define _PSR_PIVL_MASK  (0xF<<(_PSR_PIVL_SHIFT))  // Interrupt mask level
 #define _PSR_S          (1<<2)                    // Supervisor state
 #define _PSR_PS         (1<<1)                    // Previous supervisor state
 #define _PSR_ET         (1<<0)                    // Enable interrupts
+#define _PSR_CM		(1<<13)			  // Enable conditionals
 
-#define _PSR_INITIAL (_PSR_S|_PSR_PS|_PSR_ET)     // Supervisor mode, exceptions
+#define _PSR_INITIAL (_PSR_S|_PSR_PS|_PSR_ET|_PSR_CM)     // Supervisor mode, exceptions
 
 // Hardware status register
+#define _HSR0_FRN	(1<<11)
+#define _HSR0_GRN	(1<<10)
 #define _HSR0_ICE       (1<<31)                   // Instruction cache enable
 #define _HSR0_DCE       (1<<30)                   // Data cache enable
 #define _HSR0_IMMU      (1<<26)                   // Instruction MMU enable
 #define _HSR0_DMMU      (1<<25)                   // Data MMU enable
 
@@ -159,11 +159,11 @@ externC int hal_msbindex(int);
 // _sparg_ name of variable containing current sp, will be changed to new sp
 // _thread_ thread object address, passed as argument to entry point
 // _entry_ entry point address.
 // _id_ bit pattern used in initializing registers, for debugging.
 
-#define _HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )             \
+#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )             \
     CYG_MACRO_START                                                             \
     register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) &~15;                          \
     register HAL_SavedRegisters *_regs_;                                        \
     int _i_;                                                                    \
     _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters));       \
Index: packages/hal/frv/arch/current/include/hal_diag.h
===================================================================
RCS file: packages/hal/frv/arch/current/include/hal_diag.h
diff -N packages/hal/frv/arch/current/include/hal_diag.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/include/hal_diag.h	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,94 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, gthomas
+// Contributors: nickg, gthomas
+// Date:         1998-09-11
+// Purpose:      HAL Support for Kernel Diagnostic Routines
+// Description:  Diagnostic routines for use during kernel development.
+// Usage:        #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+/*---------------------------------------------------------------------------*/
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+// Not the best place for this, but ...
+extern void hal_delay_us(cyg_int32 usecs);
+
+#define HAL_DELAY_US(n)          hal_delay_us(n);
+
+#else
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c                                       */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+#define HAL_DIAG_INIT()          hal_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_diag_read_char(&_c_)
+
+#endif
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h                                                         */
+#endif /* CYGONCE_HAL_DIAG_H */
Index: packages/hal/frv/arch/current/src/context.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/arch/current/src/context.S,v
retrieving revision 1.2
diff -u -p -5 -r1.2 context.S
--- packages/hal/frv/arch/current/src/context.S	23 May 2002 23:02:52 -0000	1.2
+++ packages/hal/frv/arch/current/src/context.S	5 Sep 2004 20:50:13 -0000
@@ -6,11 +6,11 @@
 // #
 // #===========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -97,10 +97,16 @@ hal_thread_switch_context:
         sti     gr28,@(sp,_TS_GPR28)
         sti     gr29,@(sp,_TS_GPR29)
         sti     gr30,@(sp,_TS_GPR30)
         sti     gr31,@(sp,_TS_GPR31)
 #if _NGPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400	
+	movsg	HSR0,gr5
+	srli	gr5,#10,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif
         sti     gr32,@(sp,_TS_GPR32)
         sti     gr33,@(sp,_TS_GPR33)
         sti     gr34,@(sp,_TS_GPR34)
         sti     gr35,@(sp,_TS_GPR35)
         sti     gr36,@(sp,_TS_GPR36)
@@ -129,10 +135,11 @@ hal_thread_switch_context:
         sti     gr59,@(sp,_TS_GPR59)
         sti     gr60,@(sp,_TS_GPR60)
         sti     gr61,@(sp,_TS_GPR61)
         sti     gr62,@(sp,_TS_GPR62)
         sti     gr63,@(sp,_TS_GPR63)
+1:	
 #endif        
         movsg   psr,gr4
         sti     gr4,@(sp,_TS_PSR)
         movsg   lr,gr4
         sti     gr4,@(sp,_TS_PC)
@@ -171,41 +178,17 @@ hal_thread_load_context:
         movgs   gr8,ccr
         ldi     @(sp,_TS_LCR),gr8
         movgs   gr8,lcr
         ldi     @(sp,_TS_CCCR),gr8
         movgs   gr8,cccr
-        ldi     @(sp,_TS_GPR2),gr2       // Restore registers
-        ldi     @(sp,_TS_GPR3),gr3
-        ldi     @(sp,_TS_GPR4),gr4
-        ldi     @(sp,_TS_GPR5),gr5
-        ldi     @(sp,_TS_GPR6),gr6
-        ldi     @(sp,_TS_GPR7),gr7
-        ldi     @(sp,_TS_GPR8),gr8
-        ldi     @(sp,_TS_GPR9),gr9
-        ldi     @(sp,_TS_GPR10),gr10
-        ldi     @(sp,_TS_GPR11),gr11
-        ldi     @(sp,_TS_GPR12),gr12
-        ldi     @(sp,_TS_GPR13),gr13
-        ldi     @(sp,_TS_GPR14),gr14
-        ldi     @(sp,_TS_GPR15),gr15
-        ldi     @(sp,_TS_GPR16),gr16
-        ldi     @(sp,_TS_GPR17),gr17
-        ldi     @(sp,_TS_GPR18),gr18
-        ldi     @(sp,_TS_GPR19),gr19
-        ldi     @(sp,_TS_GPR20),gr20
-        ldi     @(sp,_TS_GPR21),gr21
-        ldi     @(sp,_TS_GPR22),gr22
-        ldi     @(sp,_TS_GPR23),gr23
-        ldi     @(sp,_TS_GPR24),gr24
-        ldi     @(sp,_TS_GPR25),gr25
-        ldi     @(sp,_TS_GPR26),gr26
-        ldi     @(sp,_TS_GPR27),gr27
-        ldi     @(sp,_TS_GPR28),gr28
-        ldi     @(sp,_TS_GPR29),gr29
-        ldi     @(sp,_TS_GPR30),gr30
-        ldi     @(sp,_TS_GPR31),gr31
 #if _NGPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400	
+	movsg	HSR0,gr5
+	srli	gr5,#10,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif	
         ldi     @(sp,_TS_GPR32),gr32
         ldi     @(sp,_TS_GPR33),gr33
         ldi     @(sp,_TS_GPR34),gr34
         ldi     @(sp,_TS_GPR35),gr35
         ldi     @(sp,_TS_GPR36),gr36
@@ -234,11 +217,42 @@ hal_thread_load_context:
         ldi     @(sp,_TS_GPR59),gr59
         ldi     @(sp,_TS_GPR60),gr60
         ldi     @(sp,_TS_GPR61),gr61
         ldi     @(sp,_TS_GPR62),gr62
         ldi     @(sp,_TS_GPR63),gr63
+1:	
 #endif        
+        ldi     @(sp,_TS_GPR2),gr2       // Restore registers
+        ldi     @(sp,_TS_GPR3),gr3
+        ldi     @(sp,_TS_GPR4),gr4
+        ldi     @(sp,_TS_GPR5),gr5
+        ldi     @(sp,_TS_GPR6),gr6
+        ldi     @(sp,_TS_GPR7),gr7
+        ldi     @(sp,_TS_GPR8),gr8
+        ldi     @(sp,_TS_GPR9),gr9
+        ldi     @(sp,_TS_GPR10),gr10
+        ldi     @(sp,_TS_GPR11),gr11
+        ldi     @(sp,_TS_GPR12),gr12
+        ldi     @(sp,_TS_GPR13),gr13
+        ldi     @(sp,_TS_GPR14),gr14
+        ldi     @(sp,_TS_GPR15),gr15
+        ldi     @(sp,_TS_GPR16),gr16
+        ldi     @(sp,_TS_GPR17),gr17
+        ldi     @(sp,_TS_GPR18),gr18
+        ldi     @(sp,_TS_GPR19),gr19
+        ldi     @(sp,_TS_GPR20),gr20
+        ldi     @(sp,_TS_GPR21),gr21
+        ldi     @(sp,_TS_GPR22),gr22
+        ldi     @(sp,_TS_GPR23),gr23
+        ldi     @(sp,_TS_GPR24),gr24
+        ldi     @(sp,_TS_GPR25),gr25
+        ldi     @(sp,_TS_GPR26),gr26
+        ldi     @(sp,_TS_GPR27),gr27
+        ldi     @(sp,_TS_GPR28),gr28
+        ldi     @(sp,_TS_GPR29),gr29
+        ldi     @(sp,_TS_GPR30),gr30
+        ldi     @(sp,_TS_GPR31),gr31
         ldi     @(sp,_TS_SP),sp
         rett    #0
 
 // ----------------------------------------------------------------------------
 //  HAL longjmp, setjmp implementations - based on newlib
@@ -264,18 +278,25 @@ hal_setjmp:
 	stdi	gr24, @(gr8,32)
 	stdi	gr26, @(gr8,40)
 	stdi	gr28, @(gr8,48)
 	stdi	gr30, @(gr8,56)
 #if _NGPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400	
+	movsg	HSR0,gr5
+	srli	gr5,#10,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif	
 	stdi	gr48, @(gr8,64)
 	stdi	gr50, @(gr8,72)
 	stdi	gr52, @(gr8,80)
 	stdi	gr54, @(gr8,88)
 	stdi	gr56, @(gr8,96)
 	stdi	gr58, @(gr8,104)
 	stdi	gr60, @(gr8,112)
 	stdi	gr62, @(gr8,120)
+1:	
 #endif
 
 #if _NFPR != 0
 	stdfi	fr16, @(gr8,128)
 	stdfi	fr18, @(gr8,136)
@@ -284,18 +305,25 @@ hal_setjmp:
 	stdfi	fr24, @(gr8,160)
 	stdfi	fr26, @(gr8,168)
 	stdfi	fr28, @(gr8,176)
 	stdfi	fr30, @(gr8,184)
 #if _NFPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400	
+	movsg	HSR0,gr5
+	srli	gr5,#11,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif	
 	stdfi	fr48, @(gr8,192)
 	stdfi	fr50, @(gr8,200)
 	stdfi	fr52, @(gr8,208)
 	stdfi	fr54, @(gr8,216)
 	stdfi	fr56, @(gr8,224)
 	stdfi	fr58, @(gr8,232)
 	stdfi	fr60, @(gr8,240)
 	stdfi	fr62, @(gr8,248)
+1:	
 #endif
 #endif
 
         movsg	lr, gr4
 	sti     gr4, @(gr8,256)
@@ -307,51 +335,66 @@ hal_setjmp:
 .Lend1:
 	.size	hal_setjmp,.Lend1-hal_setjmp
 
 	.global	hal_longjmp
 	.type	hal_longjmp,@function
-hallongjmp:
-	lddi	@(gr8,0), gr16
-	lddi	@(gr8,8), gr18
-	lddi 	@(gr8,16), gr20
-	lddi	@(gr8,24), gr22
-	lddi	@(gr8,32), gr24
-	lddi	@(gr8,40), gr26
-	lddi	@(gr8,48), gr28
-	lddi	@(gr8,56), gr30
-#if _NGPR != 32
-	lddi	@(gr8,64), gr48
-	lddi	@(gr8,72), gr50
-	lddi	@(gr8,80), gr52
-	lddi	@(gr8,88), gr54
-	lddi	@(gr8,96), gr56
-	lddi	@(gr8,104), gr58
-	lddi	@(gr8,112), gr60
-	lddi	@(gr8,120), gr62
-#endif
-
+hal_longjmp:
 #if _NFPR != 0
 	lddfi	@(gr8,128), fr16
 	lddfi	@(gr8,136), fr18
 	lddfi 	@(gr8,144), fr20
 	lddfi	@(gr8,152), fr22
 	lddfi	@(gr8,160), fr24
 	lddfi	@(gr8,168), fr26
 	lddfi	@(gr8,176), fr28
 	lddfi	@(gr8,184), fr30
 #if _NFPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400	
+	movsg	HSR0,gr5
+	srli	gr5,#11,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif	
 	lddfi	@(gr8,192), fr48
 	lddfi	@(gr8,200), fr50
 	lddfi	@(gr8,208), fr52
 	lddfi	@(gr8,216), fr54
 	lddfi	@(gr8,224), fr56
 	lddfi	@(gr8,232), fr58
 	lddfi	@(gr8,240), fr60
 	lddfi	@(gr8,248), fr62
+1:
 #endif
 #endif
 
+#if _NGPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400	
+	movsg	HSR0,gr5
+	srli	gr5,#10,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif	
+	lddi	@(gr8,64), gr48
+	lddi	@(gr8,72), gr50
+	lddi	@(gr8,80), gr52
+	lddi	@(gr8,88), gr54
+	lddi	@(gr8,96), gr56
+	lddi	@(gr8,104), gr58
+	lddi	@(gr8,112), gr60
+	lddi	@(gr8,120), gr62
+1:	
+#endif
+	lddi	@(gr8,0), gr16
+	lddi	@(gr8,8), gr18
+	lddi 	@(gr8,16), gr20
+	lddi	@(gr8,24), gr22
+	lddi	@(gr8,32), gr24
+	lddi	@(gr8,40), gr26
+	lddi	@(gr8,48), gr28
+	lddi	@(gr8,56), gr30
+
+
         ldi     @(gr8,256), gr4
 	movgs   gr4,lr
 
         ldi     @(gr8,260), sp
         ldi     @(gr8,264), fp
Index: packages/hal/frv/arch/current/src/hal_breakpoint.c
===================================================================
RCS file: packages/hal/frv/arch/current/src/hal_breakpoint.c
diff -N packages/hal/frv/arch/current/src/hal_breakpoint.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/src/hal_breakpoint.c	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,479 @@
+//==========================================================================
+//
+//      hal_breakpoint.c
+//
+//      HAL breakpoint/watchpoint code for Fujitsu FR-V
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-09-07
+// Purpose:      HAL board support
+// Description:  Hardware breakpoint/watchpoint support
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+
+
+// ------------------------------------------------------------------------
+//
+// Hardware breakpoint/watchpoint support
+// ======================================
+//
+// Now follows a load of extreme unpleasantness to deal with the totally
+// broken debug model of this device.
+//
+// To modify the special hardware debug registers, it is necessary to put
+// the CPU into "debug mode".  This can only be done by executing a break
+// instruction, or taking a special hardware break event as described by
+// the special hardware debug registers.
+//
+// But once in debug mode, no break is taken, and break instructions are
+// ignored, because we are in debug mode.
+//
+// So we must exit debug mode for normal running, which you can only do via
+// a rett #1 instruction.  Because rett is for returning from traps, it
+// halts the CPU if you do it with traps enabled.  So you have to mess
+// about disabling traps before the rett.  Also, because rett #1 is for
+// returning from a *debug* trap, you can only issue it from debug mode -
+// or it halts the CPU.
+//
+// To be able to set and unset hardware debug breakpoints and watchpoints,
+// we must enter debug mode (via a "break" instruction).  Fortunately, it
+// is possible to return from a "break" remaining in debug mode, using a
+// rett #0, so we can arrange that a break instruction just means "go to
+// debug mode".
+//
+// So we can manipulate the special hardware debug registers by executing a
+// "break", doing the work, then doing the magic sequence to rett #1.
+// These are encapsulated in HAL_FRV_ENTER_DEBUG_MODE() and
+// HAL_FRV_EXIT_DEBUG_MODE() from plf_stub.h
+//
+// So, we get into break_hander() for two reasons:
+//   1) a break instruction.  Detect this and do nothing; return skipping
+//      over the break instruction.  CPU remains in debug mode.
+//   2) a hardware debug trap.  Continue just as for a normal exception;
+//      GDB and the stubs will handle it.  But first, exit debug mode, or
+//      stuff happening in the stubs will go wrong.
+//
+// In order to be certain that we are in debug mode, for performing (2)
+// safely, vectors.S installs a special debug trap handler on vector #255.
+// That's the reason for break_handler() existing as a separate routine.
+// 
+// Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for the
+// FRV_FRVGEN target; while we do use Hardware Debug, we don't use *that*
+// sort of hardware debug, specifically we do not use hardware single-step,
+// because it breaks as soon as we exit debug mode, ie. whilst we are still
+// within the stub.  So in fact defining CYGSEM_HAL_FRV_HW_DEBUG is bad; I
+// guess it is mis-named.
+//
+
+// ------------------------------------------------------------------------
+// First a load of ugly boilerplate for register access.
+#include <cyg/hal/fr-v.h>
+#include <cyg/hal/hal_stub.h>           // HAL_STUB_HW_STOP_NONE et al
+#include <cyg/hal/frv_stub.h>           // register names PC, PSR et al
+#include <cyg/hal/plf_stub.h>           // HAL_FRV_EXIT_DEBUG_MODE()
+
+// First a load of glue
+static inline unsigned get_bpsr(void) {
+    unsigned retval;
+    asm volatile ( "movsg   bpsr,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_bpsr(unsigned val) {
+    asm volatile ( "movgs   %0,bpsr\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dcr(void) {
+    unsigned retval;
+    asm volatile ( "movsg   dcr,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dcr(unsigned val) {
+    asm volatile ( "movgs   %0,dcr\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_brr(void) {
+    unsigned retval;
+    asm volatile ( "movsg   brr,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_brr(unsigned val) {
+    asm volatile ( "movgs   %0,brr\n" : /* no outputs */  : "r" (val) );}
+
+// Four Instruction Break Address Registers
+static inline unsigned get_ibar0(void) {
+    unsigned retval;
+    asm volatile ( "movsg   ibar0,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_ibar0(unsigned val) {
+    asm volatile ( "movgs   %0,ibar0\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_ibar1(void) {
+    unsigned retval;
+    asm volatile ( "movsg   ibar1,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_ibar1(unsigned val){
+    asm volatile ( "movgs   %0,ibar1\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_ibar2(void) {
+    unsigned retval;
+    asm volatile ( "movsg   ibar2,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_ibar2(unsigned val) {
+    asm volatile ( "movgs   %0,ibar2\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_ibar3(void) {
+    unsigned retval;
+    asm volatile ( "movsg   ibar3,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_ibar3(unsigned val){
+    asm volatile ( "movgs   %0,ibar3\n" : /* no outputs */  : "r" (val) );}
+
+// Two Data Break Address Registers
+static inline unsigned get_dbar0(void) {
+    unsigned retval;
+    asm volatile ( "movsg   dbar0,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbar0(unsigned val){
+    asm volatile ( "movgs   %0,dbar0\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbar1(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbar1,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbar1(unsigned val){
+    asm volatile ( "movgs   %0,dbar1\n" : /* no outputs */  : "r" (val) );}
+
+// Two times two Data Break Data Registers
+static inline unsigned get_dbdr00(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbdr00,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbdr00(unsigned val){
+    asm volatile ( "movgs   %0,dbdr00\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbdr01(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbdr01,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbdr01(unsigned val){
+    asm volatile ( "movgs   %0,dbdr01\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbdr10(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbdr10,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbdr10(unsigned val){
+    asm volatile ( "movgs   %0,dbdr10\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbdr11(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbdr11,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbdr11(unsigned val){
+    asm volatile ( "movgs   %0,dbdr11\n" : /* no outputs */  : "r" (val) );}
+
+// Two times two Data Break Mask Registers
+static inline unsigned get_dbmr00(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbmr00,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbmr00(unsigned val){
+    asm volatile ( "movgs   %0,dbmr00\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbmr01(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbmr01,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbmr01(unsigned val){
+    asm volatile ( "movgs   %0,dbmr01\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbmr10(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbmr10,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbmr10(unsigned val){
+    asm volatile ( "movgs   %0,dbmr10\n" : /* no outputs */  : "r" (val) );}
+
+static inline unsigned get_dbmr11(void){
+    unsigned retval;
+    asm volatile ( "movsg   dbmr11,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_dbmr11(unsigned val){
+    asm volatile ( "movgs   %0,dbmr11\n" : /* no outputs */  : "r" (val) );}
+
+// and here's the prototype.  Which compiles, believe it or not.
+static inline unsigned get_XXXX(void){
+    unsigned retval;
+    asm volatile ( "movsg   XXXX,%0\n" : "=r" (retval) : /* no inputs */  );
+    return retval;}
+static inline void set_XXXX(unsigned val){
+    asm volatile ( "movgs   %0,XXXX\n" : /* no outputs */  : "r" (val) );}
+
+// ------------------------------------------------------------------------
+// This is called in the same manner as exception_handler() in hal_misc.c
+// Comments compare and contrast what we do here.
+
+static unsigned int saved_brr = 0;
+
+void
+break_handler(HAL_SavedRegisters *regs)
+{
+    unsigned int i, old_bpsr;
+
+    // See if it an actual "break" instruction.
+    i = get_brr();
+    saved_brr |= i; // do not lose previous state
+    // Acknowledge the trap, clear the "factor" (== cause)
+    set_brr( 0 );
+
+    // Now leave debug mode so that it's safe to run the stub code.
+
+    // Unfortunately, leaving debug mode isn't a self-contained
+    // operation.  The only means of doing it is with a "rett #1"
+    // instruction, which will also restore the previous values of
+    // the ET and S status flags.  We can massage the BPSR
+    // register so that the flags keep their current values, but
+    // we need to save the old one first.
+    i = old_bpsr = get_bpsr ();
+    i |= _BPSR_BS; // Stay in supervisor mode
+    i &= ~_BPSR_BET; // Keep traps disabled
+    set_bpsr (i);
+    HAL_FRV_EXIT_DEBUG_MODE();
+
+    // Only perturb this variable if stopping, not
+    // just for a break instruction.
+    _hal_registers = regs; 
+
+    // Continue with the standard mechanism:
+    __handle_exception();
+
+    // Go back into debug mode.
+    HAL_FRV_ENTER_DEBUG_MODE();
+    // Restore the original BPSR register.
+    set_bpsr (old_bpsr);
+    return;
+}
+
+// ------------------------------------------------------------------------
+
+// Now the routines to manipulate said hardware break and watchpoints.
+
+int cyg_hal_plf_hw_breakpoint(int setflag, void *vaddr, int len)
+{
+    unsigned int addr = (unsigned)vaddr;
+    unsigned int dcr;
+    unsigned int retcode = 0;
+
+    HAL_FRV_ENTER_DEBUG_MODE();
+    dcr = get_dcr();
+
+    // GDB manual suggests that idempotency is required, so first remove
+    // any identical BP in residence.  Implements remove arm anyway.
+    if ( 0 != (dcr & (_DCR_IBE0 | _DCR_IBCE0)) &&
+         get_ibar0() == addr                       )
+        dcr &=~(_DCR_IBE0 | _DCR_IBCE0);
+    else if ( 0 != (dcr & (_DCR_IBE1 | _DCR_IBCE1)) &&
+              get_ibar1() == addr                       )
+        dcr &=~(_DCR_IBE1 | _DCR_IBCE1);
+    else if ( 0 != (dcr & (_DCR_IBE2 | _DCR_IBCE2)) &&
+              get_ibar2() == addr                       )
+        dcr &=~(_DCR_IBE2 | _DCR_IBCE2);
+    else if ( 0 != (dcr & (_DCR_IBE3 | _DCR_IBCE3)) &&
+              get_ibar3() == addr                       )
+        dcr &=~(_DCR_IBE3 | _DCR_IBCE3);
+    else
+        retcode = -1;
+    
+    if (setflag) {
+        retcode = 0; // it is OK really
+        if ( 0 == (dcr & (_DCR_IBE0 | _DCR_IBCE0)) ) {
+	    set_ibar0(addr);
+            dcr |= _DCR_IBE0;
+        }
+	else if ( 0 == (dcr & (_DCR_IBE1 | _DCR_IBCE1)) ) {
+	    set_ibar1(addr);
+            dcr |= _DCR_IBE1;
+        }
+	else if ( 0 == (dcr & (_DCR_IBE2 | _DCR_IBCE2)) ) {
+	    set_ibar2(addr);
+            dcr |= _DCR_IBE2;
+        }
+	else if ( 0 == (dcr & (_DCR_IBE3 | _DCR_IBCE3)) ) {
+	    set_ibar3(addr);
+            dcr |= _DCR_IBE3;
+        }
+	else
+	    retcode = -1;
+    }
+
+    if ( 0 == retcode )
+        set_dcr(dcr);
+    HAL_FRV_EXIT_DEBUG_MODE();
+    return retcode;
+}
+
+int cyg_hal_plf_hw_watchpoint(int setflag, void *vaddr, int len, int type)
+{
+    unsigned int addr = (unsigned)vaddr;
+    unsigned int mode;
+    unsigned int dcr;
+    unsigned int retcode = 0;
+    unsigned long long mask;
+    unsigned int mask0, mask1;
+    int i;
+
+    // Check the length fits within one block.
+    if ( ((~7) & (addr + len - 1)) != ((~7) & addr) )
+        return -1;
+
+    // Assuming big-endian like the platform seems to be...
+
+    // Get masks for the 8-byte span.  00 means enabled, ff means ignore a
+    // byte, which is why this looks funny at first glance.
+    mask = 0x00ffffffffffffffULL >> ((len - 1) << 3);
+    for (i = 0; i < (addr & 7); i++) {
+        mask >>= 8;
+        mask |= 0xff00000000000000ULL;
+    }
+
+    mask0 = mask >> 32;
+    mask1 = mask & 0xffffffffULL;
+
+    addr &=~7; // round to 8-byte block
+
+    HAL_FRV_ENTER_DEBUG_MODE();
+    dcr = get_dcr();
+
+    // GDB manual suggests that idempotency is required, so first remove
+    // any identical WP in residence.  Implements remove arm anyway.
+    if (      0 != (dcr & (7 * _DCR_DBASE0)) &&
+              get_dbar0() == addr            &&
+              get_dbmr00() == mask0 && get_dbmr01() == mask1 )
+        dcr &=~(7 * _DCR_DBASE0);
+    else if ( 0 != (dcr & (7 * _DCR_DBASE1)) &&
+              get_dbar1() == addr&&
+              get_dbmr10() == mask0 && get_dbmr11() == mask1 )
+        dcr &=~(7 * _DCR_DBASE1);
+    else
+        retcode = -1;
+
+    if (setflag) {
+        retcode = 0; // it is OK really
+        if      (type == 2)       mode = 2; // break on write
+        else if (type == 3)       mode = 4; // break on read
+        else if (type == 4)       mode = 6; // break on any access
+        else {
+            mode = 0; // actually add no enable at all.
+            retcode = -1;
+        }
+        if ( 0 == (dcr & (7 * _DCR_DBASE0)) ) {
+            set_dbar0(addr);
+            // Data and Mask 0,1 to zero (mask no bits/bytes)
+            set_dbdr00(0); set_dbdr01(0); set_dbmr00(mask0); set_dbmr01(mask1);
+            mode *= _DCR_DBASE0;
+            dcr |= mode;
+        }
+        else if ( 0 == (dcr & (7 * _DCR_DBASE1)) ) {
+            set_dbar1(addr);
+            set_dbdr10(0); set_dbdr11(0); set_dbmr10(mask0); set_dbmr11(mask1);
+            mode *= _DCR_DBASE1;
+            dcr |= mode;
+        }
+        else
+            retcode = -1;
+    }
+
+    if ( 0 == retcode )
+        set_dcr(dcr);
+    HAL_FRV_EXIT_DEBUG_MODE();
+    return retcode;
+}
+
+// Return indication of whether or not we stopped because of a
+// watchpoint or hardware breakpoint. If stopped by a watchpoint,
+// also set '*data_addr_p' to the data address which triggered the
+// watchpoint.
+int cyg_hal_plf_is_stopped_by_hardware(void **data_addr_p)
+{
+    unsigned int brr;
+    int retcode = HAL_STUB_HW_STOP_NONE;
+    unsigned long long mask;
+
+    // There was a debug event. Check the BRR for details
+    brr = saved_brr;
+    saved_brr = 0;
+
+    if ( brr & (_BRR_IB0 | _BRR_IB1 | _BRR_IB2 | _BRR_IB3) ) {
+        // then it was an instruction break
+        retcode = HAL_STUB_HW_STOP_BREAK;
+    }
+    else if ( brr & (_BRR_DB0 | _BRR_DB1) ) {
+        unsigned int addr, kind;
+        kind = get_dcr();
+        if ( brr & (_BRR_DB0) ) {
+            addr = get_dbar0();
+            kind &= 7 * _DCR_DBASE0;
+            kind /= _DCR_DBASE0;
+            mask = (((unsigned long long)get_dbmr00())<<32) | (unsigned long long)get_dbmr01();
+        } else {
+            addr = get_dbar1();
+            kind &= 7 * _DCR_DBASE1;
+            kind /= _DCR_DBASE1;
+            mask = (((unsigned long long)get_dbmr10())<<32) | (unsigned long long)get_dbmr11();
+        }
+
+        if ( data_addr_p ) {
+            // Scan for a zero byte in the mask - this gives the true address.
+            //              0123456789abcdef
+            while ( 0 != (0xff00000000000000LLU & mask) ) {
+                mask <<= 8;
+                addr++;
+            }
+            *data_addr_p = (void *)addr;
+        }
+
+        // Inverse of the mapping above in the "set" code.
+        if      (kind == 2)       retcode = HAL_STUB_HW_STOP_WATCH;
+        else if (kind == 6)       retcode = HAL_STUB_HW_STOP_AWATCH;
+        else if (kind == 4)       retcode = HAL_STUB_HW_STOP_RWATCH;
+    }
+    return retcode;
+}
+
+// ------------------------------------------------------------------------
+
Index: packages/hal/frv/arch/current/src/hal_diag.c
===================================================================
RCS file: packages/hal/frv/arch/current/src/hal_diag.c
diff -N packages/hal/frv/arch/current/src/hal_diag.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/src/hal_diag.c	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,436 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, gthomas
+// Contributors:nickg, gthomas
+// Date:        1998-03-02
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include CYGBLD_HAL_PLATFORM_H
+#include CYGBLD_HAL_PLATFORM_IO_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // basic machine info
+#include <cyg/hal/hal_intr.h>           // interrupt macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_misc.h>           // Helper functions
+
+#include <cyg/hal/fr-v.h>             // Platform specific (registers, etc)
+
+extern long _system_clock;
+#define _BRG(r) (((_system_clock/((r)*8))+1)/2)
+
+/*---------------------------------------------------------------------------*/
+/* From serial_16550.h */
+// Define the serial registers.
+#define CYG_DEV_RBR 0x00   // receiver buffer register, read, dlab = 0
+#define CYG_DEV_THR 0x00   // transmitter holding register, write, dlab = 0
+#define CYG_DEV_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_IER 0x08   // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_DLM 0x08   // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_IIR 0x10   // interrupt identification register, read, dlab = 0
+#define CYG_DEV_FCR 0x10   // fifo control register, write, dlab = 0
+#define CYG_DEV_LCR 0x18   // line control register, read/write
+#define CYG_DEV_MCR 0x20   // modem control register, read/write
+#define CYG_DEV_LSR 0x28   // line status register, read
+#define CYG_DEV_MSR 0x30   // modem status register, read
+
+#define CYG_DEV_CLK 0x90   // Prescaler clock control register - Fujitsu special
+#define CYG_DEV_PSC 0x98   // Prescaler value
+
+// Interrupt Enable Register
+#define SIO_IER_RCV 0x01
+#define SIO_IER_XMT 0x02
+#define SIO_IER_LS  0x04
+#define SIO_IER_MS  0x08
+
+// The line status register bits.
+#define SIO_LSR_DR      0x01            // data ready
+#define SIO_LSR_OE      0x02            // overrun error
+#define SIO_LSR_PE      0x04            // parity error
+#define SIO_LSR_FE      0x08            // framing error
+#define SIO_LSR_BI      0x10            // break interrupt
+#define SIO_LSR_THRE    0x20            // transmitter holding register empty
+#define SIO_LSR_TEMT    0x40            // transmitter register empty
+#define SIO_LSR_ERR     0x80            // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS  0x01              // delta clear to send
+#define SIO_MSR_DDSR  0x02              // delta data set ready
+#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
+#define SIO_MSR_DDCD  0x08              // delta data carrier detect
+#define SIO_MSR_CTS   0x10              // clear to send
+#define SIO_MSR_DSR   0x20              // data set ready
+#define SIO_MSR_RI    0x40              // ring indicator
+#define SIO_MSR_DCD   0x80              // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0   0x01             // word length select bit 0
+#define SIO_LCR_WLS1   0x02             // word length select bit 1
+#define SIO_LCR_STB    0x04             // number of stop bits
+#define SIO_LCR_PEN    0x08             // parity enable
+#define SIO_LCR_EPS    0x10             // even parity select
+#define SIO_LCR_SP     0x20             // stick parity
+#define SIO_LCR_SB     0x40             // set break
+#define SIO_LCR_DLAB   0x80             // divisor latch access bit
+
+// Modem Control Register
+#define SIO_MCR_DTR 0x01
+#define SIO_MCR_RTS 0x02
+#define SIO_MCR_INT 0x08   // Enable interrupts
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint8* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+    int baud_rate;
+} channel_data_t;
+
+//-----------------------------------------------------------------------------
+
+static void
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8* base = chan->base;
+    cyg_uint8 lcr;
+    int _brg = _BRG(chan->baud_rate);
+    
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+    // Set the baud rate
+    HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
+    lcr |= SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
+    HAL_WRITE_UINT8(base+CYG_DEV_DLL, _brg & 0xFF);
+    HAL_WRITE_UINT8(base+CYG_DEV_DLM, _brg >> 8);
+    lcr &= ~SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
+
+    // Enable & clear FIFO
+    HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07);  
+
+    // Configure interrupt
+    HAL_INTERRUPT_CONFIGURE(chan->isr_vector, 1, 1);  // Interrupt when IRQ is high
+}
+
+void
+cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+
+    HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
+    if ((lsr & SIO_LSR_DR) == 0)
+        return false;
+
+    HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
+
+    return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+static channel_data_t pid_ser_channels[] = {
+    { (cyg_uint8*)_FRVGEN_UART0, 1000, CYGNUM_HAL_INTERRUPT_SERIALA, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+    { (cyg_uint8*)_FRVGEN_UART1, 1000, CYGNUM_HAL_INTERRUPT_SERIALB, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+};
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    int ret = 0;
+
+    CYGARC_HAL_SAVE_GP();
+
+    switch (__func) {
+    case __COMMCTL_GETBAUD:
+	ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+    {
+        va_list ap;
+	int newbaud;
+
+        va_start(ap, __func);
+	newbaud = va_arg(ap, cyg_int32);
+        va_end(ap);
+
+ 	switch(newbaud) {
+	case 9600:
+	case 19200:
+	case 38400:
+	case 57600:
+	case 115200:
+	case 230400:
+	case 460800:
+		chan->baud_rate = newbaud;
+		cyg_hal_plf_serial_init_channel(chan);
+		break;
+
+	default:
+		ret = -1;
+	}
+        break;
+    }
+    case __COMMCTL_IRQ_ENABLE:
+        irq_state = 1;
+
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
+
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
+
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    default:
+        break;
+    }
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    int res = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    char c;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+    HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
+    if ( (lsr & SIO_LSR_DR) != 0 ) {
+
+        HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
+        if( cyg_hal_is_break( &c , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Special case - turn on clocks for UARTS
+    HAL_WRITE_UINT32(_FRVGEN_UART0+CYG_DEV_CLK, 0x80<<24);
+
+    // Disable interrupts.
+    HAL_INTERRUPT_MASK(pid_ser_channels[0].isr_vector);
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+    HAL_INTERRUPT_MASK(pid_ser_channels[1].isr_vector);
+#endif
+
+    // Init channels
+    cyg_hal_plf_serial_init_channel(&pid_ser_channels[0]);
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+    cyg_hal_plf_serial_init_channel(&pid_ser_channels[1]);
+#endif
+
+    // Setup procs in the vector table
+
+    // Set channel 0
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[0]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+    // Set channel 1
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[1]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
Index: packages/hal/frv/arch/current/src/hal_mk_defs.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/arch/current/src/hal_mk_defs.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 hal_mk_defs.c
--- packages/hal/frv/arch/current/src/hal_mk_defs.c	23 May 2002 23:02:53 -0000	1.2
+++ packages/hal/frv/arch/current/src/hal_mk_defs.c	5 Sep 2004 20:50:13 -0000
@@ -6,11 +6,11 @@
 //
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -175,10 +175,11 @@ main(void)
     DEFINE(_NFPR, _NFPR);
 
     DEFINE(_PSR_ET, _PSR_ET);
     DEFINE(_PSR_S, _PSR_S);
     DEFINE(_PSR_PS, _PSR_PS);
+    DEFINE(_PSR_CM, _PSR_CM);
     DEFINE(_PSR_PIVL_MASK, _PSR_PIVL_MASK);
     DEFINE(_PSR_PIVL_SHIFT, _PSR_PIVL_SHIFT);
 
     DEFINE(_HSR0_ICE, _HSR0_ICE);
     DEFINE(_HSR0_DCE, _HSR0_DCE);
Index: packages/hal/frv/arch/current/src/redboot_linux_exec.c
===================================================================
RCS file: packages/hal/frv/arch/current/src/redboot_linux_exec.c
diff -N packages/hal/frv/arch/current/src/redboot_linux_exec.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ packages/hal/frv/arch/current/src/redboot_linux_exec.c	5 Sep 2004 20:50:13 -0000
@@ -0,0 +1,130 @@
+//==========================================================================
+//
+//      redboot_linux_exec.c
+//
+//      RedBoot exec command for Linux booting
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    t@keshi.org
+// Contributors: t@keshi.org, jskov, dwmw2
+// Date:         2003-11-13
+// Purpose:      RedBoot exec command for Linux booting, from MIPS arch
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <redboot.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h>
+
+#ifdef CYGPKG_IO_ETH_DRIVERS
+#include <cyg/io/eth/eth_drv.h>            // Logical driver interfaces
+#endif
+
+#define xstr(s) str(s)
+#define str(s...) #s
+
+static void do_exec(int argc, char *argv[]);
+RedBoot_cmd("exec", 
+            "Execute an image", 
+            "[-c \"kernel command line\"] [-w <timeout>]\n"
+	    "        [<entry point>]",
+            do_exec
+    );
+
+static void 
+do_exec(int argc, char *argv[])
+{
+    cyg_uint32 entry = (cyg_uint32)entry_address?:CYGDAT_REDBOOT_FRV_LINUX_BOOT_ENTRY;
+    char *cmd_line = xstr(CYGDAT_REDBOOT_FRV_LINUX_BOOT_COMMAND_LINE);
+    bool cmd_line_set, wait_time_set;
+    int wait_time, res;
+    char line[8];
+    
+    struct option_info opts[3];
+    void (*linux_boot)(unsigned long, char *);
+    int oldints;
+    hal_virtual_comm_table_t *__chan;
+    int baud;
+
+    init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM, 
+              (void **)&wait_time, (bool *)&wait_time_set, "wait timeout");
+    init_opts(&opts[1], 'c', true, OPTION_ARG_TYPE_STR, 
+              (void **)&cmd_line, &cmd_line_set, "kernel command line");
+    
+    if (!scan_opts(argc, argv, 1, opts, 2, (void *)&entry, 
+                   OPTION_ARG_TYPE_NUM, "entry address"))
+        return;
+
+    linux_boot = (void *)entry;
+
+    __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+    baud = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_GETBAUD);
+
+    diag_printf("Now booting linux kernel:\n");
+    diag_printf(" Entry 0x%08x\n", entry);
+    diag_printf(" Cmdline : %s\n", cmd_line);
+
+    if (wait_time_set) {
+        diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
+                    (void *)entry, wait_time);
+        res = _rb_gets(line, sizeof(line), wait_time*1000);
+        if (res == _GETS_CTRLC) {
+            return;
+        }
+    }
+    
+    HAL_DISABLE_INTERRUPTS(oldints);
+
+#ifdef CYGPKG_IO_ETH_DRIVERS
+    eth_drv_stop();
+#endif
+   
+    HAL_DCACHE_SYNC();
+    HAL_ICACHE_DISABLE();
+    HAL_DCACHE_DISABLE();
+    HAL_DCACHE_SYNC();
+    HAL_ICACHE_INVALIDATE_ALL();
+    HAL_DCACHE_INVALIDATE_ALL();
+
+    linux_boot(0xdead1eaf, cmd_line);
+}
Index: packages/hal/frv/arch/current/src/vectors.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/arch/current/src/vectors.S,v
retrieving revision 1.2
diff -u -p -5 -r1.2 vectors.S
--- packages/hal/frv/arch/current/src/vectors.S	23 May 2002 23:02:53 -0000	1.2
+++ packages/hal/frv/arch/current/src/vectors.S	5 Sep 2004 20:50:14 -0000
@@ -6,11 +6,11 @@
 // #
 // #========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -138,10 +138,16 @@
         sti     gr28,@(\base,_TS_GPR28)
         sti     gr29,@(\base,_TS_GPR29)
         sti     gr30,@(\base,_TS_GPR30)
         sti     gr31,@(\base,_TS_GPR31)        
 #if _NGPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400
+	movsg	HSR0,gr5
+	srli	gr5,#10,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif
         sti     gr32,@(\base,_TS_GPR32)
         sti     gr33,@(\base,_TS_GPR33)
         sti     gr34,@(\base,_TS_GPR34)
         sti     gr35,@(\base,_TS_GPR35)
         sti     gr36,@(\base,_TS_GPR36)
@@ -170,22 +176,21 @@
         sti     gr59,@(\base,_TS_GPR59)
         sti     gr60,@(\base,_TS_GPR60)
         sti     gr61,@(\base,_TS_GPR61)
         sti     gr62,@(\base,_TS_GPR62)
         sti     gr63,@(\base,_TS_GPR63)
+1:	
 #endif
 	movsg	psr,gr5
 	sti	gr5,@(\base,_TS_PSR)
 	movsg	lcr,gr5
 	sti	gr5,@(\base,_TS_LCR)
 	movsg	cccr,gr5
 	sti	gr5,@(\base,_TS_CCCR)
 	movsg	bpcsr,gr5
-#if defined( CYGSEM_HAL_FRV_HW_DEBUG ) || defined(CYGPKG_HAL_FRV_FRV400)
         cmpi    gr4,#CYGNUM_HAL_VECTOR_BREAKPOINT,icc0
         beq     icc0,0,10f
-#endif        
 5:      movsg	pcsr,gr5
         cmpi    gr4,#CYGNUM_HAL_VECTOR_SYSCALL,icc0
         blt     icc0,0,10f
 6:      subi    gr5,#4,gr5              // traps show PC+4
 10:     sti	gr5,@(\base,_TS_PC)
@@ -203,41 +208,17 @@
         movgs   gr5,psr
 	ldi	@(\base,_TS_LCR),gr5
         movgs   gr5,lcr
 	ldi	@(\base,_TS_CCCR),gr5
         movgs   gr5,cccr
-        ldi     @(\base,_TS_GPR2),gr2
-        ldi     @(\base,_TS_GPR3),gr3
-        ldi     @(\base,_TS_GPR4),gr4
-        ldi     @(\base,_TS_GPR5),gr5
-        ldi     @(\base,_TS_GPR6),gr6
-        ldi     @(\base,_TS_GPR7),gr7
-        ldi     @(\base,_TS_GPR8),gr8
-        ldi     @(\base,_TS_GPR9),gr9
-        ldi     @(\base,_TS_GPR10),gr10
-        ldi     @(\base,_TS_GPR11),gr11
-        ldi     @(\base,_TS_GPR12),gr12
-        ldi     @(\base,_TS_GPR13),gr13
-        ldi     @(\base,_TS_GPR14),gr14
-        ldi     @(\base,_TS_GPR15),gr15
-        ldi     @(\base,_TS_GPR16),gr16
-        ldi     @(\base,_TS_GPR17),gr17
-        ldi     @(\base,_TS_GPR18),gr18
-        ldi     @(\base,_TS_GPR19),gr19
-        ldi     @(\base,_TS_GPR20),gr20
-        ldi     @(\base,_TS_GPR21),gr21
-        ldi     @(\base,_TS_GPR22),gr22
-        ldi     @(\base,_TS_GPR23),gr23
-        ldi     @(\base,_TS_GPR24),gr24
-        ldi     @(\base,_TS_GPR25),gr25
-        ldi     @(\base,_TS_GPR26),gr26
-        ldi     @(\base,_TS_GPR27),gr27
-        ldi     @(\base,_TS_GPR28),gr28
-        ldi     @(\base,_TS_GPR29),gr29
-        ldi     @(\base,_TS_GPR30),gr30
-        ldi     @(\base,_TS_GPR31),gr31
 #if _NGPR != 32
+#ifdef CYGINT_HAL_FRV_ARCH_FR400
+	movsg	HSR0,gr5
+	srli	gr5,#10,gr5
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,1f
+#endif
         ldi     @(\base,_TS_GPR32),gr32
         ldi     @(\base,_TS_GPR33),gr33
         ldi     @(\base,_TS_GPR34),gr34
         ldi     @(\base,_TS_GPR35),gr35
         ldi     @(\base,_TS_GPR36),gr36
@@ -266,17 +247,48 @@
         ldi     @(\base,_TS_GPR59),gr59
         ldi     @(\base,_TS_GPR60),gr60
         ldi     @(\base,_TS_GPR61),gr61
         ldi     @(\base,_TS_GPR62),gr62
         ldi     @(\base,_TS_GPR63),gr63
+1:	
 #endif        
+        ldi     @(\base,_TS_GPR2),gr2
+        ldi     @(\base,_TS_GPR3),gr3
+        ldi     @(\base,_TS_GPR4),gr4
+        ldi     @(\base,_TS_GPR5),gr5
+        ldi     @(\base,_TS_GPR6),gr6
+        ldi     @(\base,_TS_GPR7),gr7
+        ldi     @(\base,_TS_GPR8),gr8
+        ldi     @(\base,_TS_GPR9),gr9
+        ldi     @(\base,_TS_GPR10),gr10
+        ldi     @(\base,_TS_GPR11),gr11
+        ldi     @(\base,_TS_GPR12),gr12
+        ldi     @(\base,_TS_GPR13),gr13
+        ldi     @(\base,_TS_GPR14),gr14
+        ldi     @(\base,_TS_GPR15),gr15
+        ldi     @(\base,_TS_GPR16),gr16
+        ldi     @(\base,_TS_GPR17),gr17
+        ldi     @(\base,_TS_GPR18),gr18
+        ldi     @(\base,_TS_GPR19),gr19
+        ldi     @(\base,_TS_GPR20),gr20
+        ldi     @(\base,_TS_GPR21),gr21
+        ldi     @(\base,_TS_GPR22),gr22
+        ldi     @(\base,_TS_GPR23),gr23
+        ldi     @(\base,_TS_GPR24),gr24
+        ldi     @(\base,_TS_GPR25),gr25
+        ldi     @(\base,_TS_GPR26),gr26
+        ldi     @(\base,_TS_GPR27),gr27
+        ldi     @(\base,_TS_GPR28),gr28
+        ldi     @(\base,_TS_GPR29),gr29
+        ldi     @(\base,_TS_GPR30),gr30
+        ldi     @(\base,_TS_GPR31),gr31
         ldi     @(\base,_TS_SP),gr1   // This has to be last - Stack pointer
         rett    #\retv
         .endm
-        
-#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
+	
         .macro  exception_VSR
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
         subi    sp,24,sp
         sti     gr4,@(sp,0)
 #else
@@ -285,34 +297,38 @@
 #endif                
         addi    gr0,#((.-8)-_vectors)/16,gr4
         bra     _exception
         .endm
 
-#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
-        .macro  break_VSR
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        .macro  break_VSR
         subi    sp,24,sp
         sti     gr4,@(sp,0)
-#else
-        subi    sp,_TS_size,sp
-        sti     gr4,@(sp,_TS_GPR4)
-#endif                
         addi    gr0,#((.-8)-_vectors)/16,gr4
         bra     _break
         .endm
-#endif // CYGPKG_HAL_FRV_FRV400 && STUBS
+#else
+#define break_VSR exception_VSR
+#endif // STUBS
 
         .macro  interrupt_VSR
         subi    sp,_TS_size,sp
         sti     gr4,@(sp,_TS_GPR4)
         addi    gr0,#((.-8)-_vectors)/16,gr4
         bra     _interrupt
         .endm
         
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
         .section ".rom_vectors","ax"
 _vectors:               
         call    reset_vector
+#else /* RAM */
+	.section ".rodata","a"
+	.balign	4096
+_vectors:               
+	nop
+#endif	
         nop	// I hate fencepost stuff like this....                 
         nop	// (NEXT_INDEX_AFTER_THIS - 1) - (PREVIOUS_INDEX_FILLED)
         nop	// (LAST_INDEX_TO_FILL)        - (PREVIOUS_INDEX_FILLED)
         .rept   (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1-1)-0
         exception_VSR
@@ -321,25 +337,20 @@ _vectors:               
         interrupt_VSR
         .endr
         .rept   (254) - CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15
         exception_VSR
         .endr
-#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 	break_VSR // in index 255
-#else
-	exception_VSR // another one
-#endif // CYGPKG_HAL_FRV_FRV400 && STUBS
 	
 //
 // Handle a break
 //
 // just like _exception, but it calls break_handler instead.
 //
-#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
-	_break:
-        // Save current register state
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+_break:
+        // Save current register state
         sti     gr5,@(sp,4)
 
 	// First, check BRR to see whether we're processing a break
 	// instruction.  The stub uses this instruction to enter debug mode.
 	movsg	brr,gr5
@@ -410,25 +421,22 @@ _vectors:               
 10:     lda     __GDB_stack,sp          // already on GDB stack?
 11:     
         subi    sp,_TS_size,sp          // Space for scratch saves
         save_GDB_exception_regs sp,gr6
         save_state sp
-#else
-        save_exception_regs sp
-        save_state sp
-#endif
-        LED     0x0FFF
+
+        LED     0x0FF1
         add     sp,gr0,gr8
         call    break_handler
         restore_state sp,bpcsr,1
-#endif // CYGPKG_HAL_FRV_FRV400 && STUBS
+#endif // STUBS
 
 //
 // Handle an exception
 //
 _exception:
-        // Save current register state
+	// Save current register state
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
         sti     gr5,@(sp,4)
         sti     gr6,@(sp,8)
         sti     gr16,@(sp,12)
 	movsg	lr,gr5
@@ -455,12 +463,12 @@ _exception:
         save_state sp
 #else
         save_exception_regs sp
         save_state sp
 #endif
-        LED     0x0FFF
-        add     sp,gr0,gr8
+        LED     0x0FF2
+	mov	sp,gr8
         call    exception_handler
         bra     _exception_return
 
 //
 // Handle an interrupt
@@ -519,27 +527,82 @@ _interrupt:                             
 //                        
 _exception_return:               
         LED     0x0000
         restore_state sp,pcsr,0
 
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
         .global reset_vector
 reset_vector:
-
+#if 1
+	// I'm not sure why this is necessary, but power on reset
+	// of CB70/VDK appears very unreliable without it.
+	setlos	#1000,gr4
+99:	subicc	gr4,#1,gr4,icc0
+	bne	icc0,0,99b
+#endif
         // Make sure the CPU is in the proper mode (system), interrupts disabled
         movsg   psr,gr4
         li      ~(_PSR_ET|_PSR_PS|_PSR_PIVL_MASK),gr5
         and     gr4,gr5,gr4
-        li      (_PSR_S|_PSR_ET|(0x0F<<_PSR_PIVL_SHIFT)),gr5
+        li      (_PSR_S|_PSR_ET|_PSR_CM|(0x0F<<_PSR_PIVL_SHIFT)),gr5
         or      gr4,gr5,gr4
-        movgs   gr4,psr
+	movgs   gr4,psr
         
-        // Make sure caches, MMUs are disabled
         movsg   hsr0,gr4
-        li      ~(_HSR0_ICE|_HSR0_DCE|_HSR0_IMMU|_HSR0_DMMU),gr5
-        and     gr4,gr5,gr4
-        movgs   gr4,hsr0
-        
+        // Make sure caches, MMUs, sleep states are disabled
+        li      ~(_HSR0_ICE|_HSR0_DCE|_HSR0_IMMU|_HSR0_DMMU|7),gr5
+        and     gr4,gr5,gr5
+        movgs   gr5,hsr0
+
+#ifdef __CB70_DEBUG
+	membar
+	sethi	#0xffc0,gr11
+	setlo	#0x0000,gr11
+
+	setlo	#0x5555,gr6
+	sthi	gr6,@(gr11,0x100)  // leds
+	membar
+#endif
+	
+#ifdef CYGSEM_REDBOOT_FRV_LINUX_BOOT
+	andicc	gr4,#7,gr0,icc0	// Were we in a sleep state?
+	beq	icc0,0,3f	// No... normal startup
+
+#ifdef __CB70_DEBUG
+	setlo	#1,gr6
+	sthi	gr6,@(gr11,0x100)  // leds
+	membar
+#endif
+	
+	not	gr14,gr5	// If gr14 = ~gr13 then gr14 is return address
+	cmp	gr5,gr13,icc0	// ... else normal startup
+	bne	icc0,0,3f
+
+#ifdef __CB70_DEBUG
+	setlo	#2,gr6
+	sthi	gr6,@(gr11,0x100)  // leds
+	membar
+#endif
+	
+	// Assume FR400 since FR5xx doesn't run Linux (yet)
+	li	_FRV400_SDRAM_STS, gr4
+	sti	gr0,@(gr4,8)	// DRCN. Turn off self-refresh.
+2:	
+	ldi	@(gr4,0),gr5	// Wait for it to come back...
+	andicc	gr5,#1,gr0,icc0
+	bne	icc0,0,2b
+
+#ifdef __CB70_DEBUG
+	setlo	#4,gr6
+	sthi	gr6,@(gr11,0x100)  // leds
+	membar
+#endif
+
+	jmpil	@(gr14,#0)
+	
+3:
+#endif		
         // Initialize hardware platform - this macro only contains
         // code which must be run before any "normal" accesses are
         // allowed, such as enabling DRAM controllers, etc.
         platform_init
         
@@ -561,38 +624,41 @@ reset_vector:
 	setlos	#4,gr7
 15:	ldu	@(gr4,gr7),gr5
 	stu	gr5,@(gr6,gr7)
 	cmp	gr6,gr8,icc0
 	bne	icc0,0,15b        
+        LED     0x5001
         jmpl    @(gr10,gr0)
 20:     nop        
-#endif
+#endif // ROMRAM
 
         // Fall through to normal program startup
-        
-#endif  //  CYG_HAL_STARTUP_ROM
+#endif // ROM || ROMRAM        
+#endif  // !CYGSEM_HAL_USE_ROM_MONITOR
 
         .text
         
         .global _start
 _start:         
-        // Set the global offset register (gr16)
+        LED 0x5002
+        // Set the global offset register (gr16) call
         call    .Lcall
     .Lcall:
         movsg   lr,gr4
         sethi   #gprelhi(.Lcall),gr5
         setlo   #gprello(.Lcall),gr5
         sub     gr4,gr5,gr16
 
         LED     0x0000
-        
-#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR        
         // Set up trap base register                
         lda     _vectors,gr4
         movgs   gr4,tbr
 
         LED     0x0001
+#endif
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
         
         // Relocate [copy] data from ROM to RAM
         lda     __rom_data_start,gr4
         lda     __ram_data_start,gr5
         lda     __ram_data_end,gr6
Index: packages/hal/frv/frv400/current/src/frv400_misc.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/frv/frv400/current/src/frv400_misc.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 frv400_misc.c
--- packages/hal/frv/frv400/current/src/frv400_misc.c	23 May 2002 23:02:54 -0000	1.2
+++ packages/hal/frv/frv400/current/src/frv400_misc.c	5 Sep 2004 20:50:14 -0000
@@ -647,436 +647,7 @@ _frv400_pci_cfg_write_uint32(int bus, in
         HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
     }
     HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
 }
 
-// ------------------------------------------------------------------------
-//
-// Hardware breakpoint/watchpoint support
-// ======================================
-//
-// Now follows a load of extreme unpleasantness to deal with the totally
-// broken debug model of this device.
-//
-// To modify the special hardware debug registers, it is necessary to put
-// the CPU into "debug mode".  This can only be done by executing a break
-// instruction, or taking a special hardware break event as described by
-// the special hardware debug registers.
-//
-// But once in debug mode, no break is taken, and break instructions are
-// ignored, because we are in debug mode.
-//
-// So we must exit debug mode for normal running, which you can only do via
-// a rett #1 instruction.  Because rett is for returning from traps, it
-// halts the CPU if you do it with traps enabled.  So you have to mess
-// about disabling traps before the rett.  Also, because rett #1 is for
-// returning from a *debug* trap, you can only issue it from debug mode -
-// or it halts the CPU.
-//
-// To be able to set and unset hardware debug breakpoints and watchpoints,
-// we must enter debug mode (via a "break" instruction).  Fortunately, it
-// is possible to return from a "break" remaining in debug mode, using a
-// rett #0, so we can arrange that a break instruction just means "go to
-// debug mode".
-//
-// So we can manipulate the special hardware debug registers by executing a
-// "break", doing the work, then doing the magic sequence to rett #1.
-// These are encapsulated in HAL_FRV_ENTER_DEBUG_MODE() and
-// HAL_FRV_EXIT_DEBUG_MODE() from plf_stub.h
-//
-// So, we get into break_hander() for two reasons:
-//   1) a break instruction.  Detect this and do nothing; return skipping
-//      over the break instruction.  CPU remains in debug mode.
-//   2) a hardware debug trap.  Continue just as for a normal exception;
-//      GDB and the stubs will handle it.  But first, exit debug mode, or
-//      stuff happening in the stubs will go wrong.
-//
-// In order to be certain that we are in debug mode, for performing (2)
-// safely, vectors.S installs a special debug trap handler on vector #255.
-// That's the reason for break_handler() existing as a separate routine.
-// 
-// Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for the
-// FRV_FRV400 target; while we do use Hardware Debug, we don't use *that*
-// sort of hardware debug, specifically we do not use hardware single-step,
-// because it breaks as soon as we exit debug mode, ie. whilst we are still
-// within the stub.  So in fact defining CYGSEM_HAL_FRV_HW_DEBUG is bad; I
-// guess it is mis-named.
-//
-
-// ------------------------------------------------------------------------
-// First a load of ugly boilerplate for register access.
-
-#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-
-#include <cyg/hal/hal_stub.h>           // HAL_STUB_HW_STOP_NONE et al
-#include <cyg/hal/frv_stub.h>           // register names PC, PSR et al
-#include <cyg/hal/plf_stub.h>           // HAL_FRV_EXIT_DEBUG_MODE()
-
-// First a load of glue
-static inline unsigned get_bpsr(void) {
-    unsigned retval;
-    asm volatile ( "movsg   bpsr,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_bpsr(unsigned val) {
-    asm volatile ( "movgs   %0,bpsr\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dcr(void) {
-    unsigned retval;
-    asm volatile ( "movsg   dcr,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dcr(unsigned val) {
-    asm volatile ( "movgs   %0,dcr\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_brr(void) {
-    unsigned retval;
-    asm volatile ( "movsg   brr,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_brr(unsigned val) {
-    asm volatile ( "movgs   %0,brr\n" : /* no outputs */  : "r" (val) );}
-
-// Four Instruction Break Address Registers
-static inline unsigned get_ibar0(void) {
-    unsigned retval;
-    asm volatile ( "movsg   ibar0,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_ibar0(unsigned val) {
-    asm volatile ( "movgs   %0,ibar0\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_ibar1(void) {
-    unsigned retval;
-    asm volatile ( "movsg   ibar1,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_ibar1(unsigned val){
-    asm volatile ( "movgs   %0,ibar1\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_ibar2(void) {
-    unsigned retval;
-    asm volatile ( "movsg   ibar2,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_ibar2(unsigned val) {
-    asm volatile ( "movgs   %0,ibar2\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_ibar3(void) {
-    unsigned retval;
-    asm volatile ( "movsg   ibar3,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_ibar3(unsigned val){
-    asm volatile ( "movgs   %0,ibar3\n" : /* no outputs */  : "r" (val) );}
-
-// Two Data Break Address Registers
-static inline unsigned get_dbar0(void) {
-    unsigned retval;
-    asm volatile ( "movsg   dbar0,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbar0(unsigned val){
-    asm volatile ( "movgs   %0,dbar0\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbar1(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbar1,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbar1(unsigned val){
-    asm volatile ( "movgs   %0,dbar1\n" : /* no outputs */  : "r" (val) );}
-
-// Two times two Data Break Data Registers
-static inline unsigned get_dbdr00(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbdr00,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbdr00(unsigned val){
-    asm volatile ( "movgs   %0,dbdr00\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbdr01(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbdr01,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbdr01(unsigned val){
-    asm volatile ( "movgs   %0,dbdr01\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbdr10(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbdr10,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbdr10(unsigned val){
-    asm volatile ( "movgs   %0,dbdr10\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbdr11(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbdr11,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbdr11(unsigned val){
-    asm volatile ( "movgs   %0,dbdr11\n" : /* no outputs */  : "r" (val) );}
-
-// Two times two Data Break Mask Registers
-static inline unsigned get_dbmr00(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbmr00,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbmr00(unsigned val){
-    asm volatile ( "movgs   %0,dbmr00\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbmr01(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbmr01,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbmr01(unsigned val){
-    asm volatile ( "movgs   %0,dbmr01\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbmr10(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbmr10,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbmr10(unsigned val){
-    asm volatile ( "movgs   %0,dbmr10\n" : /* no outputs */  : "r" (val) );}
-
-static inline unsigned get_dbmr11(void){
-    unsigned retval;
-    asm volatile ( "movsg   dbmr11,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_dbmr11(unsigned val){
-    asm volatile ( "movgs   %0,dbmr11\n" : /* no outputs */  : "r" (val) );}
-
-// and here's the prototype.  Which compiles, believe it or not.
-static inline unsigned get_XXXX(void){
-    unsigned retval;
-    asm volatile ( "movsg   XXXX,%0\n" : "=r" (retval) : /* no inputs */  );
-    return retval;}
-static inline void set_XXXX(unsigned val){
-    asm volatile ( "movgs   %0,XXXX\n" : /* no outputs */  : "r" (val) );}
-
-// ------------------------------------------------------------------------
-// This is called in the same manner as exception_handler() in hal_misc.c
-// Comments compare and contrast what we do here.
-
-static unsigned int saved_brr = 0;
-
-void
-break_handler(HAL_SavedRegisters *regs)
-{
-    unsigned int i, old_bpsr;
-
-    // See if it an actual "break" instruction.
-    i = get_brr();
-    saved_brr |= i; // do not lose previous state
-    // Acknowledge the trap, clear the "factor" (== cause)
-    set_brr( 0 );
-
-    // Now leave debug mode so that it's safe to run the stub code.
-
-    // Unfortunately, leaving debug mode isn't a self-contained
-    // operation.  The only means of doing it is with a "rett #1"
-    // instruction, which will also restore the previous values of
-    // the ET and S status flags.  We can massage the BPSR
-    // register so that the flags keep their current values, but
-    // we need to save the old one first.
-    i = old_bpsr = get_bpsr ();
-    i |= _BPSR_BS; // Stay in supervisor mode
-    i &= ~_BPSR_BET; // Keep traps disabled
-    set_bpsr (i);
-    HAL_FRV_EXIT_DEBUG_MODE();
-
-    // Only perturb this variable if stopping, not
-    // just for a break instruction.
-    _hal_registers = regs; 
-
-    // Continue with the standard mechanism:
-    __handle_exception();
-
-    // Go back into debug mode.
-    HAL_FRV_ENTER_DEBUG_MODE();
-    // Restore the original BPSR register.
-    set_bpsr (old_bpsr);
-    return;
-}
-
-// ------------------------------------------------------------------------
-
-// Now the routines to manipulate said hardware break and watchpoints.
-
-int cyg_hal_plf_hw_breakpoint(int setflag, void *vaddr, int len)
-{
-    unsigned int addr = (unsigned)vaddr;
-    unsigned int dcr;
-    unsigned int retcode = 0;
-
-    HAL_FRV_ENTER_DEBUG_MODE();
-    dcr = get_dcr();
-
-    // GDB manual suggests that idempotency is required, so first remove
-    // any identical BP in residence.  Implements remove arm anyway.
-    if ( 0 != (dcr & (_DCR_IBE0 | _DCR_IBCE0)) &&
-         get_ibar0() == addr                       )
-        dcr &=~(_DCR_IBE0 | _DCR_IBCE0);
-    else if ( 0 != (dcr & (_DCR_IBE1 | _DCR_IBCE1)) &&
-              get_ibar1() == addr                       )
-        dcr &=~(_DCR_IBE1 | _DCR_IBCE1);
-    else if ( 0 != (dcr & (_DCR_IBE2 | _DCR_IBCE2)) &&
-              get_ibar2() == addr                       )
-        dcr &=~(_DCR_IBE2 | _DCR_IBCE2);
-    else if ( 0 != (dcr & (_DCR_IBE3 | _DCR_IBCE3)) &&
-              get_ibar3() == addr                       )
-        dcr &=~(_DCR_IBE3 | _DCR_IBCE3);
-    else
-        retcode = -1;
-    
-    if (setflag) {
-        retcode = 0; // it is OK really
-        if ( 0 == (dcr & (_DCR_IBE0 | _DCR_IBCE0)) ) {
-	    set_ibar0(addr);
-            dcr |= _DCR_IBE0;
-        }
-	else if ( 0 == (dcr & (_DCR_IBE1 | _DCR_IBCE1)) ) {
-	    set_ibar1(addr);
-            dcr |= _DCR_IBE1;
-        }
-	else if ( 0 == (dcr & (_DCR_IBE2 | _DCR_IBCE2)) ) {
-	    set_ibar2(addr);
-            dcr |= _DCR_IBE2;
-        }
-	else if ( 0 == (dcr & (_DCR_IBE3 | _DCR_IBCE3)) ) {
-	    set_ibar3(addr);
-            dcr |= _DCR_IBE3;
-        }
-	else
-	    retcode = -1;
-    }
-
-    if ( 0 == retcode )
-        set_dcr(dcr);
-    HAL_FRV_EXIT_DEBUG_MODE();
-    return retcode;
-}
-
-int cyg_hal_plf_hw_watchpoint(int setflag, void *vaddr, int len, int type)
-{
-    unsigned int addr = (unsigned)vaddr;
-    unsigned int mode;
-    unsigned int dcr;
-    unsigned int retcode = 0;
-    unsigned long long mask;
-    unsigned int mask0, mask1;
-    int i;
-
-    // Check the length fits within one block.
-    if ( ((~7) & (addr + len - 1)) != ((~7) & addr) )
-        return -1;
-
-    // Assuming big-endian like the platform seems to be...
-
-    // Get masks for the 8-byte span.  00 means enabled, ff means ignore a
-    // byte, which is why this looks funny at first glance.
-    mask = 0x00ffffffffffffffULL >> ((len - 1) << 3);
-    for (i = 0; i < (addr & 7); i++) {
-        mask >>= 8;
-        mask |= 0xff00000000000000ULL;
-    }
-
-    mask0 = mask >> 32;
-    mask1 = mask & 0xffffffffULL;
-
-    addr &=~7; // round to 8-byte block
-
-    HAL_FRV_ENTER_DEBUG_MODE();
-    dcr = get_dcr();
-
-    // GDB manual suggests that idempotency is required, so first remove
-    // any identical WP in residence.  Implements remove arm anyway.
-    if (      0 != (dcr & (7 * _DCR_DBASE0)) &&
-              get_dbar0() == addr            &&
-              get_dbmr00() == mask0 && get_dbmr01() == mask1 )
-        dcr &=~(7 * _DCR_DBASE0);
-    else if ( 0 != (dcr & (7 * _DCR_DBASE1)) &&
-              get_dbar1() == addr&&
-              get_dbmr10() == mask0 && get_dbmr11() == mask1 )
-        dcr &=~(7 * _DCR_DBASE1);
-    else
-        retcode = -1;
-
-    if (setflag) {
-        retcode = 0; // it is OK really
-        if      (type == 2)       mode = 2; // break on write
-        else if (type == 3)       mode = 4; // break on read
-        else if (type == 4)       mode = 6; // break on any access
-        else {
-            mode = 0; // actually add no enable at all.
-            retcode = -1;
-        }
-        if ( 0 == (dcr & (7 * _DCR_DBASE0)) ) {
-            set_dbar0(addr);
-            // Data and Mask 0,1 to zero (mask no bits/bytes)
-            set_dbdr00(0); set_dbdr01(0); set_dbmr00(mask0); set_dbmr01(mask1);
-            mode *= _DCR_DBASE0;
-            dcr |= mode;
-        }
-        else if ( 0 == (dcr & (7 * _DCR_DBASE1)) ) {
-            set_dbar1(addr);
-            set_dbdr10(0); set_dbdr11(0); set_dbmr10(mask0); set_dbmr11(mask1);
-            mode *= _DCR_DBASE1;
-            dcr |= mode;
-        }
-        else
-            retcode = -1;
-    }
-
-    if ( 0 == retcode )
-        set_dcr(dcr);
-    HAL_FRV_EXIT_DEBUG_MODE();
-    return retcode;
-}
-
-// Return indication of whether or not we stopped because of a
-// watchpoint or hardware breakpoint. If stopped by a watchpoint,
-// also set '*data_addr_p' to the data address which triggered the
-// watchpoint.
-int cyg_hal_plf_is_stopped_by_hardware(void **data_addr_p)
-{
-    unsigned int brr;
-    int retcode = HAL_STUB_HW_STOP_NONE;
-    unsigned long long mask;
-
-    // There was a debug event. Check the BRR for details
-    brr = saved_brr;
-    saved_brr = 0;
-
-    if ( brr & (_BRR_IB0 | _BRR_IB1 | _BRR_IB2 | _BRR_IB3) ) {
-        // then it was an instruction break
-        retcode = HAL_STUB_HW_STOP_BREAK;
-    }
-    else if ( brr & (_BRR_DB0 | _BRR_DB1) ) {
-        unsigned int addr, kind;
-        kind = get_dcr();
-        if ( brr & (_BRR_DB0) ) {
-            addr = get_dbar0();
-            kind &= 7 * _DCR_DBASE0;
-            kind /= _DCR_DBASE0;
-            mask = (((unsigned long long)get_dbmr00())<<32) | (unsigned long long)get_dbmr01();
-        } else {
-            addr = get_dbar1();
-            kind &= 7 * _DCR_DBASE1;
-            kind /= _DCR_DBASE1;
-            mask = (((unsigned long long)get_dbmr10())<<32) | (unsigned long long)get_dbmr11();
-        }
-
-        if ( data_addr_p ) {
-            // Scan for a zero byte in the mask - this gives the true address.
-            //              0123456789abcdef
-            while ( 0 != (0xff00000000000000LLU & mask) ) {
-                mask <<= 8;
-                addr++;
-            }
-            *data_addr_p = (void *)addr;
-        }
-
-        // Inverse of the mapping above in the "set" code.
-        if      (kind == 2)       retcode = HAL_STUB_HW_STOP_WATCH;
-        else if (kind == 6)       retcode = HAL_STUB_HW_STOP_AWATCH;
-        else if (kind == 4)       retcode = HAL_STUB_HW_STOP_RWATCH;
-    }
-    return retcode;
-}
-
-// ------------------------------------------------------------------------
-
-#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-
 /*------------------------------------------------------------------------*/
 // EOF frv400_misc.c
Index: packages/redboot/current/doc/redboot_installing.sgml
===================================================================
RCS file: /cvs/ecos/ecos/packages/redboot/current/doc/redboot_installing.sgml,v
retrieving revision 1.16
diff -u -p -5 -r1.16 redboot_installing.sgml
--- packages/redboot/current/doc/redboot_installing.sgml	16 Oct 2003 19:04:02 -0000	1.16
+++ packages/redboot/current/doc/redboot_installing.sgml	5 Sep 2004 20:50:21 -0000
@@ -4654,10 +4654,289 @@ export PLATFORM_DIR=frv400
 description of the associated modes.</para>
 </sect2>
 
 </sect1>
 
+<?Pub _newpage>
+<sect1 id="mb93091">
+<title>Fujitsu FR-V Design Kit (MB93091-CBxx)</title>
+<sect2>
+<title>Overview</title>
+
+<para><indexterm><primary>Fujitsu FR-V MB93091-CBxx Design
+Kit</primary> <secondary>installing and
+testing</secondary></indexterm><indexterm><primary> installing and
+testing </primary><secondary>Fujitsu FR-V MB93091-CBxx Design
+Kit</secondary></indexterm> RedBoot supports both serial ports, which
+are available via the stacked serial connectors on the mother board in
+the case of the FR400 CPU board, and via serial connectors present on
+the other supported CPU boards themselves. The topmost port is the
+default and is considered to be port 0 by RedBoot.  The bottommost
+port is serial port 1.  The default serial port settings are
+115200,8,N,1. The serial port supports baud rates up to 460800, which
+can be set using the <command>baud</command> command as described in
+<xref linkend="RedBoot-Commands-and-Examples">.
+
+</para>
+<para>
+FLASH management is also supported, but only for the FLASH device in IC7. 
+This arrangement allows for IC8 to retain either the original Fujitsu board
+firmware, or some application specific contents.
+Two basic RedBoot configurations are supported:
+
+      <informaltable frame="all">
+	<tgroup cols="4" colsep="1" rowsep="1" align="left">
+	  <thead>
+	    <row>
+	      <entry>Configuration</entry>
+	      <entry>Mode</entry>
+	      <entry>Description</entry>
+	      <entry>File</entry>
+	    </row>
+	  </thead>
+	  <tbody>
+	    <row>
+	      <entry>ROMRAM</entry>
+	      <entry>[ROMRAM]</entry>
+	      <entry>RedBoot running from RAM, but contained in the
+	      board's flash boot sector.</entry>
+	      <entry>redboot_ROMRAM.ecm</entry>
+	    </row>
+	    <row>
+	      <entry>RAM</entry>
+	      <entry>[RAM]</entry>
+	      <entry>RedBoot running from RAM with RedBoot in the
+	      flash boot sector.</entry>
+	      <entry>redboot_RAM.ecm</entry>
+	    </row>
+</tbody>
+</tgroup>
+</informaltable>
+</para>
+<para>Since the normal RedBoot configuration does not use the FLASH ROM
+except during startup, it is unnecessary to load a RAM-based RedBoot
+before reprogramming the FLASH.</para>
+</sect2>
+
+<sect2>
+<title>Initial Installation Method </title>
+
+<para>
+RedBoot can be installed by directly programming the FLASH device in IC7
+or by using the Fujitsu provided software to download and install a
+version into the FLASH device.  Complete instructions are provided
+separately.
+</para>
+
+</sect2>
+
+<sect2>
+<title>Special RedBoot Commands</title>
+
+<para>The <command>exec</command> command as described in <xref linkend="RedBoot-Commands-and-Examples">
+is supported by RedBoot on this target, for executing Linux kernels. Only the command line and timeout options
+are relevant to this platform.</para>
+</sect2>
+
+<sect2>
+<title>Memory Maps</title>
+
+<para>The memory map of this platform is fixed by the hardware (cannot
+be changed by software).  The only attributes which can be modified are
+control over cacheability, as noted below.
+<screen>
+Address                 Cache?      Resource
+00000000-03EFFFFF         Yes       SDRAM (via plugin DIMM)
+03F00000-03FFFFFF         No        SDRAM (used for PCI window)
+10000000-1FFFFFFF         No        MB86943 PCI bridge
+20000000-201FFFFF         No        SRAM
+21000000-23FFFFFF         No        Motherboard resources
+24000000-25FFFFFF         No        PCI I/O space
+26000000-2FFFFFFF         No        PCI Memory space
+30000000-FDFFFFFF         ??        Unused
+FE000000-FEFFFFFF         No        I/O devices
+FF000000-FF1FFFFF         No        IC7 - RedBoot FLASH
+FF200000-FF3FFFFF         No        IC8 - unused FLASH
+FF400000-FFFFFFFF         No        Misc other I/O
+</screen>
+</para>
+
+<note> <title>NOTE</title>
+<para>
+The only configuration currently suppored requires a 64MiB SDRAM 
+DIMM to be present on the CPU card.  No other memory configuration
+is supported at this time.
+</para>
+</note>
+
+</sect2>
+
+<sect2>
+<title>Rebuilding RedBoot</title>
+
+<para>These shell variables provide the platform-specific information
+needed for building RedBoot according to the procedure described in
+<xref linkend="Rebuilding-Redboot">:
+<programlisting>
+export TARGET=mb93091
+export ARCH_DIR=frv
+export PLATFORM_DIR=mb93091
+</programlisting>
+</para>
+
+<para>The names of configuration files are listed above with the
+description of the associated modes.</para>
+</sect2>
+
+<sect2>
+<title>Resource Usage</title>
+
+<para>
+The RedBoot image occupies flash addresses 0xFF000000 - 0xFF03FFFF. To
+execute it copies itself out of there to RAM at 0x03E00000. RedBoot
+reserves memory from 0x00000000 to 0x0001FFFF for its own use.
+User programs can use memory from 0x00020000 to 0x03DFFFFF.
+RAM based RedBoot configurations are
+designed to run from RAM at 0x00020000.
+</para>
+</sect2>
+
+</sect1>
+
+<?Pub _newpage>
+<sect1 id="mb93093">
+<title>Fujitsu FR-V Portable Demonstration Kit (MB93093-PD00)</title>
+<sect2>
+<title>Overview</title>
+
+<para><indexterm><primary>Fujitsu FR-V Portable Demonstration Kit</primary>
+<secondary>installing and testing</secondary></indexterm><indexterm><primary>
+installing and testing
+</primary><secondary>Fujitsu FR-V Portable Demonstration Kit</secondary></indexterm>
+RedBoot supports the serial port which is available via a special cable connected 
+to the CON_UART connector on the board. The default serial port settings are 115200,8,N,1. 
+The serial port supports baud rates up to 460800, which can be set using the <command>baud</command>
+command as described in <xref linkend="RedBoot-Commands-and-Examples">.
+</para>
+
+<para>
+FLASH management is also supported. 
+Two basic RedBoot configurations are supported:
+
+      <informaltable frame="all">
+	<tgroup cols="4" colsep="1" rowsep="1" align="left">
+	  <thead>
+	    <row>
+	      <entry>Configuration</entry>
+	      <entry>Mode</entry>
+	      <entry>Description</entry>
+	      <entry>File</entry>
+	    </row>
+	  </thead>
+	  <tbody>
+	    <row>
+	      <entry>ROMRAM</entry>
+	      <entry>[ROMRAM]</entry>
+	      <entry>RedBoot running from RAM, but contained in the
+	      board's flash boot sector.</entry>
+	      <entry>redboot_ROMRAM.ecm</entry>
+	    </row>
+	    <row>
+	      <entry>RAM</entry>
+	      <entry>[RAM]</entry>
+	      <entry>RedBoot running from RAM with RedBoot in the
+	      flash boot sector.</entry>
+	      <entry>redboot_RAM.ecm</entry>
+	    </row>
+</tbody>
+</tgroup>
+</informaltable>
+</para>
+<para>Since the normal RedBoot configuration does not use the FLASH ROM
+except during startup, it is unnecessary to load a RAM-based RedBoot
+before reprogramming the FLASH.</para>
+</sect2>
+
+<sect2>
+<title>Initial Installation Method </title>
+
+<para>
+The Portable Demonstration Kit should have been shipped with an existing
+version of RedBoot, which can be upgraded to the current version using
+the instructions below. 
+</para>
+
+</sect2>
+
+<sect2>
+<title>Special RedBoot Commands</title>
+
+<para>The <command>exec</command> command as described in <xref linkend="RedBoot-Commands-and-Examples">
+is supported by RedBoot on this target, for executing Linux kernels. Only the command line and timeout options
+are relevant to this platform.</para>
+</sect2>
+
+<sect2>
+<title>Memory Maps</title>
+
+<para>The memory map of this platform is fixed by the hardware (cannot
+be changed by software).  The only attributes which can be modified are
+control over cacheability, as noted below.
+<screen>
+Address                 Cache?      Resource
+00000000-03EFFFFF         Yes       SDRAM (via plugin DIMM)
+03F00000-03FFFFFF         No        Unused (SDRAM)
+10000000-1FFFFFFF         No        AX88796 Ethernet
+20000000-2FFFFFFF         No        System FPGA
+30000000-3FFFFFFF         No        MB93493 companion chip (unused)
+40000000-FCFFFFFF         ??        Unused
+FD000000-FDFFFFFF         ??        FLASH (ROM3,ROM4) (unused)
+FE000000-FEFFFFFF         No        Miscellaneous on-chip I/O
+FF000000-FFFFFFFF         No        RedBoot FLASH (16MiB)
+</screen>
+</para>
+
+<note> <title>NOTE</title>
+<para>
+The only configuration currently suppored requires a 64MiB SDRAM 
+DIMM to be present on the CPU card.  No other memory configuration
+is supported at this time.
+</para>
+</note>
+
+</sect2>
+
+<sect2>
+<title>Rebuilding RedBoot</title>
+
+<para>These shell variables provide the platform-specific information
+needed for building RedBoot according to the procedure described in
+<xref linkend="Rebuilding-Redboot">:
+<programlisting>
+export TARGET=mb93093
+export ARCH_DIR=frv
+export PLATFORM_DIR=mb93093
+</programlisting>
+</para>
+</sect2>
+
+<sect2>
+<title>Resource Usage</title>
+
+<para>
+The RedBoot image occupies flash addresses 0xFF000000 - 0xFF03FFFF. To
+execute it copies itself out of there to RAM at 0x03E00000. RedBoot
+reserves memory from 0x00000000 to 0x0001FFFF for its own use.
+User programs can use memory from 0x00020000 to 0x03DFFFFF.
+RAM based RedBoot configurations are
+designed to run from RAM at 0x00020000.
+</para>
+</sect2>
+
+</sect1>
+
+
 <!-- ********************************* IA32  *************************** -->
 <?Pub _newpage>
 <sect1 id="x86pc">
 <title>IA32/x86 x86-Based PC</title>
 <sect2>


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