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PPC - New platform/variants


Adding Analogue & Micro Rattler - Motorola MPC8250

-- 
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: ecos.db
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ecos.db,v
retrieving revision 1.101
diff -u -5 -p -r1.101 ecos.db
--- ecos.db	18 Aug 2003 08:22:02 -0000	1.101
+++ ecos.db	19 Aug 2003 14:52:04 -0000
@@ -1007,10 +1007,18 @@ package CYGPKG_IO_SERIAL_SH_SCIF {
     directory	      devs/serial/sh/scif
     script	      ser_sh_scif.cdl	
     description       "SH SCIF serial device drivers"
 }
 
+package CYGPKG_DEVS_ETH_PHY {
+	alias 		{ "Generic PHY support" eth_phy_support }
+	hardware
+	directory	devs/eth/phy
+	script		phy_eth_drivers.cdl
+        description     "PHY (ethernet physical transciever) API."
+}
+
 package CYGPKG_DEVS_ETH_ARM_CERF {
 	alias 		{ "Crystal LAN ethernet driver for Cerf boards" cerf_eth_driver }
 	hardware
 	directory	devs/eth/arm/cerf
 	script		cerf_eth_drivers.cdl
@@ -1420,10 +1428,18 @@ package CYGPKG_DEVS_ETH_POWERPC_FEC {
 	directory	devs/eth/powerpc/fec
 	script		fec_eth_drivers.cdl
         description     "Ethernet driver for PowerPC FEC (MPC8xxT) based boards."
 }
 
+package CYGPKG_DEVS_ETH_POWERPC_FCC {
+	alias 		{ "FCC ethernet driver" fcc_eth_driver }
+	hardware
+	directory	devs/eth/powerpc/fcc
+	script		fcc_eth_drivers.cdl
+        description     "Fast ethernet driver for PowerPC MPCxxx based boards."
+}
+
 package CYGPKG_DEVS_ETH_POWERPC_VIPER {
 	alias 		{ "A&M Viper ethernet driver" viper_eth_driver }
 	hardware
 	directory	devs/eth/powerpc/viper
 	script		viper_eth_drivers.cdl
@@ -2794,10 +2810,21 @@ package CYGPKG_HAL_POWERPC_MPC8260 {
            The PowerPC MPC8260 PowerQUICCII variant HAL package provides 
            support for this processor variant. It is also necessary to
            select a specific target platform HAL package."
 }
 
+package CYGPKG_HAL_POWERPC_MPC8XXX {
+	alias		{ "PowerPC MPC8XXX variant HAL" hal_mpc8xxx }
+	directory	hal/powerpc/mpc8xxx/
+	script		hal_powerpc_mpc8xxx.cdl
+	hardware
+        description "
+           The PowerPC MPC8XXX PowerQUICCII variant HAL package provides 
+           support for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+}
+
 package CYGPKG_HAL_POWERPC_MPC8xx {
 	alias		{ "PowerPC 8xx variant HAL" hal_mpc8xx mpc8xx_hal mpc8xx_arch_hal }
 	directory	hal/powerpc/mpc8xx/
 	script		hal_powerpc_mpc8xx.cdl
 	hardware
@@ -4899,6 +4926,52 @@ target adderII {
         }
         enable { CYGHWR_HAL_POWERPC_ADDER_II }
         description "
             The adderII target provides the packages needed to run
             eCos on a A&M Adder PPC852T board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_HAL_POWERPC_RATTLER {
+	alias		{ "A&M Rattler MPC8250 board" hal_powerpc_rattler powerpc_rattler_hal }
+	directory	hal/powerpc/rattler
+	script		hal_powerpc_rattler.cdl
+	hardware
+        description "
+            The RATTLER HAL package provides the support needed to run
+            eCos on a A&M RATTLER board equipped with a PowerPC processor."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_RATTLER {
+        alias           { "A&M Rattler ethernet driver" rattler_eth_driver }
+        hardware
+        directory       devs/eth/powerpc/rattler
+        script          rattler_eth_drivers.cdl
+        description     "Ethernet driver specifics for A&M Rattler (MPC8250) based boards."
+}
+
+package CYGPKG_DEVS_FLASH_POWERPC_RATTLER {
+	alias 		{ "FLASH memory support for A&M Rattler (MPC8250)" flash_rattler }
+	directory	devs/flash/powerpc/rattler
+	script		flash_rattler.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the A&M Rattler (MPC8250) platforms."
+}
+
+target rattler {
+        alias		{ "A&M Rattler (8250) board" }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_MPC8XXX
+                          CYGPKG_HAL_POWERPC_RATTLER
+                          CYGPKG_DEVS_FLASH_POWERPC_RATTLER
+                          CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+                          CYGPKG_DEVS_ETH_POWERPC_FCC
+                          CYGPKG_DEVS_ETH_POWERPC_RATTLER
+                          CYGPKG_DEVS_ETH_PHY
+        }
+        description "
+            The rattler target provides the packages needed to run
+            eCos on an Analogue & Micro Rattler (MPC8250) board."
 }
Index: NEWS
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/NEWS,v
retrieving revision 1.74
diff -u -5 -p -r1.74 NEWS
--- NEWS	5 Jun 2003 13:21:24 -0000	1.74
+++ NEWS	19 Aug 2003 16:30:40 -0000
@@ -1,5 +1,9 @@
+* New port to Analogue & Micro Rattler (Motorola MPC8250)
+* Improved support for ethernet PHY devices.
+* Improved variant support for Motorola Power-QUICC2 systems.
+* Vastly improved networking speeds in RedBoot stack.
 * New port for Motorola PrPMC1100 (Intel XScale IXC1100)
 * SNTP client supports IPv6 multicast packets from time servers.
 * DNS client support looking up IPv6 addresses and reverse lookups
 * FTP client is IPv6 aware.
 * httpd daemon is IPv6 aware.
Index: devs/eth/powerpc/fcc/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/fcc/current/ChangeLog
diff -N devs/eth/powerpc/fcc/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/ChangeLog	19 Aug 2003 16:34:38 -0000
@@ -0,0 +1,46 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/if_fcc.c: 
+	* src/fcc.h: 
+	* cdl/fcc_eth_drivers.cdl: New file(s) - generic ethernet driver
+	for Motorola QUICC-2 FCC controller.  Roughly based on previously
+	contributed devs/eth/powerpc/quicc2 package.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+	
+	
+
Index: devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl
diff -N devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl	19 Aug 2003 16:13:05 -0000
@@ -0,0 +1,132 @@
+# ====================================================================
+#
+#      fcc_eth_drivers.cdl
+#
+#      Ethernet drivers - variant dependent support for PowerPC MPC8xxx
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002, 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  
+# Contributors:   
+# Date:           2003-08-19
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_FCC {
+    display       "MPC8xxx FCC ethernet driver"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_HAL_POWERPC 
+    active_if	  CYGPKG_HAL_POWERPC_MPC8XXX
+
+    include_dir   .
+    include_files ; # none _exported_ whatsoever
+
+    description   "Fast ethernet driver for PowerPC MPC8xxx boards."
+    compile       -library=libextras.a if_fcc.c
+
+    cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE {
+        display       "Buffer size"
+        flavor        data
+        default_value 1540
+        description   "
+            This option specifies the size of the internal buffers used
+            for the PowerPC FCC/ethernet device."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM {
+        display       "Number of output buffers"
+        flavor        data
+        legal_values  2 to 64
+        default_value 8
+        description   "
+            This option specifies the number of output buffer packets
+            to be used for the PowerPC FCC/ethernet device."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM {
+        display       "Number of input buffers"
+        flavor        data
+        legal_values  2 to 64
+        default_value 8
+        description   "
+            This option specifies the number of input buffer packets
+            to be used for the PowerPC FCC/ethernet device."
+    }
+
+    cdl_component CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY {
+        display       "Reset and reconfigure PHY"
+        flavor        bool
+        default_value { CYG_HAL_STARTUP != "RAM" }
+        active_if     CYGPKG_DEVS_ETH_PHY
+        description "
+            This option allows control over the physical transceiver"
+
+        cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_LINK_MODE {
+            display       "Initial link mode"
+            flavor        data
+            legal_values  { "10Mb" "100Mb" "Auto" }
+            default_value { "Auto" }
+            description   "
+                This option specifies initial mode for the physical
+                link.  The PHY will be reset and then set to this mode."
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_POWERPC_FCC_OPTIONS {
+        display "MPC8xxx FCC ethernet driver build options"
+        flavor  none
+	no_define
+
+        cdl_option CYGPKG_DEVS_ETH_POWERPC_FCC_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-D_KERNEL -D__ECOS" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the MPC8xxx FCC ethernet driver package. 
+		These flags are used in addition to the set of global 
+		flags."
+        }
+    }
+}
Index: devs/eth/powerpc/fcc/current/src/fcc.h
===================================================================
RCS file: devs/eth/powerpc/fcc/current/src/fcc.h
diff -N devs/eth/powerpc/fcc/current/src/fcc.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/src/fcc.h	19 Aug 2003 16:13:37 -0000
@@ -0,0 +1,181 @@
+//==========================================================================
+//
+//      fcc.h
+//
+//      PowerPC MPC8xxx fast ethernet (FCC)
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: pfine, mtek
+// Date:         2003-08-19
+// Purpose:      
+// Description:  
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/devs_eth_powerpc_fcc.h>
+// The port connected to the ethernet
+#define FCC1  0
+#define FCC2  1
+
+/* ------------------------ */
+/* FCC REGISTER CONSTANTS   */
+/* ------------------------ */
+
+// GFMR masks (RESET: 0x00000000)
+#define FCC_GFMR_EN_Rx   0x00000020   // Receive enable  
+#define FCC_GFMR_EN_Tx   0x00000010   // Transmit enable
+#define FCC_GFMR_INIT    0x0000000C   // mode=ethernet
+
+//PSMR masks (RESET: 0x00000000)
+#define FCC_PSMR_INIT    0x00000080   // 32-bit CRC
+
+//TODR masks (RESET: 0x0000)
+#define FCC_TOD_INIT     0x0000
+#define FCC_TOD_SET      0x8000
+
+//DSR masks (RESET: 0x7E7E)
+#define FCC_DSR_INIT     0xD555
+
+//FCCE & FCCM (RESET: 0x0000) 
+#define FCC_EV_GRA   0x0080  // Graceful stop
+#define FCC_EV_RXC   0x0040  // A control frame has been received
+#define FCC_EV_TXC   0x0020  // Out of sequence frame sent 
+#define FCC_EV_TXE   0x0010  // Error in transmission channel
+#define FCC_EV_RXF   0x0008  // A complete frame received
+#define FCC_EV_BSY   0x0004  // A received frame discarded due to lack
+                             // of buffers
+#define FCC_EV_TXB   0x0002  // A buffer sent to ethernet
+#define FCC_EV_RXB   0x0001  // A buffer that is a non-complete frame
+                             // is received
+
+/* ------------------------------ */
+/* FCC PARAMETER RAM CONSTANTS    */
+/* ------------------------------ */
+
+#define FCC_FCR_INIT     0x00000000  // Clear the reserved bits
+#define FCC_FCR_MOT_BO   0x10000000  // Motorola byte ordering
+#define FCC_PRAM_C_MASK  0xDEBB20E3  // Constant MASK for CRC
+#define FCC_PRAM_C_PRES  0xFFFFFFFF  // CRC Preset
+#define FCC_PRAM_RETLIM  15          // Retry limit
+#define FCC_PRAM_PER_LO  5           // Persistance
+#define FCC_PRAM_PER_HI  0       
+#define FCC_PRAM_MRBLR   1536    
+#define FCC_MAX_FLR      1518        // Max frame length
+#define FCC_MIN_FLR      64          // Min frame length
+#define FCC_PRAM_PAD_CH  0x8888
+#define FCC_PRAM_MAXD    1520
+#define FCC1_PRAM_OFFSET  0x8400      // Offset of t_Fcc_Pram in 82xx 
+#define FCC2_PRAM_OFFSET  0x8500      // Offset of t_Fcc_Pram in 82xx 
+
+/* ------------------------------ */
+/* BUFFER DESCRIPTOR CONSTANTS    */
+/* ------------------------------ */
+#define FCC_BD_Rx_Empty      0x8000  // Buffer is empty, FCC can fill
+#define FCC_BD_Rx_Wrap       0x2000  // Wrap: Last buffer in ring
+#define FCC_BD_Rx_Int        0x1000  // Interrupt
+#define FCC_BD_Rx_Last       0x0800  // Last buffer in frame
+#define FCC_BD_Rx_Miss       0x0100  // Miss: promiscious mode
+#define FCC_BD_Rx_BC         0x0080  // Broadcast address
+#define FCC_BD_Rx_MC         0x0040  // Multicast address
+#define FCC_BD_Rx_LG         0x0020  // Frame length violation
+#define FCC_BD_Rx_NO         0x0010  // Non-octet aligned frame
+#define FCC_BD_Rx_SH         0x0008  // Short frame
+#define FCC_BD_Rx_CR         0x0004  // CRC error
+#define FCC_BD_Rx_OV         0x0002  // Overrun
+#define FCC_BD_Rx_TR         0x0001  // Frame truncated. late collision
+
+#define FCC_BD_Tx_Ready      0x8000  // Frame ready
+#define FCC_BD_Tx_Pad        0x4000  // Pad short frames
+#define FCC_BD_Tx_Wrap       0x2000  // Wrap: Last buffer in ring
+#define FCC_BD_Tx_Int        0x1000  // Interrupt
+#define FCC_BD_Tx_Last       0x0800  // Last buffer in frame
+#define FCC_BD_Tx_TC         0x0400  // Send CRC after data
+#define FCC_BD_Tx_DEF        0x0200  // Defer indication
+#define FCC_BD_Tx_HB         0x0100  // Heartbeat
+#define FCC_BD_Tx_LC         0x0080  // Late collision
+#define FCC_BD_Tx_RL         0x0040  // Retransmission limit
+#define FCC_BD_Tx_RC         0x003C  // Retry count 
+#define FCC_BD_Tx_UN         0x0002  // Underrun
+#define FCC_BD_Tx_CSL        0x0001  // Carrier sense lost
+#define FCC_BD_Tx_ERRORS     (FCC_BD_Tx_LC|FCC_BD_Tx_RL|FCC_BD_Tx_RC|FCC_BD_Tx_UN|FCC_BD_Tx_CSL)
+
+
+// Buffer descriptor
+struct fcc_bd {
+    volatile unsigned short  ctrl;
+    volatile unsigned short  length;
+    volatile unsigned char  *buffer;
+};
+
+//
+// Info kept about each interface
+//
+struct fcc_eth_info { 
+    // These fields should be defined by the implementation
+    int                       int_vector;
+    char                     *esa_key;        // RedBoot 'key' for device ESA
+    unsigned char             enaddr[6];
+    int                       rxnum;          // Number of Rx buffers
+    unsigned char            *rxbuf;          // Rx buffer space
+    int                       txnum;          // Number of Tx buffers
+    unsigned char            *txbuf;          // Tx buffer space
+#ifdef CYGPKG_DEVS_ETH_PHY
+    eth_phy_access_t         *phy;            // Routines to access PHY
+#endif
+    // The rest of the structure is set up at runtime
+    volatile struct fcc_regs *fcc_reg;        // See "mpc8260.h"
+    struct fcc_bd            *txbd, *rxbd;    // Next Tx,Rx descriptor to use
+    struct fcc_bd            *tbase, *rbase;  // First Tx,Rx descriptor
+    struct fcc_bd            *tnext, *rnext;  // Next descriptor to check for interrupt
+    int                       txsize, rxsize; // Length of individual buffers
+    unsigned long             txkey[CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM];
+#ifdef CYGPKG_NET
+    cyg_interrupt             fcc_eth_interrupt;
+    cyg_handle_t              fcc_eth_interrupt_handle;
+#endif
+};
+
+// CPM_CPCR masks 
+#define CPCR_GRSTOP_TX          0x00000005
+#define CPCR_MCN_FCC            0x00000300
+#define CPCR_READY_TO_RX_CMD   0  /* Ready to receive a command */
Index: devs/eth/powerpc/fcc/current/src/if_fcc.c
===================================================================
RCS file: devs/eth/powerpc/fcc/current/src/if_fcc.c
diff -N devs/eth/powerpc/fcc/current/src/if_fcc.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/src/if_fcc.c	19 Aug 2003 16:14:34 -0000
@@ -0,0 +1,675 @@
+//==========================================================================
+//
+//      dev/if_fcc.c
+//
+//      Fast ethernet device driver for PowerPC MPC8xxx (QUICC-II) boards
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: mtek, pfine
+// Date:         2003-08-19
+// Purpose:      
+// Description:  hardware driver for MPC8xxx FCC
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/devs_eth_powerpc_fcc.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/mpc8xxx.h>
+
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#ifdef CYGPKG_NET
+#include <pkgconf/net.h>
+#endif
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+#include <cyg/io/eth_phy.h>
+#endif
+
+#include "fcc.h"
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+#endif
+#endif
+
+#ifdef CYGDAT_DEVS_FCC_ETH_INL
+#include CYGDAT_DEVS_FCC_ETH_CDL   // platform configury
+#include CYGDAT_DEVS_FCC_ETH_INL   // platform details
+#else
+#error "No board instance defined!"
+#endif
+
+#define ALIGN_TO_CACHE_LINES(x)  ( (long)((x) + 31) & 0xffffffe0 )
+
+// Buffer descriptors are in dual ported RAM, which is marked non-cached
+#define FCC_BDs_NONCACHED
+
+#define os_printf diag_printf
+
+// CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h
+#ifndef CONFIG_ESA
+#define CONFIG_ESA 6      // ethernet address length ...
+#endif
+
+#ifndef CONFIG_BOOL
+#define CONFIG_BOOL 1
+#endif
+
+static void          fcc_eth_int(struct eth_drv_sc *data);
+
+// This ISR is called when the ethernet interrupt occurs
+#ifdef CYGPKG_NET
+static int
+fcc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
+{
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)data;
+    struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+
+    cyg_drv_interrupt_mask(qi->int_vector);
+    return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
+}
+#endif
+
+// Deliver function (ex-DSR) handles the ethernet [logical] processing
+static void
+fcc_eth_deliver(struct eth_drv_sc * sc)
+{
+#ifdef CYGPKG_NET
+    struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+#endif
+
+    fcc_eth_int(sc);
+#ifdef CYGPKG_NET
+    //  Clearing the event register acknowledges FCC interrupt ...
+    cyg_drv_interrupt_unmask(qi->int_vector);
+#endif
+
+}
+
+
+// Initialize the interface - performed at system startup
+// This function must set up the interface, including arranging to
+// handle interrupts, etc, so that it may be "started" cheaply later.
+static bool 
+fcc_eth_init(struct cyg_netdevtab_entry *dtp)
+{
+    struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
+    struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+    volatile t_Fcc_Pram  *fcc =  (volatile t_Fcc_Pram *)0;
+    volatile t_EnetFcc_Pram *E_fcc;
+    int i, fcc_chan;
+    bool esa_ok;
+    unsigned char *c_ptr;
+    unsigned char _enaddr[6];
+    unsigned long rxbase, txbase;
+    struct fcc_bd *rxbd, *txbd;
+    // The FCC seems rather picky about these...
+    static long rxbd_base = 0x3000;
+    static long txbd_base = 0xB000;
+
+    // Set up pointers to FCC controller
+    switch (qi->int_vector) {
+    case CYGNUM_HAL_INTERRUPT_FCC1:
+        qi->fcc_reg = &(IMM->fcc_regs[FCC1]);
+        fcc =  (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC1_PRAM_OFFSET);
+        fcc_chan = FCC1_PAGE_SUBBLOCK;
+        break;
+    case CYGNUM_HAL_INTERRUPT_FCC2:
+        qi->fcc_reg = &(IMM->fcc_regs[FCC2]);
+        fcc =  (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC2_PRAM_OFFSET);
+        fcc_chan = FCC2_PAGE_SUBBLOCK;
+        break;
+    default:
+        os_printf("Can't initialize '%s' - unknown FCC!\n", dtp->name);
+        return false;
+    }
+
+    // just in case :  disable Transmit and Receive 
+    qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
+    
+    // Try to read the ethernet address of the transciever ...
+#ifdef CYGPKG_REDBOOT
+    esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
+#else
+    esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, 
+                                         qi->esa_key, _enaddr, CONFIG_ESA);
+#endif
+    if (esa_ok) {
+        memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
+    } else {
+        // No 'flash config' data available - use default
+        os_printf("FCC_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
+    }
+
+    // Initialize Receive Buffer Descriptors
+    rxbase = rxbd_base;
+    fcc->riptr = rxbase;           // temp work buffer
+    fcc->mrblr = FCC_PRAM_MRBLR;   // Max Rx buffer 
+    fcc->rstate &= FCC_FCR_INIT;
+    fcc->rstate |= FCC_FCR_MOT_BO;
+    rxbase += 64;
+    rxbd_base += sizeof(struct fcc_bd)*qi->rxnum + 64;
+    rxbd = (struct fcc_bd *)(CYGARC_IMM_BASE + rxbase);
+    fcc->rbase = (CYG_WORD)rxbd;
+    c_ptr = qi->rxbuf;
+    qi->rbase = rxbd;
+    qi->rxbd  = rxbd;
+    qi->rnext = rxbd;
+
+    for (i = 0; i < qi->rxnum; i++, rxbd++) {
+        rxbd->ctrl   = (FCC_BD_Rx_Empty | FCC_BD_Rx_Int);
+        rxbd->length = 0;                   // reset 
+        c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
+        rxbd->buffer = (volatile unsigned char *)c_ptr;
+        c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
+    }
+    rxbd--;
+    rxbd->ctrl |= FCC_BD_Rx_Wrap;
+
+    // Initialize Transmit Buffer Descriptors
+    txbase = txbd_base;
+    fcc->tiptr = txbase;   // in dual port RAM (see 28-11)
+    fcc->tstate &= FCC_FCR_INIT;
+    fcc->tstate |= FCC_FCR_MOT_BO;
+    txbase += 64;
+    txbd_base += sizeof(struct fcc_bd)*qi->txnum + 64;
+    txbd = (struct fcc_bd *)(CYGARC_IMM_BASE + txbase);
+    fcc->tbase = (CYG_WORD)txbd;
+    c_ptr = qi->txbuf;
+    qi->tbase = txbd;
+    qi->txbd  = txbd;
+    qi->tnext = txbd;
+
+    for (i = 0; i < qi->txnum; i++, txbd++) {
+        txbd->ctrl   = (FCC_BD_Tx_Pad | FCC_BD_Tx_Int);  
+        txbd->length = 0;   // reset : Write before send
+        c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
+        txbd->buffer = (volatile unsigned char  *)c_ptr;
+        c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
+    }
+    txbd--;
+    txbd->ctrl |= FCC_BD_Tx_Wrap;
+    
+    // Ethernet Specific FCC Parameter RAM Initialization     
+    E_fcc = &(fcc->SpecificProtocol.e);
+    E_fcc->c_mask   = FCC_PRAM_C_MASK; // (see 30-9)
+    E_fcc->c_pres   = FCC_PRAM_C_PRES;
+    E_fcc->crcec    = 0;
+    E_fcc->alec     = 0;
+    E_fcc->disfc    = 0;
+    E_fcc->ret_lim  = FCC_PRAM_RETLIM;
+    E_fcc->p_per    = FCC_PRAM_PER_LO;
+    E_fcc->gaddr_h  = 0;
+    E_fcc->gaddr_l  = 0;
+    E_fcc->tfcstat  = 0;
+    E_fcc->mflr     = FCC_MAX_FLR;
+
+    E_fcc->paddr1_h = ((short)qi->enaddr[5] << 8) | qi->enaddr[4];
+    E_fcc->paddr1_m = ((short)qi->enaddr[3] << 8) | qi->enaddr[2];
+    E_fcc->paddr1_l = ((short)qi->enaddr[1] << 8) | qi->enaddr[0];
+
+    E_fcc->iaddr_h  = 0;
+    E_fcc->iaddr_l  = 0;
+    E_fcc->minflr   = FCC_MIN_FLR;
+    E_fcc->taddr_h  = 0;
+    E_fcc->taddr_m  = 0;
+    E_fcc->taddr_l  = 0;
+    E_fcc->pad_ptr  = fcc->tiptr; // No special padding char ...
+    E_fcc->cf_type  = 0;
+    E_fcc->maxd1    = FCC_PRAM_MAXD;
+    E_fcc->maxd2    = FCC_PRAM_MAXD;
+
+    // FCC register initialization 
+    qi->fcc_reg->fcc_gfmr = FCC_GFMR_INIT; 
+    qi->fcc_reg->fcc_psmr = FCC_PSMR_INIT;
+    qi->fcc_reg->fcc_dsr  = FCC_DSR_INIT;
+
+#ifdef CYGPKG_NET
+    // clear the events of FCCX
+    qi->fcc_reg->fcc_fcce = 0xFFFF;   
+    qi->fcc_reg->fcc_fccm = FCC_EV_TXE | FCC_EV_TXB | FCC_EV_RXF;
+
+    // Set up to handle interrupts
+    cyg_drv_interrupt_create(qi->int_vector,
+                             0,  // Highest //CYGARC_SIU_PRIORITY_HIGH,
+                             (cyg_addrword_t)sc, //  Data passed to ISR
+                             (cyg_ISR_t *)fcc_eth_isr,
+                             (cyg_DSR_t *)eth_drv_dsr,
+                             &qi->fcc_eth_interrupt_handle,
+                             &qi->fcc_eth_interrupt);
+    cyg_drv_interrupt_attach(qi->fcc_eth_interrupt_handle);
+    cyg_drv_interrupt_acknowledge(qi->int_vector);
+    cyg_drv_interrupt_unmask(qi->int_vector);
+#else
+
+    // Mask the interrupts 
+    qi->fcc_reg->fcc_fccm = 0;
+#endif
+
+    // Issue Init RX & TX Parameters Command for FCCx
+    while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); 
+    IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
+        fcc_chan |
+        CPCR_MCN_FCC | 
+        CPCR_FLG;              /* ISSUE COMMAND */
+    while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); 
+
+#ifdef CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
+    {
+        unsigned short phy_state;
+        unsigned short reset_mode;
+        int phy_unit = 0;
+        int phy_ok;
+        int phy_timeout = 5*100;
+
+        // Reset PHY (transceiver)
+        _eth_phy_init(qi->phy);
+
+        if (_eth_phy_read(qi->phy, PHY_BMSR, phy_unit, &phy_state)) {
+            if ((phy_state & PHY_BMSR_LINK) !=  PHY_BMSR_LINK) {
+                _eth_phy_write(qi->phy, PHY_BMCR, phy_unit, PHY_BMCR_RESET);
+                for (i = 0;  i < 10;  i++) {
+                    phy_ok = _eth_phy_read(qi->phy, PHY_BMCR, phy_unit, &phy_state);
+                    if (!phy_ok) break;
+                    if (!(phy_state & PHY_BMCR_RESET)) break;
+                }
+                if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
+                    diag_printf("%s: Can't get PHY unit to soft reset: %x\n", dtp->name, phy_state);
+                    return false;
+                }
+                reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX;
+                _eth_phy_write(qi->phy, PHY_BMCR, phy_unit, reset_mode);
+                while (phy_timeout-- >= 0) {
+                    phy_ok = _eth_phy_read(qi->phy, PHY_BMSR, phy_unit, &phy_state);
+                    if (phy_ok && (phy_state & PHY_BMSR_LINK)) {
+                        break;
+                    } else {
+                        CYGACC_CALL_IF_DELAY_US(10000);   // 10ms
+                    }
+                }
+                if (phy_timeout <= 0) {
+                    diag_printf("** %s Warning: PHY LINK UP failed\n", dtp->name);
+                }
+            }
+            else {
+                diag_printf("** %s Info: PHY LINK already UP \n", dtp->name);
+            }
+        }
+    }
+#endif // CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
+
+    // Initialize upper level driver for ecos
+    (sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
+
+    return true;
+}
+ 
+//
+// This function is called to "start up" the interface.  It may be called
+// multiple times, even when the hardware is already running.  It will be
+// called whenever something "hardware oriented" changes and should leave
+// the hardware ready to send/receive packets.
+//
+static void
+fcc_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+    
+  // Enable the device : 
+  // Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive
+  qi->fcc_reg->fcc_gfmr |= (FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
+  
+}
+
+//
+// This function is called to shut down the interface.
+//
+static void
+fcc_eth_stop(struct eth_drv_sc *sc)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  
+  // Disable the device : 
+  // Clear the ENT/ENR bits in the GFMR -- Disable Transmit/Receive
+  qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
+}
+
+
+//
+// This function is called for low level "control" operations
+//
+static int
+fcc_eth_control(struct eth_drv_sc *sc, unsigned long key,
+                void *data, int length)
+{
+  switch (key) {
+  case ETH_DRV_SET_MAC_ADDRESS:
+    return 0;
+    break;
+  default:
+    return 1;
+    break;
+  }
+}
+
+
+//
+// This function is called to see if another packet can be sent.
+// It should return the number of packets which can be handled.
+// Zero should be returned if the interface is busy and can not send any more.
+//
+static int
+fcc_eth_can_send(struct eth_drv_sc *sc)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  volatile struct fcc_bd *txbd = qi->txbd;
+#ifndef FCC_BDs_NONCACHED
+  int cache_state;
+#endif
+
+#ifndef FCC_BDs_NONCACHED
+  HAL_DCACHE_IS_ENABLED(cache_state);
+  if (cache_state) {
+    HAL_DCACHE_INVALIDATE(fcc_eth_txring, 
+                          8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+  }
+#endif
+
+  return ((txbd->ctrl & FCC_BD_Tx_Ready) == 0);
+}
+
+//
+// This routine is called to send data to the hardware.
+static void 
+fcc_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, 
+             int total_len, unsigned long key)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  struct fcc_bd *txbd, *txfirst;
+  volatile char *bp;
+  int i, txindex;
+  int cache_state;    
+
+  HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FCC_BDs_NONCACHED
+  if (cache_state) {
+    HAL_DCACHE_INVALIDATE(fcc_eth_txring, 
+                          8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+  }
+#endif
+ 
+  // Find a free buffer
+  txbd = txfirst = qi->txbd;
+  while (txbd->ctrl & FCC_BD_Tx_Ready) {
+    // This buffer is busy, move to next one
+    if (txbd->ctrl & FCC_BD_Tx_Wrap) {
+      txbd = qi->tbase;
+    } else {
+      txbd++;
+    }
+    if (txbd == txfirst) {
+#ifdef CYGPKG_NET
+      panic ("No free xmit buffers");
+#else
+      os_printf("FCC Ethernet: No free xmit buffers\n");
+#endif
+    }
+  }
+
+  // Remember the next buffer to try
+  if (txbd->ctrl & FCC_BD_Tx_Wrap) {
+    qi->txbd = qi->tbase;
+  } else {
+    qi->txbd = txbd+1;
+  }
+
+  txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
+  qi->txkey[txindex] = key;
+
+  // Set up buffer
+  txbd->length = total_len;
+  bp = txbd->buffer;
+  for (i = 0;  i < sg_len;  i++) {
+    memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
+    bp += sg_list[i].len;
+  }
+
+  // Make sure no stale data buffer ...
+  if (cache_state) {
+    HAL_DCACHE_FLUSH(txbd->buffer, txbd->length);
+  }
+
+  // Send it on it's way
+  txbd->ctrl |= FCC_BD_Tx_Ready | FCC_BD_Tx_Last | FCC_BD_Tx_TC;
+
+#ifndef FCC_BDs_NONCACHED
+  if (cache_state) {
+    HAL_DCACHE_FLUSH(fcc_eth_txring, 
+                     8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);  
+  }
+#endif  
+
+}
+
+//
+// This function is called when a packet has been received.  It's job is
+// to prepare to unload the packet from the hardware.  Once the length of
+// the packet is known, the upper layer of the driver can be told.  When
+// the upper layer is ready to unload the packet, the internal function
+// 'fcc_eth_recv' will be called to actually fetch it from the hardware.
+//
+static void
+fcc_eth_RxEvent(struct eth_drv_sc *sc)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  struct fcc_bd *rxbd;
+  int cache_state;
+
+  HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FCC_BDs_NONCACHED
+  if (cache_state) {
+    HAL_DCACHE_INVALIDATE(fcc_eth_rxring, 
+                          8*CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM);
+  }
+#endif
+
+  rxbd = qi->rnext;
+  while ((rxbd->ctrl & FCC_BD_Rx_Empty) == 0) {
+    qi->rxbd = rxbd;  // Save for callback
+
+    // This is the right way of doing it, but dcbi has a bug ...
+    //    if (cache_state) {
+    //      HAL_DCACHE_INVALIDATE(rxbd->buffer, rxbd->length); 
+    //    }
+    (sc->funs->eth_drv->recv)(sc, rxbd->length);
+#if 1 // Coherent caches?
+    if (cache_state) {
+      HAL_DCACHE_FLUSH(rxbd->buffer, rxbd->length); 
+    }
+#endif
+    rxbd->ctrl |= FCC_BD_Rx_Empty;
+    if (rxbd->ctrl & FCC_BD_Rx_Wrap) {
+      rxbd = qi->rbase;
+    } else {
+      rxbd++;
+    }
+  }
+  // Remember where we left off
+  qi->rnext = (struct fcc_bd *)rxbd;
+
+  // Make sure no stale data
+#ifndef FCC_BDs_NONCACHED
+  if (cache_state) {
+    HAL_DCACHE_FLUSH(fcc_eth_rxring, 
+                     8*CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM);
+  }
+#endif
+
+}
+
+//
+// This function is called as a result of the "eth_drv_recv()" call above.
+// It's job is to actually fetch data for a packet from the hardware once
+// memory buffers have been allocated for the packet.  Note that the buffers
+// may come in pieces, using a scatter-gather list.  This allows for more
+// efficient processing in the upper layers of the stack.
+//
+static void
+fcc_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  unsigned char *bp;
+  int i;
+  
+  bp = (unsigned char *)qi->rxbd->buffer;
+
+  for (i = 0;  i < sg_len;  i++) {
+    if (sg_list[i].buf != 0) {
+      memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
+      bp += sg_list[i].len;
+    }
+  }
+
+}
+
+static void
+fcc_eth_TxEvent(struct eth_drv_sc *sc, int stat)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  struct fcc_bd *txbd;
+  int txindex;
+#ifndef FCC_BDs_NONCACHED
+  int cache_state;
+#endif
+
+#ifndef FCC_BDs_NONCACHED
+  // Make sure no stale data
+  HAL_DCACHE_IS_ENABLED(cache_state);
+  if (cache_state) {
+    HAL_DCACHE_INVALIDATE(fcc_eth_txring, 
+                          8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+  }
+#endif
+
+  txbd = qi->tnext;
+  // Note: TC field is used to indicate the buffer has/had data in it
+  while ( (txbd->ctrl & (FCC_BD_Tx_TC | FCC_BD_Tx_Ready)) == FCC_BD_Tx_TC ) {
+      if ((txbd->ctrl & FCC_BD_Tx_ERRORS) != 0) {
+#if 0
+          diag_printf("FCC Tx error BD: %x/%x- ", txbd, txbd->ctrl);
+          if ((txbd->ctrl & FCC_BD_Tx_LC) != 0) diag_printf("Late Collision/");
+          if ((txbd->ctrl & FCC_BD_Tx_RL) != 0) diag_printf("Retry limit/");
+//          if ((txbd->ctrl & FCC_BD_Tx_RC) != 0) diag_printf("Late Collision/");
+          if ((txbd->ctrl & FCC_BD_Tx_UN) != 0) diag_printf("Underrun/");
+          if ((txbd->ctrl & FCC_BD_Tx_CSL) != 0) diag_printf("Carrier Lost/");
+          diag_printf("\n");
+#endif
+      }
+
+    txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
+    (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
+    txbd->ctrl &= ~FCC_BD_Tx_TC;
+    if (txbd->ctrl & FCC_BD_Tx_Wrap) {
+      txbd = qi->tbase;
+    } else {
+      txbd++;
+    }
+  }
+  // Remember where we left off
+  qi->tnext = (struct fcc_bd *)txbd;
+
+  // Make sure no stale data  
+#ifndef FCC_BDs_NONCACHED
+  if (cache_state) {
+    HAL_DCACHE_FLUSH(fcc_eth_txring, 
+                     8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+  }
+#endif
+
+}
+
+//
+// Interrupt processing
+//
+static void          
+fcc_eth_int(struct eth_drv_sc *sc)
+{
+  struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+  unsigned short iEvent;
+
+  while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){
+    // Clear pending interrupts (writing 1's to this register)
+    qi->fcc_reg->fcc_fcce = iEvent; 
+    // Tx Done or Tx Error
+    if ( iEvent & (FCC_EV_TXB | FCC_EV_TXE) ) {     
+      fcc_eth_TxEvent(sc, iEvent);
+    }
+    // Complete or non-complete frame receive
+    if (iEvent & (FCC_EV_RXF | FCC_EV_RXB) ) {    
+      fcc_eth_RxEvent(sc);
+    }
+  }
+}
+
+//
+// Interrupt vector
+//
+static int          
+fcc_eth_int_vector(struct eth_drv_sc *sc)
+{
+    struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+    return (qi->int_vector);
+}
+
Index: devs/eth/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.20
diff -u -5 -p -r1.20 ChangeLog
--- devs/eth/powerpc/quicc/current/ChangeLog	15 Jul 2003 00:57:45 -0000	1.20
+++ devs/eth/powerpc/quicc/current/ChangeLog	19 Aug 2003 16:16:03 -0000
@@ -1,5 +1,10 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/if_quicc.c (quicc_eth_init): Use 'quicc_eth_command()'
+	function instead of brute-force inline code.
+
 2003-07-14  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/if_quicc.c (quicc_eth_init): Only flush cache if enabled.
 
 	* cdl/quicc_eth_drivers.cdl: Force serial debug messages during
Index: devs/eth/powerpc/quicc/current/src/if_quicc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c,v
retrieving revision 1.20
diff -u -5 -p -r1.20 if_quicc.c
--- devs/eth/powerpc/quicc/current/src/if_quicc.c	15 Jul 2003 00:57:45 -0000	1.20
+++ devs/eth/powerpc/quicc/current/src/if_quicc.c	15 Jul 2003 14:12:35 -0000
@@ -157,10 +157,11 @@ clear_led(int bit)
 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
 static cyg_interrupt quicc_eth_interrupt;
 static cyg_handle_t  quicc_eth_interrupt_handle;
 #endif
 static void          quicc_eth_int(struct eth_drv_sc *data);
+static void          quicc_eth_command(struct eth_drv_sc *sc, unsigned long cmd);
 
 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
 // This ISR is called when the ethernet interrupt occurs
 static int
 quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
@@ -364,12 +365,11 @@ quicc_eth_init(struct cyg_netdevtab_entr
     enet_pram->taddr_h = 0;
     enet_pram->taddr_m = 0;
     enet_pram->taddr_l = 0;
 
     // Initialize the CPM (set up buffer pointers, etc).
-    eppc->cp_cr = QUICC_CPM_SCCx | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
-    while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
+    quicc_eth_command(sc, QUICC_CPM_CR_INIT_TXRX);
 
     // Clear any pending interrupt/exceptions
     scc->scc_scce = 0xFFFF;
 
     // Enable interrupts
@@ -707,18 +707,16 @@ quicc_eth_recv(struct eth_drv_sc *sc, st
     else
         qi->rx_resource++;
 
 }
 
-
 static void
 quicc_eth_command( struct eth_drv_sc *sc, unsigned long cmd)
 {
    volatile EPPC *eppc = (volatile EPPC *)eppc_base();
    
    eppc->cp_cr = QUICC_CPM_SCCx | cmd | QUICC_CPM_CR_BUSY;
-
    while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
        continue;
 }
 
 static void
Index: devs/eth/powerpc/rattler/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/rattler/current/ChangeLog
diff -N devs/eth/powerpc/rattler/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/rattler/current/ChangeLog	19 Aug 2003 16:36:13 -0000
@@ -0,0 +1,44 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* include/rattler_eth.inl: 
+	* cdl/rattler_eth_drivers.cdl: New file(s) - platform specifics
+	for ethernet drivers on Analogue & Micro Rattler (MPC8250) board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+	
+	
+
Index: devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
diff -N devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl	19 Aug 2003 16:35:47 -0000
@@ -0,0 +1,92 @@
+#====================================================================
+#
+#      rattler_eth_drivers.cdl
+#
+#      Hardware specifics for A&M Rattler ethernet
+#
+#====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas, hmt
+# Original data:  gthomas
+# Contributors:   gthomas, F.Robbins
+# Date:           2003-08-19
+#
+#####DESCRIPTIONEND####
+#
+#====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_RATTLER {
+    display       "A&M Rattler (MPC8250) ethernet support"
+    description   "Hardware specifics for A&M Rattler ethernet"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_HAL_POWERPC 
+    active_if	  CYGPKG_HAL_POWERPC_MPC8XXX
+
+    requires      CYGPKG_DEVS_ETH_POWERPC_FCC
+    requires      CYGPKG_HAL_POWERPC_RATTLER
+
+    cdl_option CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1 {
+        display       "Include fcc1/eth0 ethernet device"
+        default_value 1
+        description   "
+          This option controls whether a driver for FCC1/eth0
+          is included in the resulting system."
+        implements    CYGHWR_NET_DRIVERS
+        implements    CYGHWR_NET_DRIVER_ETH0
+    }
+
+    cdl_option CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC2 {
+        display       "Include fcc2/eth1 ethernet device"
+        default_value 1
+        description   "
+          This option controls whether a driver for FCC2/eth1
+          is included in the resulting system."
+        implements    CYGHWR_NET_DRIVERS
+        implements    CYGHWR_NET_DRIVER_ETH1
+        requires      CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1
+    }
+
+    include_dir   cyg/io
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGDAT_DEVS_FCC_ETH_CDL <pkgconf/devs_eth_powerpc_rattler.h>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_FCC_ETH_INL <cyg/io/rattler_eth.inl>"
+    }
+}
Index: devs/eth/powerpc/rattler/current/include/rattler_eth.inl
===================================================================
RCS file: devs/eth/powerpc/rattler/current/include/rattler_eth.inl
diff -N devs/eth/powerpc/rattler/current/include/rattler_eth.inl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/rattler/current/include/rattler_eth.inl	19 Aug 2003 16:36:14 -0000
@@ -0,0 +1,311 @@
+#ifndef CYGONCE_DEVS_RATTLER_ETH_INL
+#define CYGONCE_DEVS_RATTLER_ETH_INL
+//==========================================================================
+//
+//      rattler_eth.inl
+//
+//      Hardware specifics for A&M Rattler ethernet support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas,F.Robbins
+// Date:         2003-08-19
+// Purpose:      
+// Description:  
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// 
+// Pin layout for PHY connections
+//
+#define FCC1_PHY_RESET 0x01000000
+#define FCC1_PHY_DATA  0x10000000
+#define FCC1_PHY_CLOCK 0x20000000
+#define FCC2_PHY_RESET 0x02000000
+#define FCC2_PHY_DATA  0x04000000
+#define FCC2_PHY_CLOCK 0x08000000
+
+#ifdef CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1
+//
+// Initialize the PHY associated with FCC1/eth0
+//
+static void 
+fcc1_phy_init(void)
+{
+    // Set up PHY reset line
+    IMM->io_regs[PORT_B].pdat &= ~FCC1_PHY_RESET;
+    IMM->io_regs[PORT_B].pdat |= FCC1_PHY_RESET;
+    IMM->io_regs[PORT_C].pdir |= FCC1_PHY_CLOCK;
+}
+
+//
+// Set up a particular data bit for FCC1/eth0
+//
+static void 
+fcc1_phy_set_data(int val)
+{
+    if (val) {
+        // Output
+        IMM->io_regs[PORT_C].pdat |= FCC1_PHY_DATA;
+    } else {
+        // Input
+        IMM->io_regs[PORT_C].pdat &= ~FCC1_PHY_DATA;
+    }
+}
+
+//
+// Read the current data bit for FCC1/eth0
+//
+static int  
+fcc1_phy_get_data(void)
+{
+    if ((IMM->io_regs[PORT_C].pdat & FCC1_PHY_DATA) != 0) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+//
+// Set the clock bit for FCC1/eth0
+//
+static void 
+fcc1_phy_set_clock(int val)
+{
+    if (val) {
+        // Output
+        IMM->io_regs[PORT_C].pdat |= FCC1_PHY_CLOCK;
+    } else {
+        // Input
+        IMM->io_regs[PORT_C].pdat &= ~FCC1_PHY_CLOCK;
+    }
+}
+
+//
+// Set the clock/data direction for FCC1/eth0
+// Note: always forces clock to be an output
+//
+static void 
+fcc1_phy_set_dir(int data_dir)
+{
+    if (data_dir) {
+        // Output
+        IMM->io_regs[PORT_C].pdir |= FCC1_PHY_DATA;
+    } else {
+        // Input
+        IMM->io_regs[PORT_C].pdir &= ~FCC1_PHY_DATA;
+    }
+}
+
+ETH_PHY_ACCESS_FUNS(fcc1_phy,
+                    fcc1_phy_init,
+                    fcc1_phy_set_data,
+                    fcc1_phy_get_data,
+                    fcc1_phy_set_clock,
+                    fcc1_phy_set_dir);
+
+static unsigned char fcc_eth0_rxbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM *
+                                    (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+static unsigned char fcc_eth0_txbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM *
+                                    (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+RedBoot_config_option("FCC1/eth0 Network hardware address [MAC]",
+                      fcc1_esa,
+                      ALWAYS_ENABLED, true,
+                      CONFIG_ESA, 0
+    );
+#endif
+
+static struct fcc_eth_info fcc_eth0_info = {
+    CYGNUM_HAL_INTERRUPT_FCC1,               // Interrupt
+    "fcc1_esa",                              // ESA 'key'
+    { 0x00, 0x08, 0xe5, 0x11, 0x22, 0x33 },  // Fallback ESA
+    CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM,       // Number of Rx buffers
+    fcc_eth0_rxbufs,                         // Pointer to buffers
+    CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM,       // Number of Tx buffers
+    fcc_eth0_txbufs,                         // Pointer to buffers    
+    &fcc1_phy,
+};
+
+ETH_DRV_SC(fcc_eth0_sc,
+           &fcc_eth0_info,     // Driver specific data
+           "eth0",             // Name for this interface
+           fcc_eth_start,
+           fcc_eth_stop,
+           fcc_eth_control,
+           fcc_eth_can_send,
+           fcc_eth_send,
+           fcc_eth_recv,
+           fcc_eth_deliver,
+           fcc_eth_int,
+           fcc_eth_int_vector);
+
+NETDEVTAB_ENTRY(fcc_eth0_netdev, 
+                "fcc_eth0", 
+                fcc_eth_init, 
+                &fcc_eth0_sc);
+#endif // CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1
+
+#ifdef CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC2
+//
+// Initialize the PHY associated with FCC2/eth1
+//
+static void 
+fcc2_phy_init(void)
+{
+    // Set up PHY reset line
+    IMM->io_regs[PORT_B].pdat &= ~FCC2_PHY_RESET;
+    IMM->io_regs[PORT_B].pdat |= FCC2_PHY_RESET;
+    IMM->io_regs[PORT_C].pdir |= FCC2_PHY_CLOCK;
+}
+
+//
+// Set up a particular data bit for FCC2/eth1
+//
+static void 
+fcc2_phy_set_data(int val)
+{
+    if (val) {
+        // Output
+        IMM->io_regs[PORT_C].pdat |= FCC2_PHY_DATA;
+    } else {
+        // Input
+        IMM->io_regs[PORT_C].pdat &= ~FCC2_PHY_DATA;
+    }
+}
+
+//
+// Read the current data bit for FCC2/eth1
+//
+static int  
+fcc2_phy_get_data(void)
+{
+    if ((IMM->io_regs[PORT_C].pdat & FCC2_PHY_DATA) != 0) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+//
+// Set the clock bit for FCC2/eth1
+//
+static void 
+fcc2_phy_set_clock(int val)
+{
+    if (val) {
+        // Output
+        IMM->io_regs[PORT_C].pdat |= FCC2_PHY_CLOCK;
+    } else {
+        // Input
+        IMM->io_regs[PORT_C].pdat &= ~FCC2_PHY_CLOCK;
+    }
+}
+
+//
+// Set the clock/data direction for FCC2/eth1
+// Note: always forces clock to be an output
+//
+static void 
+fcc2_phy_set_dir(int data_dir)
+{
+    if (data_dir) {
+        // Output
+        IMM->io_regs[PORT_C].pdir |= FCC2_PHY_DATA;
+    } else {
+        // Input
+        IMM->io_regs[PORT_C].pdir &= ~FCC2_PHY_DATA;
+    }
+}
+
+ETH_PHY_ACCESS_FUNS(fcc2_phy,
+                    fcc2_phy_init,
+                    fcc2_phy_set_data,
+                    fcc2_phy_get_data,
+                    fcc2_phy_set_clock,
+                    fcc2_phy_set_dir);
+
+static unsigned char fcc_eth1_rxbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM *
+                                    (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+static unsigned char fcc_eth1_txbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM *
+                                    (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+RedBoot_config_option("FCC2/eth1 Network hardware address [MAC]",
+                      fcc2_esa,
+                      ALWAYS_ENABLED, true,
+                      CONFIG_ESA, 0
+    );
+#endif
+
+static struct fcc_eth_info fcc_eth1_info = {
+    CYGNUM_HAL_INTERRUPT_FCC2,               // Interrupt
+    "fcc2_esa",                              // ESA 'key'
+    { 0x00, 0x08, 0xe5, 0x11, 0x22, 0x33 },  // Fallback ESA
+    CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM,       // Number of Rx buffers
+    fcc_eth1_rxbufs,                         // Pointer to buffers
+    CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM,       // Number of Tx buffers
+    fcc_eth1_txbufs,                         // Pointer to buffers    
+    &fcc2_phy,
+};
+
+ETH_DRV_SC(fcc_eth1_sc,
+           &fcc_eth1_info,     // Driver specific data
+           "eth1",             // Name for this interface
+           fcc_eth_start,
+           fcc_eth_stop,
+           fcc_eth_control,
+           fcc_eth_can_send,
+           fcc_eth_send,
+           fcc_eth_recv,
+           fcc_eth_deliver,
+           fcc_eth_int,
+           fcc_eth_int_vector);
+
+NETDEVTAB_ENTRY(fcc_eth1_netdev, 
+                "fcc_eth1", 
+                fcc_eth_init, 
+                &fcc_eth1_sc);
+#endif // CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC2
+
+#endif  // CYGONCE_DEVS_RATTLER_ETH_INL
+// ------------------------------------------------------------------------
Index: devs/flash/powerpc/rattler/current/ChangeLog
===================================================================
RCS file: devs/flash/powerpc/rattler/current/ChangeLog
diff -N devs/flash/powerpc/rattler/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/rattler/current/ChangeLog	19 Aug 2003 16:38:11 -0000
@@ -0,0 +1,41 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/rattler_flash.c: 
+	* cdl/flash_rattler.cdl: New file(s) - platform support for
+	FLASH on Analogue & Micro Rattler (MPC8250) boards.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl
===================================================================
RCS file: devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl
diff -N devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl	19 Aug 2003 16:37:15 -0000
@@ -0,0 +1,75 @@
+# ====================================================================
+#
+#      flash_rattler.cdl
+#
+#      FLASH memory - Hardware support on A&M Rattler (MPC8250)
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           2003-08-19
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_POWERPC_RATTLER {
+    display       "A&M Rattler (MPC8250) FLASH memory support"
+
+    parent        CYGPKG_IO_FLASH
+    active_if	  CYGPKG_IO_FLASH
+    requires	  CYGPKG_HAL_POWERPC_RATTLER
+
+    implements    CYGHWR_IO_FLASH_DEVICE
+
+    compile       rattler_flash.c
+
+    # Arguably this should do in the generic package
+    # but then there is a logic loop so you can never enable it.
+    cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED {
+        display   "Generic AMD flash driver required"
+    }
+
+    implements    CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
+    requires      CYGHWR_DEVS_FLASH_AMD_AM29LV320D
+    requires      CYGHWR_DEVS_FLASH_AMD_AM29LV640
+
+}
+
Index: devs/flash/powerpc/rattler/current/src/rattler_flash.c
===================================================================
RCS file: devs/flash/powerpc/rattler/current/src/rattler_flash.c
diff -N devs/flash/powerpc/rattler/current/src/rattler_flash.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/rattler/current/src/rattler_flash.c	19 Aug 2003 16:38:12 -0000
@@ -0,0 +1,74 @@
+//==========================================================================
+//
+//      rattler_flash.c
+//
+//      Flash programming support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2003-08-19
+// Purpose:      
+// Description:  
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//--------------------------------------------------------------------------
+// Device properties
+
+#define CYGNUM_FLASH_INTERLEAVE	(1)
+#define CYGNUM_FLASH_SERIES	(1)
+#define CYGNUM_FLASH_WIDTH      (16)
+#define CYGNUM_FLASH_BASE 	(0xFE000000)
+#define CYGNUM_FLASH_16AS8      (0)
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+#define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT  // This feature fails :-(
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_am29xxxxx.inl"
+
+// ------------------------------------------------------------------------
+// EOF rattler_flash.c
Index: devs/flash/powerpc/viper/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/powerpc/viper/current/ChangeLog,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ChangeLog
--- devs/flash/powerpc/viper/current/ChangeLog	24 Jun 2002 13:10:24 -0000	1.7
+++ devs/flash/powerpc/viper/current/ChangeLog	19 Aug 2003 16:40:27 -0000
@@ -1,5 +1,12 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/viper_flash.c: Support new board layout which has 16bit
+	wide FLASH devices.
+	
+	* cdl/flash_viper.cdl: Add new 8MB device AM29LV640.
+
 2002-06-24  Gary Thomas  <gary@chez-thomas.org>
 
 	* cdl/flash_viper.cdl: Old devices use AM29LV800 chip.
 
 2002-06-20  Gary Thomas  <gary@chez-thomas.org>
Index: devs/flash/powerpc/viper/current/cdl/flash_viper.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/powerpc/viper/current/cdl/flash_viper.cdl,v
retrieving revision 1.6
diff -u -5 -p -r1.6 flash_viper.cdl
--- devs/flash/powerpc/viper/current/cdl/flash_viper.cdl	24 Jun 2002 13:10:27 -0000	1.6
+++ devs/flash/powerpc/viper/current/cdl/flash_viper.cdl	19 Aug 2003 16:18:02 -0000
@@ -7,10 +7,11 @@
 # ====================================================================
 #####ECOSGPLCOPYRIGHTBEGIN####
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
 ## Software Foundation; either version 2 or (at your option) any later version.
 ##
@@ -66,9 +67,10 @@ cdl_package CYGPKG_DEVS_FLASH_VIPER {
         display   "Generic AMD flash driver required"
     }
 
     implements    CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
     requires      CYGHWR_DEVS_FLASH_AMD_AM29LV320D
+    requires      CYGHWR_DEVS_FLASH_AMD_AM29LV640
     requires      CYGHWR_DEVS_FLASH_AMD_AM29LV800
 
 }
 
Index: devs/flash/powerpc/viper/current/src/viper_flash.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/powerpc/viper/current/src/viper_flash.c,v
retrieving revision 1.5
diff -u -5 -p -r1.5 viper_flash.c
--- devs/flash/powerpc/viper/current/src/viper_flash.c	20 Jun 2002 23:08:16 -0000	1.5
+++ devs/flash/powerpc/viper/current/src/viper_flash.c	19 Aug 2003 16:18:30 -0000
@@ -7,10 +7,11 @@
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -53,17 +54,20 @@
 #include <cyg/infra/cyg_type.h>
 
 //--------------------------------------------------------------------------
 // Device properties
 
+#ifdef CYGHWR_HAL_POWERPC_VIPER_I  // Old board layout
+#define CYGNUM_FLASH_WIDTH      (8)
+#define CYGNUM_FLASH_16AS8      (1)
+#else                              // New board layout
+#define CYGNUM_FLASH_WIDTH      (16)
+#define CYGNUM_FLASH_16AS8      (0)
+#endif
 #define CYGNUM_FLASH_INTERLEAVE	(1)
 #define CYGNUM_FLASH_SERIES	(1)
-#define CYGNUM_FLASH_WIDTH      (8)
 #define CYGNUM_FLASH_BASE 	(0xFE000000)
-#define CYGNUM_FLASH_16AS8      (1)
-
-//static cyg_uint32 plf_flash_base;
 
 //--------------------------------------------------------------------------
 // Platform specific extras
 #define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT  // This feature fails :-(
 
Index: hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl,v
retrieving revision 1.7
diff -u -5 -p -r1.7 hal_powerpc_adder.cdl
--- hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl	24 Jul 2003 20:24:06 -0000	1.7
+++ hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl	19 Aug 2003 14:52:04 -0000
@@ -94,11 +94,11 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER {
             description "
                 Select this model for an Adder with the PPC850 processor."
         }
 
         cdl_option  CYGHWR_HAL_POWERPC_ADDER_II {
-            display       "Adder-I with 852T"
+            display       "Adder-II with 852T"
             requires      !CYGHWR_HAL_POWERPC_ADDER_I
             requires      { CYGHWR_HAL_POWERPC_MPC8XX == "852T" }
             default_value 0
             implements    CYGNUM_HAL_QUICC_SMC1
             implements    CYGNUM_HAL_QUICC_SCC3
Index: hal/powerpc/arch/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/ChangeLog,v
retrieving revision 1.50
diff -u -5 -p -r1.50 ChangeLog
--- hal/powerpc/arch/current/ChangeLog	6 Aug 2003 17:31:26 -0000	1.50
+++ hal/powerpc/arch/current/ChangeLog	19 Aug 2003 16:21:27 -0000
@@ -1,5 +1,11 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/hal_intr.c (hal_IRQ_init): Precalculate clock tick per
+	microsecond (us) ratio to reduce overheads in delay.  Without
+	this, delays of small numbers of microseconds were inaccurate.
+
 2003-08-06  Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
 
 	* src/vectors.S (cyg_hal_default_interrupt_vsr): Removed ifdef on
 	CYGFUN_HAL_COMMON_KERNEL_SUPPORT around call to	interrupt_end().
 
Index: hal/powerpc/arch/current/src/hal_intr.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/src/hal_intr.c,v
retrieving revision 1.11
diff -u -5 -p -r1.11 hal_intr.c
--- hal/powerpc/arch/current/src/hal_intr.c	23 May 2002 23:04:14 -0000	1.11
+++ hal/powerpc/arch/current/src/hal_intr.c	19 Aug 2003 16:21:29 -0000
@@ -7,10 +7,11 @@
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -53,19 +54,24 @@
 
 #include <pkgconf/hal.h>
 
 #include <cyg/hal/hal_intr.h>
 
+static unsigned long ticks_per_us;
+
 externC void
 hal_IRQ_init(void)
 {
     // No architecture general initialization, but the variant may have
     // provided some.
     hal_variant_IRQ_init();
 
     // Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
     HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
+
+    // Pre-calculate this factor to avoid the extra calculations on each delay
+    ticks_per_us = ((long long)1 * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
 }
 
 // Delay for some number of useconds.
 externC void 
 hal_delay_us(int us)
@@ -74,11 +80,15 @@ hal_delay_us(int us)
     long ticks;
     int diff;
 
     // Note: the system constant CYGNUM_HAL_RTC_PERIOD corresponds to 10,000us
     // Scale the desired number of microseconds to be a number of decrementer ticks
-    ticks = ((long long)us * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
+    if (ticks_per_us > 0) {
+        ticks = us * ticks_per_us;
+    } else {
+        ticks = ((long long)us * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
+    }
     asm volatile("mfdec  %0;" : "=r"(old_dec) : );
     while (ticks > 0) {
         do {
             asm volatile("mfdec  %0;" : "=r"(new_dec) : );        
         } while (old_dec == new_dec);
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.31
diff -u -5 -p -r1.31 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog	15 Jul 2003 00:58:02 -0000	1.31
+++ hal/powerpc/mpc8xx/current/ChangeLog	19 Aug 2003 16:41:51 -0000
@@ -1,5 +1,11 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/var_misc.c: 
+	* include/var_cache.h: 
+	* cdl/hal_powerpc_mpc8xx.cdl: New variant 866T.
+
 2003-07-14  Gary Thomas  <gary@mlbassoc.com>
 
 	* include/var_cache.h: Data cache flush on 850 fails when using 
 	cache SPR commands, so use brute force.  This fixes some problems
 	with network based debugging (RedBoot got lost because of cache
Index: hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl,v
retrieving revision 1.9
diff -u -5 -p -r1.9 hal_powerpc_mpc8xx.cdl
--- hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl	23 Mar 2003 16:22:14 -0000	1.9
+++ hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl	19 Aug 2003 14:52:04 -0000
@@ -103,11 +103,11 @@ cdl_package CYGPKG_HAL_POWERPC_MPC8xx {
     }
 
     cdl_component CYGHWR_HAL_POWERPC_MPC8XX {
         display       "PowerPC 8xx microprocessor family"
         flavor        data
-	legal_values  { "823" "850" "852T" "855T" "860" "860T" "862T" "862P" }
+	legal_values  { "823" "850" "852T" "855T" "860" "860T" "862T" "862P" "866T" }
         default_value "860"
         implements    CYGINT_HAL_POWERPC_VARIANT
         description "
             The PowerPC 8xx microprocessor family. These are embedded parts 
             that in addition to the PowerPC processor core have built in peripherals
Index: hal/powerpc/mpc8xx/current/include/var_cache.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_cache.h,v
retrieving revision 1.6
diff -u -5 -p -r1.6 var_cache.h
--- hal/powerpc/mpc8xx/current/include/var_cache.h	15 Jul 2003 00:58:02 -0000	1.6
+++ hal/powerpc/mpc8xx/current/include/var_cache.h	19 Aug 2003 14:52:04 -0000
@@ -81,10 +81,11 @@
 #endif // defined(CYGHWR_HAL_POWERPC_MPC862P)
 
 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
+    defined(CYGHWR_HAL_POWERPC_MPC8XX_866T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
 // Data cache
 #define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
 #define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
Index: hal/powerpc/mpc8xx/current/src/var_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/src/var_misc.c,v
retrieving revision 1.15
diff -u -5 -p -r1.15 var_misc.c
--- hal/powerpc/mpc8xx/current/src/var_misc.c	16 Apr 2003 16:04:23 -0000	1.15
+++ hal/powerpc/mpc8xx/current/src/var_misc.c	19 Aug 2003 14:52:04 -0000
@@ -128,10 +128,11 @@ hal_variant_idle_thread_action( cyg_uint
 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
+    defined(CYGHWR_HAL_POWERPC_MPC8XX_866T) || \
     defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
 #define NUM_TLBS 32
 #elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
 #define NUM_TLBS 8
 #else
Index: hal/powerpc/mpc8xxx/current/ChangeLog
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/ChangeLog
diff -N hal/powerpc/mpc8xxx/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/ChangeLog	19 Aug 2003 16:51:10 -0000
@@ -0,0 +1,51 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/variant.S: 
+	* src/var_misc.c: 
+	* src/var_intr.c: 
+	* src/quicc2_diag.c: 
+	* src/cpm.c: 
+	* include/variant.inc:
+	* include/var_regs.h: 
+	* include/var_intr.h:
+	* include/var_cache.h: 
+	* include/mpc8xxx.h: 
+	* cdl/hal_powerpc_mpc8xxx.cdl: New file(s) - variant support for
+	Motorola MPC8xxx (Power-QUICC2) based systems.  Roughly based on
+	previously contributed hal/powerpc/mpc8260 package.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl
diff -N hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl	19 Aug 2003 16:44:08 -0000
@@ -0,0 +1,177 @@
+# ====================================================================
+#
+#      hal_powerpc_mpc8xxx.cdl
+#
+#      PowerPC/MPC8xxx variant architectural HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002, 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      pfine
+# Contributors:   jskov, gthomas
+# Date:           2001-12-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_POWERPC_MPC8XXX {
+    display       "PowerPC MPC8xxx variant HAL"
+    parent        CYGPKG_HAL_POWERPC
+    hardware
+    include_dir   cyg/hal
+    define_header hal_powerpc_mpc8xxx.h
+    description   "
+           The PowerPC MPC8xxx variant HAL package provides generic support
+           for this processor variant. It is also necessary to
+           select a specific target platform HAL package."
+
+    # Note: This should be sub-variant specific to reduce memory use.
+    define_proc {
+        puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)"
+        puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)"
+    }
+
+    implements    CYGINT_HAL_POWERPC_VARIANT
+
+    cdl_option CYGHWR_HAL_POWERPC_FPU {
+        display    "Variant FPU support"
+        calculated 0
+    }
+
+    cdl_option CYGPKG_HAL_POWERPC_MSBFIRST {
+        display    "CPU Variant big-endian"
+        calculated 1
+    }
+
+    define_proc {
+        puts $::cdl_header "#include <pkgconf/hal_powerpc.h>"
+    }
+
+    cdl_interface CYGNUM_HAL_MPC8XXX_SMC1 {
+        display    "SMC1 is available for serial I/O"
+        description "
+          This interface indicates that SMC1 can be outfitted as
+          a serial device."
+    }
+
+    cdl_interface CYGNUM_HAL_MPC8XXX_SMC2 {
+        display    "SMC2 is available for serial I/O"
+        description "
+          This interface indicates that SMC2 can be outfitted as
+          a serial device."
+    }
+
+    cdl_interface CYGNUM_HAL_MPC8XXX_SCC1 {
+        display    "SCC1 is available for serial I/O"
+        description "
+          Port SCC1 is available for serial I/O"
+    }
+
+    cdl_interface CYGNUM_HAL_MPC8XXX_SCC2 {
+        display    "SCC2 is available for serial I/O"
+        description "
+          Port SCC2 is available for serial I/O"
+    }
+
+    cdl_interface CYGNUM_HAL_MPC8XXX_SCC3 {
+        display    "SCC3 is available for serial I/O"
+        description "
+          Port SCC3 is available for serial I/O"
+    }
+
+    cdl_interface CYGNUM_HAL_MPC8XXX_SCC4 {
+        display    "SCC4 is available for serial I/O"
+        description "
+          Port SCC4 is available for serial I/O"
+    }
+
+   cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Baud rate for the HAL diagnostic port"
+        flavor        data
+        legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+                      4800 7200 9600 14400 19200 38400 57600 115200 230400
+        }
+        default_value 38400
+        description   "
+            This option specifies the default baud rate (speed) for the 
+            HAL diagnostic port."
+   }
+
+   cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+       display      "Number of communication channels on the board"
+       flavor       data
+       calculated   CYGNUM_HAL_MPC8XXX_SMC1+CYGNUM_HAL_MPC8XXX_SMC2+CYGNUM_HAL_MPC8XXX_SCC1+CYGNUM_HAL_MPC8XXX_SCC2+CYGNUM_HAL_MPC8XXX_SCC3+CYGNUM_HAL_MPC8XXX_SCC4
+   }
+
+   cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+       display          "Debug serial port"
+       active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+       flavor data
+       legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+       default_value    0
+       description      "
+           The MPC8xxx variants can have many serial ports.  This option
+           chooses which port will be used to connect to a host running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+           This option chooses which of the serial ports 
+           will be used for diagnostic output."
+    }
+
+    # This option is only used when USE_ROM_MONITOR is enabled - but
+    # it cannot be a sub-option to that option, since the code uses the
+    # definition in a preprocessor comparison.
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
+        display          "Debug serial port used by ROM monitor"
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+           This option chooses which of the serial ports 
+           will be used for GDB debugging."
+    }
+
+    compile       var_intr.c var_misc.c variant.S quicc2_diag.c cpm.c
+}
Index: hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
diff -N hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/include/mpc8xxx.h	19 Aug 2003 16:44:45 -0000
@@ -0,0 +1,1243 @@
+#ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
+#define CYGONCE_HAL_PPC_QUICC2_MPC8260_H
+
+//==========================================================================
+//
+//      mpc8260.h
+//
+//      PowerPC QUICC2 register definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Red Hat
+// Contributors: hmt, gthomas
+// Date:         1999-06-08
+// Purpose:      PowerPC QUICC2 definitions
+// Description:  PowerPC QUICC2 definitions
+// Usage:        THIS IS NOT AN EXTERNAL API
+//               This file is in the include dir to share it between
+//               QUICCII serial code and MPC8260 initialization code.
+//               #include <cyg/hal/mpc8260.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_regs.h>           // For IMM base
+
+#define DPRAM_SMC1_OFFSET 0x2000
+#define DPRAM_SMC2_OFFSET 0x2100
+#define DPRAM_BD_OFFSET   0x2200
+
+/*--------------------------*/
+/* Buffer Descriptor Format */
+/*--------------------------*/
+
+typedef struct BufferDescriptor 
+
+{
+   CYG_WORD16  bd_cstatus;     /* control and status */
+   CYG_WORD16  bd_length;      /* transfer length */
+   volatile CYG_BYTE   *bd_addr;        /* buffer address */
+
+} BD;
+
+
+/*-------------------------------*/
+/* Buffer Descriptor Ring format */
+/*-------------------------------*/
+
+typedef struct BufferDescRings 
+
+{
+    BD RxBD;    /* Rx BD ring */
+    BD TxBD;    /* Tx BD ring */
+
+} BDRINGS;
+
+#define _Packed 
+#define _PackedType __attribute__((packed))
+
+/******************************************************************************
+*
+*  PARAMETER RAM (PRAM) FOR EACH PERIPHERAL
+*  
+*  Each subsection contains protocol-specific PRAM for each peripheral,
+*  followed by the PRAM common to all protocols for that peripheral.  These 
+*  structs are used as needed in the main MPC8260 memory map structure.  Note 
+*  that different modes of operation will require the use of different PRAM 
+*  structs, and that certain structs may overlay and conflict with the use of 
+*  other PRAM areas.  Consult the MPC8260 User Manual for details as to what
+*  is unavailable when certain protocols are run on certain peripherals.
+*
+******************************************************************************/
+                          
+
+
+/*---------------------------------------------------------------------------*/
+/*                   SERIAL COMMUNICATION CONTROLLER (SCC)                 */
+/*---------------------------------------------------------------------------*/
+
+/*----------*/
+/* SCC HDLC */
+/*----------*/
+
+typedef _Packed struct 
+{
+    CYG_BYTE    reserved1[4]; /* Reserved area */
+    CYG_WORD    c_mask;       /* CRC constant */
+    CYG_WORD    c_pres;       /* CRC preset */
+    CYG_WORD16   disfc;        /* discarded frame counter */
+    CYG_WORD16   crcec;        /* CRC error counter */
+    CYG_WORD16   abtsc;        /* abort sequence counter */
+    CYG_WORD16   nmarc;        /* nonmatching address rx cnt */
+    CYG_WORD16   retrc;        /* frame transmission counter. */
+                           /* For FCC this area is reserved.*/
+    CYG_WORD16   mflr;         /* maximum frame length reg */
+    CYG_WORD16   max_cnt;      /* maximum length counter */
+    CYG_WORD16   rfthr;        /* received frames threshold */
+    CYG_WORD16   rfcnt;        /* received frames count */
+    CYG_WORD16   hmask;        /* user defined frm addr mask */
+    CYG_WORD16   haddr1;       /* user defined frm address 1 */
+    CYG_WORD16   haddr2;       /* user defined frm address 2 */
+    CYG_WORD16   haddr3;       /* user defined frm address 3 */
+    CYG_WORD16   haddr4;       /* user defined frm address 4 */
+    CYG_WORD16   tmp;          /* temp */
+    CYG_WORD16   tmp_mb;       /* temp */
+} _PackedType t_HdlcScc_Pram;
+
+ 
+/*--------------*/
+/* SCC Ethernet */
+/*--------------*/
+
+typedef _Packed struct 
+{
+    CYG_WORD    c_pres;      /* CRC preset */
+    CYG_WORD    c_mask;      /* CRC constant mask*/
+    CYG_WORD    crcec;       /* CRC error counter */
+    CYG_WORD    alec;        /* alignment error counter */
+    CYG_WORD    disfc;       /* discarded frame counter */
+    CYG_WORD16   pads;        /* Short frame pad character. */
+    CYG_WORD16   ret_lim;     /* Retry limit threshold. */
+    CYG_WORD16   ret_cnt;     /* Retry limit counter. */
+    CYG_WORD16   mflr;        /* maximum frame length reg */
+    CYG_WORD16   minflr;      /* minimum frame length reg */
+    CYG_WORD16   maxd1;       /* max DMA1 length register. */
+    CYG_WORD16   maxd2;       /* max DMA2 length register. */
+    CYG_WORD16   maxd;        /* Rx max DMA. */
+    CYG_WORD16   dma_cnt;     /* Rx DMA counter. */
+    CYG_WORD16   max_b;       /* max buffer descriptor byte count. */
+    CYG_WORD16   gaddr1;      /* group address filter */
+    CYG_WORD16   gaddr2;      /* group address filter */
+    CYG_WORD16   gaddr3;      /* group address filter */
+    CYG_WORD16   gaddr4;      /* group address filter */
+    CYG_WORD    tbuf0_data0; /* Saved area 0, current frame. */
+    CYG_WORD    tbuf0_data1; /* Saved area 1, current frame. */
+    CYG_WORD    tbuf0_rba0;
+    CYG_WORD    tbuf0_crc;
+    CYG_WORD16   tbuf0_bcnt;
+    CYG_WORD16   paddr1_h;    /* physical address (MSB) */
+    CYG_WORD16   paddr1_m;    /* physical address */
+    CYG_WORD16   paddr1_l;    /* physical address (LSB) */
+    CYG_WORD16   p_per;       /* persistence */
+    CYG_WORD16   rfbd_ptr;    /* Rx first BD pointer. */
+    CYG_WORD16   tfbd_ptr;    /* Tx first BD pointer. */
+    CYG_WORD16   tlbd_ptr;    /* Tx last BD pointer. */
+    CYG_WORD    tbuf1_data0; /* Saved area 0, next frame. */
+    CYG_WORD    tbuf1_data1; /* Saved area 1, next frame. */
+    CYG_WORD    tbuf1_rba0;
+    CYG_WORD    tbuf1_crc;
+    CYG_WORD16   tbuf1_bcnt;
+    CYG_WORD16   tx_len;      /* tx frame length counter */
+    CYG_WORD16   iaddr1;      /* individual address filter. */
+    CYG_WORD16   iaddr2;      /* individual address filter.  */
+    CYG_WORD16   iaddr3;      /* individual address filter. */
+    CYG_WORD16   iaddr4;      /* individual address filter.  */
+    CYG_WORD16   boff_cnt;    /* back-off counter */
+    CYG_WORD16   taddr_h;     /* temp address (MSB) */
+    CYG_WORD16   taddr_m;     /* temp address */
+    CYG_WORD16   taddr_l;     /* temp address (LSB) */
+} _PackedType t_EnetScc_Pram;
+
+/*----------*/
+/* SCC UART */
+/*----------*/
+
+typedef _Packed struct 
+{
+    CYG_BYTE       reserved1[8];   /* Reserved area */
+    CYG_WORD16      max_idl;        /* maximum idle characters */
+    CYG_WORD16      idlc;           /* rx idle counter (internal) */
+    CYG_WORD16      brkcr;          /* break count register */
+    CYG_WORD16      parec;          /* Rx parity error counter */
+    CYG_WORD16      frmec;          /* Rx framing error counter */
+    CYG_WORD16      nosec;          /* Rx noise counter */
+    CYG_WORD16      brkec;          /* Rx break character counter */
+    CYG_WORD16      brkln;          /* Receive break length */
+    CYG_WORD16      uaddr1;         /* address character 1 */
+    CYG_WORD16      uaddr2;         /* address character 2 */
+    CYG_WORD16      rtemp;          /* temp storage */
+    CYG_WORD16      toseq;          /* Tx out of sequence char */
+    CYG_WORD16      cc[8];          /* Rx control characters */
+    CYG_WORD16      rccm;           /* Rx control char mask */
+    CYG_WORD16      rccr;           /* Rx control char register */
+    CYG_WORD16      rlbc;           /* Receive last break char */
+} _PackedType t_UartScc_Pram;
+
+
+/*-----------------*/
+/* SCC Transparent */
+/*-----------------*/
+
+typedef _Packed struct  
+{
+    CYG_WORD    c_mask;     /* CRC constant */
+    CYG_WORD    c_pres;     /* CRC preset */
+} _PackedType t_TransScc_Pram;
+
+
+/*------------*/
+/* SCC Bisync */
+/*------------*/
+
+typedef _Packed struct  
+{
+   CYG_BYTE    reserved1[4];     /* Reserved area */
+   CYG_WORD crcc;       /* CRC Constant Temp Value */
+   CYG_WORD16   prcrc;         /* Preset Receiver CRC-16/LRC */
+   CYG_WORD16   ptcrc;         /* Preset Transmitter CRC-16/LRC */
+   CYG_WORD16   parec;         /* Receive Parity Error Counter */
+   CYG_WORD16   bsync;         /* BISYNC SYNC Character */
+   CYG_WORD16   bdle;       /* BISYNC DLE Character */
+   CYG_WORD16   cc[8];         /* Rx control characters */
+   CYG_WORD16   rccm;       /* Receive Control Character Mask */
+} _PackedType t_BisyncScc_Pram;
+
+
+/*-----------------*/
+/* SCC Common PRAM */
+/*-----------------*/
+
+typedef _Packed struct 
+{
+    CYG_WORD16   rbase;      /* RX BD base address */
+    CYG_WORD16   tbase;      /* TX BD base address */
+    CYG_BYTE    rfcr;       /* Rx function code */
+    CYG_BYTE    tfcr;       /* Tx function code */
+    CYG_WORD16   mrblr;      /* Rx buffer length */
+    CYG_WORD    rstate;     /* Rx internal state */
+    CYG_WORD    rptr;       /* Rx internal data pointer */
+    CYG_WORD16   rbptr;      /* rb BD Pointer */
+    CYG_WORD16   rcount;     /* Rx internal byte count */
+    CYG_WORD    rtemp;      /* Rx temp */
+    CYG_WORD    tstate;     /* Tx internal state */
+    CYG_WORD    tptr;       /* Tx internal data pointer */
+    CYG_WORD16   tbptr;      /* Tx BD pointer */
+    CYG_WORD16   tcount;     /* Tx byte count */
+    CYG_WORD    ttemp;      /* Tx temp */
+    CYG_WORD    rcrc;       /* temp receive CRC */
+    CYG_WORD    tcrc;       /* temp transmit CRC */
+    union 
+    {
+       t_HdlcScc_Pram    h;
+       t_EnetScc_Pram    e;
+       t_UartScc_Pram    u;
+       t_TransScc_Pram   t;
+       t_BisyncScc_Pram  b;
+    } SpecificProtocol;
+    volatile CYG_BYTE COMPLETE_SIZE_OF_DPRAM_PAGE[0x5c];
+} _PackedType t_Scc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                     FAST COMMUNICATION CONTROLLER (FCC)               */
+/*---------------------------------------------------------------------------*/
+
+/*----------*/
+/* FCC HDLC */
+/*----------*/
+
+typedef _Packed struct 
+{
+    CYG_BYTE    reserved1[8]; /* Reserved area */
+    CYG_WORD    c_mask;       /* CRC constant */
+    CYG_WORD    c_pres;       /* CRC preset */
+    CYG_WORD16   disfc;        /* discarded frame counter */
+    CYG_WORD16   crcec;        /* CRC error counter */
+    CYG_WORD16   abtsc;        /* abort sequence counter */
+    CYG_WORD16   nmarc;        /* nonmatching address rx cnt */
+    CYG_WORD    max_cnt;      /* maximum length counter */
+    CYG_WORD16   mflr;         /* maximum frame length reg */
+    CYG_WORD16   rfthr;        /* received frames threshold */
+    CYG_WORD16   rfcnt;        /* received frames count */
+    CYG_WORD16   hmask;        /* user defined frm addr mask */
+    CYG_WORD16   haddr1;       /* user defined frm address 1 */
+    CYG_WORD16   haddr2;       /* user defined frm address 2 */
+    CYG_WORD16   haddr3;       /* user defined frm address 3 */
+    CYG_WORD16   haddr4;       /* user defined frm address 4 */
+    CYG_WORD16   tmp;          /* temp */
+    CYG_WORD16   tmp_mb;       /* temp */
+} _PackedType t_HdlcFcc_Pram;
+
+
+/*--------------*/
+/* FCC Ethernet */
+/*--------------*/
+
+typedef _Packed struct 
+{
+    CYG_WORD    stat_bus;       /* Internal use buffer. */
+    CYG_WORD    cam_ptr;        /* CAM address. */
+    CYG_WORD    c_mask;         /* CRC constant mask*/
+    CYG_WORD    c_pres;      /* CRC preset */
+    CYG_WORD    crcec;          /* CRC error counter */
+    CYG_WORD    alec;           /* alignment error counter */
+    CYG_WORD    disfc;          /* discarded frame counter */
+    CYG_WORD16   ret_lim;        /* Retry limit threshold. */
+    CYG_WORD16   ret_cnt;        /* Retry limit counter. */
+    CYG_WORD16   p_per;          /* persistence */
+    CYG_WORD16   boff_cnt;       /* back-off counter */
+    CYG_WORD    gaddr_h;        /* group address filter, high */
+    CYG_WORD    gaddr_l;        /* group address filter, low */
+    CYG_WORD16   tfcstat;        /* out of sequece Tx BD staus. */
+    CYG_WORD16   tfclen;         /* out of sequece Tx BD length. */
+    CYG_WORD    tfcptr;         /* out of sequece Tx BD data pointer. */
+    CYG_WORD16   mflr;           /* maximum frame length reg */
+    CYG_WORD16   paddr1_h;       /* physical address (MSB) */
+    CYG_WORD16   paddr1_m;       /* physical address */
+    CYG_WORD16   paddr1_l;       /* physical address (LSB) */
+    CYG_WORD16   ibd_cnt;        /* internal BD counter. */
+    CYG_WORD16   ibd_start;      /* internal BD start pointer. */
+    CYG_WORD16   ibd_end;        /* internal BD end pointer. */
+    CYG_WORD16   tx_len;         /* tx frame length counter */
+    CYG_BYTE    ibd_base[0x20]; /* internal micro code usage. */
+    CYG_WORD    iaddr_h;        /* individual address filter, high */
+    CYG_WORD    iaddr_l;        /* individual address filter, low */
+    CYG_WORD16   minflr;         /* minimum frame length reg */
+    CYG_WORD16   taddr_h;        /* temp address (MSB) */
+    CYG_WORD16   taddr_m;        /* temp address */
+    CYG_WORD16   taddr_l;        /* temp address (LSB) */
+    CYG_WORD16   pad_ptr;        /* pad_ptr. */
+    CYG_WORD16   cf_type;        /* flow control frame type coding. */
+    CYG_WORD16   cf_range;       /* flow control frame range. */
+    CYG_WORD16   max_b;          /* max buffer descriptor byte count. */
+    CYG_WORD16   maxd1;          /* max DMA1 length register. */
+    CYG_WORD16   maxd2;          /* max DMA2 length register. */
+    CYG_WORD16   maxd;           /* Rx max DMA. */
+    CYG_WORD16   dma_cnt;        /* Rx DMA counter. */
+    
+    /* counter: */
+    CYG_WORD    octc;           /* received octets counter. */
+    CYG_WORD    colc;           /* estimated number of collisions */
+    CYG_WORD    broc;           /* received good packets of broadcast address */
+    CYG_WORD    mulc;           /* received good packets of multicast address */
+    CYG_WORD    uspc;           /* received packets shorter then 64 octets. */
+    CYG_WORD    frgc;           /* as uspc + bad packets */
+    CYG_WORD    ospc;           /* received packets longer then 1518 octets. */
+    CYG_WORD    jbrc;           /* as ospc + bad packets  */
+    CYG_WORD    p64c;           /* received packets of 64 octets.. */
+    CYG_WORD    p65c;           /* received packets of 65-128 octets.. */
+    CYG_WORD    p128c;          /* received packets of 128-255 octets.. */
+    CYG_WORD    p256c;          /* received packets of 256-511 octets.. */
+    CYG_WORD    p512c;          /* received packets of 512-1023 octets.. */
+    CYG_WORD    p1024c;         /* received packets of 1024-1518 octets.. */
+    CYG_WORD    cam_buf;        /* cam respond internal buffer. */
+    CYG_WORD16   rfthr;          /* received frames threshold */
+    CYG_WORD16   rfcnt;          /* received frames count */
+} _PackedType t_EnetFcc_Pram;
+
+
+/*-----------------*/
+/* FCC Common PRAM */
+/*-----------------*/
+
+typedef _Packed struct 
+{
+    CYG_WORD16   riptr;      /* Rx internal temporary data pointer. */
+    CYG_WORD16   tiptr;      /* Tx internal temporary data pointer. */
+    CYG_WORD16   reserved0;  /* Reserved */
+    CYG_WORD16   mrblr;      /* Rx buffer length */
+    CYG_WORD    rstate;     /* Rx internal state */
+    CYG_WORD    rbase;      /* RX BD base address */
+    CYG_WORD16   rbdstat;    /* Rx BD status and control */
+    CYG_WORD16   rbdlen;     /* Rx BD data length */
+    CYG_WORD    rdptr;      /* rx BD data pointer */
+    CYG_WORD    tstate;     /* Tx internal state */
+    CYG_WORD    tbase;      /* TX BD base address */
+    CYG_WORD16   tbdstat;    /* Tx BD status and control */
+    CYG_WORD16   tbdlen;     /* Tx BD data length */
+    CYG_WORD    tdptr;      /* Tx  data pointer */
+    CYG_WORD    rbptr;      /* rx BD pointer */
+    CYG_WORD    tbptr;      /* Tx BD pointer */
+    CYG_WORD    rcrc;       /* Temp receive CRC */
+    CYG_WORD    reserved_1[0x1];
+    CYG_WORD    tcrc;       /* Temp transmit CRC */
+    union                /* Protocol-Specific parameter ram */
+   {
+        t_HdlcFcc_Pram    h;
+       t_EnetFcc_Pram    e;
+    } SpecificProtocol;      
+} _PackedType t_Fcc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                 MULTICHANNEL COMMUNICATION CONTROLLER (MCC)              */
+/*---------------------------------------------------------------------------*/
+
+/******************************************************************************
+* Note that each MCC uses multiple logical channels.  We first define the     *
+* PRAM for a logical channel (which can be used in either HDLC or Transparent *
+* mode;  wherever there are differences, it is specified), followed by the    *
+* PRAM for an MCC itself.                                                     *
+******************************************************************************/
+
+/*---------------------*/
+/* MCC Logical Channel */
+/*---------------------*/
+
+typedef _Packed struct
+{
+    CYG_WORD    tstate;     /* Tx internal state. */ 
+    CYG_WORD    zistate;    /* Zero insertion machine state. */
+    CYG_WORD    zidata0;    /* Zero insertion high CYG_WORD16. */
+    CYG_WORD    zidata1;    /* Zero insertion low CYG_WORD16. */
+    CYG_WORD16   tbdflags;   /* Tx internal BD flags. */
+    CYG_WORD16   tbdcnt;     /* Tx internal byte count . */
+    CYG_WORD    tbdptr;     /* Tx internal data pointer. */
+    CYG_WORD16   intmask;    /* Interrupt mask flags. */
+    CYG_WORD16   chamr;      /* channel mode register. */
+    CYG_WORD    tcrc;       /* Transparent: reserved. */
+                         /* Hdlc: Temp receive CRC.*/
+    CYG_WORD    rstate;     /* Rx internal state. */ 
+    CYG_WORD    zdstate;    /* Zero deletion machine state. */
+    CYG_WORD    zddata0;    /* Zero deletion  high CYG_WORD16. */
+    CYG_WORD    zddata1;    /* Zero deletion  low CYG_WORD16. */
+    CYG_WORD16   rbdflags;   /* Rx internal BD flags. */
+    CYG_WORD16   rbdcnt;     /* Rx internal byte count . */
+    CYG_WORD    rbdptr;     /* Rx internal data pointer. */
+    CYG_WORD16   maxrlen;    /* Transparent: Max receive buffer length. */
+                         /* Hdlc: Max receive frame length. */
+    CYG_WORD16   sync_maxcnt;/* Transparent: Receive synchronization pattern*/
+                         /* Hdlc: Max length counter. */
+    CYG_WORD    rcrc;       /* Transparent: reserved. */
+                         /* Hdlc: Temp receive CRC.*/
+} _PackedType t_Mch_Pram;
+
+
+/*----------*/
+/* MCC PRAM */
+/*----------*/
+
+typedef _Packed struct
+{
+    CYG_WORD     mccbase;    /* A pointer to starting address of BD rings. */
+    CYG_WORD16   mccstate;   /* Controller state. */
+    CYG_WORD16   mrblr;      /* Maximum receive buffer length. */
+    CYG_WORD16   grfthr;     /* Global receive frame threshold. */
+    CYG_WORD16   grfcnt;     /* Global receive frame counter. */
+    CYG_WORD     rinttmp;    /* Temp location for receive interrupt table entry. */                            
+    CYG_WORD     data0;      /* Temporary location for holding data. */
+    CYG_WORD     data1;      /* Temporary location for holding data. */
+    CYG_WORD     tintbase;   /* Transmit interrupt table base address. */
+    CYG_WORD     tintptr;    /* Transmit interrupt table pointer. */ 
+    CYG_WORD     tinttmp;    /* Temp location for receive interrupt table entry. */
+    CYG_WORD16   sctpbase;   /* A pointer to the super channel transmit table*/
+    CYG_BYTE     res0[0x2];  /* Reserved area */
+    CYG_WORD     c_mask32;   /* CRC constant. */
+    CYG_WORD16   xtrabase;   /* A pointer to the beginning of extra parameters */                            
+    CYG_WORD16   c_mask16;   /* CRC constant. */
+    CYG_WORD     rinttmp0;   /* Temp location for receive interrupt table entry. */                            
+    CYG_WORD     rinttmp1;   /* Temp location for receive interrupt table entry. */
+    CYG_WORD     rinttmp2;   /* Temp location for receive interrupt table entry. */
+    CYG_WORD     rinttmp3;   /* Temp location for receive interrupt table entry. */
+    CYG_WORD     rintbase0;  /* Receive interrupt table base address. */
+    CYG_WORD     rintptr0;   /* Receive interrupt table pointer. */
+    CYG_WORD     rintbase1;  /* Receive interrupt table base address. */
+    CYG_WORD     rintptr1;   /* Receive interrupt table pointer. */
+    CYG_WORD     rintbase2;  /* Receive interrupt table base address. */
+    CYG_WORD     rintptr2;   /* Receive interrupt table pointer. */
+    CYG_WORD     rintbase3;  /* Receive interrupt table base address. */
+    CYG_WORD     rintptr3;   /* Receive interrupt table pointer. */
+    CYG_BYTE     pad[0xa0];
+} _PackedType t_Mcc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                              ATM PARAMETER RAM                            */
+/*---------------------------------------------------------------------------*/
+
+
+/*--------------------------------------*/
+/* Address Compression parameters table */
+/*--------------------------------------*/
+
+_Packed struct AddressCompressionPram 
+{
+    volatile CYG_WORD  VptBase;  /* VP-level addressing table base address */
+    volatile CYG_WORD  VctBase;  /* VC-level addressing table base address */
+    volatile CYG_WORD  Vpt1Base; /* VP1-level addressing table base address */  
+    volatile CYG_WORD  Vct1Base; /* VC1-level addressing table base address */
+    volatile CYG_WORD16 VpMask;    /* VP mask for address compression look-up */
+} _PackedType;
+
+
+/*-------------------------------*/
+/* External CAM parameters table */
+/*-------------------------------*/
+
+_Packed struct ExtCamPram 
+{
+    volatile CYG_WORD  ExtCamBase;    /* Base address of the external CAM */
+    volatile CYG_BYTE  reserved00[4];  /* Reserved */
+    volatile CYG_WORD  ExtCam1Base;   /* Base address of the external CAM1 */
+    volatile CYG_BYTE  reserved01[6];  /* Reserved */
+} _PackedType;
+
+
+/*---------------------------*/
+/* ATM mode parameters table */
+/*---------------------------*/
+
+typedef _Packed struct AtmPram 
+{
+    volatile CYG_BYTE  reserved0[64];    /* Reserved */
+    volatile CYG_WORD16 RxCellTmpBase;    /* Rx cell temporary base address */
+    volatile CYG_WORD16 TxCellTmpBase;    /* Tx cell temporary base address */
+    volatile CYG_WORD16 UdcTmpBase;       /* UDC temp base address (in UDC mode only) */
+    volatile CYG_WORD16 IntRctBase;       /* Internal RTC base address */
+    volatile CYG_WORD16 IntTctBase;       /* Internal TCT base address */
+    volatile CYG_WORD16 IntTcteBase;      /* Internal ACT base address */
+    volatile CYG_BYTE  reserved1[4];     /* reserved four bytes */
+    volatile CYG_WORD  ExtRctBase;       /* Extrnal RTC base address */
+    volatile CYG_WORD  ExtTctBase;       /* Extrnal TCT base address */
+    volatile CYG_WORD  ExtTcteBase;      /* Extrnal ACT base address */
+    volatile CYG_WORD16 UeadOffset;       /* The offset in half-wordunits of the UEAD
+                                 entry in the UDC extra header. Should be
+                                 even address. If little-endian format is
+                                 used, the UeadOffset is of the little-endian
+                                 format. */
+    volatile CYG_BYTE  reserved2[2];     /* Reserved */
+    volatile CYG_WORD16 PmtBase;      /* Performance monitoring table base address */
+    volatile CYG_WORD16 ApcParamBase;    /* APC Parameters table base address */
+    volatile CYG_WORD16 FbpParamBase;    /* Free buffer pool parameters base address */
+    volatile CYG_WORD16 IntQParamBase;   /* Interrupt queue parameters table base */
+    volatile CYG_BYTE  reserved3[2];
+    volatile CYG_WORD16 UniStatTableBase; /* UNI statistics table base */
+    volatile CYG_WORD  BdBaseExt;        /* BD ring base address extension */
+    union 
+    {
+       struct AddressCompressionPram   AddrCompression;
+       struct ExtCamPram               ExtCam;
+    } AddrMapping;            /* Address look-up mechanism */
+    volatile CYG_WORD16 VciFiltering;     /* VCI filtering enable bits. If bit i is set,
+                                 the cell with VCI=i will be sent to the
+                                 raw cell queue. The bits 0-2 and 5 should
+                                 be zero. */
+    volatile CYG_WORD16 Gmode;            /* Global mode */
+    volatile CYG_WORD16 CommInfo1;        /* The information field associated with the */
+    volatile CYG_WORD  CommInfo2;        /* last host command */
+    volatile CYG_BYTE  reserved4[4];     /* Reserved */
+    volatile CYG_WORD  CRC32Preset;      /* Preset for CRC32 */
+    volatile CYG_WORD  CRC32Mask;        /* Constant mask for CRC32 */
+    volatile CYG_WORD16 AAL1SnpTableBase; /* AAl1 SNP protection look-up table base */
+    volatile CYG_WORD16 reserved5;        /* Reserved */
+    volatile CYG_WORD  SrtsBase;         /* External SRTS logic base address. For AAL1
+                                 only. Should be 16 bytes aligned */
+    volatile CYG_WORD16 IdleBase;         /* Idle cell base address */
+    volatile CYG_WORD16 IdleSize;         /* Idle cell size: 52, 56, 60, 64 */
+    volatile CYG_WORD  EmptyCellPayload; /* Empty cell payload (little-indian) */
+    
+    /* ABR specific only */
+    volatile CYG_WORD  Trm; /* Upper bound on time between F-RM cells for active source */                                 
+    volatile CYG_WORD16 Nrm; /* Controls the maximum data cells sent for each F-RM cell. */                           
+    volatile CYG_WORD16 Mrm; /* Controls bandwidth between F-RM, B-RM and user data cell */
+    volatile CYG_WORD16 Tcr;              /* Tag cell rate */
+    volatile CYG_WORD16 AbrRxTcte;        /* ABR reserved area address (2-CYG_WORD16 aligned)*/
+    volatile CYG_BYTE  reserved7[76];    /* Reserved */
+} _PackedType t_Atm_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                     SERIAL MANAGEMENT CHANNEL  (SMC)                   */
+/*---------------------------------------------------------------------------*/
+
+typedef _Packed struct  
+{
+   CYG_WORD16   rbase;      /* Rx BD Base Address */
+   CYG_WORD16   tbase;      /* Tx BD Base Address */
+   CYG_BYTE    rfcr;    /* Rx function code */
+   CYG_BYTE    tfcr;    /* Tx function code */
+   CYG_WORD16   mrblr;      /* Rx buffer length */
+   CYG_WORD    rstate;     /* Rx internal state */
+   CYG_WORD    rptr;    /* Rx internal data pointer */
+   CYG_WORD16   rbptr;      /* rb BD Pointer */
+   CYG_WORD16   rcount;     /* Rx internal byte count */
+   CYG_WORD    rtemp;      /* Rx temp */
+   CYG_WORD    tstate;     /* Tx internal state */
+   CYG_WORD    tptr;    /* Tx internal data pointer */
+   CYG_WORD16   tbptr;      /* Tx BD pointer */
+   CYG_WORD16   tcount;     /* Tx byte count */
+   CYG_WORD    ttemp;       /* Tx temp */
+  
+   /* SMC UART-specific PRAM */
+   CYG_WORD16   max_idl; /* Maximum IDLE Characters */
+   CYG_WORD16   idlc;    /* Temporary IDLE Counter */
+   CYG_WORD16   brkln;      /* Last Rx Break Length */
+   CYG_WORD16   brkec;      /* Rx Break Condition Counter */
+   CYG_WORD16   brkcr;      /* Break Count Register (Tx) */
+   CYG_WORD16   r_mask;     /* Temporary bit mask */
+  
+} _PackedType t_Smc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                      IDMA PARAMETER RAM                             */
+/*---------------------------------------------------------------------------*/
+
+typedef _Packed struct  
+{
+    CYG_WORD16      ibase;       /* IDMA BD Base Address               */
+    CYG_WORD16      dcm;         /* DMA channel mode register          */
+    CYG_WORD16      ibdptr;      /* next bd ptr                        */
+    CYG_WORD16      DPR_buf;     /* ptr to internal 64 byte buffer     */
+    CYG_WORD16      BUF_inv;     /* The quantity of data in DPR_buf    */
+    CYG_WORD16      SS_max;      /* Steady State Max. transfer size    */
+    CYG_WORD16      DPR_in_ptr;  /* write ptr for the internal buffer  */
+    CYG_WORD16      sts;         /* Source Transfer Size               */
+    CYG_WORD16      DPR_out_ptr; /* read ptr for the internal buffer   */
+    CYG_WORD16      seob;        /* Source end of burst                */
+    CYG_WORD16      deob;        /* Destination end of burst           */
+    CYG_WORD16      dts;         /* Destination Transfer Size          */
+    CYG_WORD16      RetAdd;      /* return address when ERM==1         */
+    CYG_WORD16      Reserved;    /* reserved */
+    CYG_WORD       BD_cnt;      /* Internal byte count                */
+    CYG_WORD       S_ptr;       /* source internal data ptr           */
+    CYG_WORD       D_ptr;       /* destination internal data ptr      */
+    CYG_WORD       istate;      /* Internal state                     */
+
+} _PackedType t_Idma_Pram;
+
+
+
+/*-------------------------------------------------------------------*/
+/*         INTER-INTEGRATED CIRCUIT  (I2C)                        */
+/*-------------------------------------------------------------------*/
+
+typedef _Packed struct 
+{
+   CYG_WORD16   rbase;      /* RX BD base address */
+   CYG_WORD16   tbase;      /* TX BD base address */
+   CYG_BYTE    rfcr;    /* Rx function code */
+   CYG_BYTE    tfcr;    /* Tx function code */
+   CYG_WORD16   mrblr;      /* Rx buffer length */
+   CYG_WORD    rstate;     /* Rx internal state */
+   CYG_WORD    rptr;    /* Rx internal data pointer */
+   CYG_WORD16   rbptr;      /* rb BD Pointer */
+   CYG_WORD16   rcount;     /* Rx internal byte count */
+   CYG_WORD    rtemp;      /* Rx temp */
+   CYG_WORD    tstate;     /* Tx internal state */
+   CYG_WORD    tptr;    /* Tx internal data pointer */
+   CYG_WORD16   tbptr;      /* Tx BD pointer */
+   CYG_WORD16   tcount;     /* Tx byte count */
+   CYG_WORD    ttemp;      /* Tx temp */
+
+} _PackedType t_I2c_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                       SERIAL PERIPHERAL INTERFACE  (SPI)                  */
+/*---------------------------------------------------------------------------*/
+
+typedef _Packed struct  
+{
+   CYG_WORD16   rbase;      /* Rx BD Base Address */
+   CYG_WORD16   tbase;      /* Tx BD Base Address */
+   CYG_BYTE    rfcr;       /* Rx function code */
+   CYG_BYTE    tfcr;       /* Tx function code */
+   CYG_WORD16   mrblr;      /* Rx buffer length */
+   CYG_WORD    rstate;     /* Rx internal state */
+   CYG_WORD    rptr;       /* Rx internal data pointer */
+   CYG_WORD16   rbptr;      /* Rx BD Pointer */
+   CYG_WORD16   rcount;     /* Rx internal byte count */
+   CYG_WORD    rtemp;      /* Rx temp */
+   CYG_WORD    tstate;     /* Tx internal state */
+   CYG_WORD    tptr;       /* Tx internal data pointer */
+   CYG_WORD16   tbptr;      /* Tx BD pointer */
+   CYG_WORD16   tcount;     /* Tx byte count */
+   CYG_WORD    ttemp;      /* Tx temp */
+   CYG_BYTE    reserved[8];
+
+} _PackedType t_Spi_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/*                RISC TIMER PARAMETER RAM                             */
+/*---------------------------------------------------------------------------*/
+
+typedef _Packed struct  
+{
+ 
+   CYG_WORD16   tm_base;    /* RISC timer table base adr */
+   CYG_WORD16   tm_ptr;     /* RISC timer table pointer */
+   CYG_WORD16   r_tmr;      /* RISC timer mode register */
+   CYG_WORD16   r_tmv;      /* RISC timer valid register */
+   CYG_WORD tm_cmd;     /* RISC timer cmd register */
+   CYG_WORD tm_cnt;     /* RISC timer internal cnt */
+} _PackedType t_timer_pram;
+
+
+
+/*--------------------------------------------------------------------------*/
+/*                  ROM MICROCODE PARAMETER RAM AREA                        */
+/*--------------------------------------------------------------------------*/
+
+typedef _Packed struct  
+{
+   CYG_WORD16   rev_num;    /* Ucode Revision Number */
+   CYG_WORD16   d_ptr;      /* MISC Dump area pointer */
+} _PackedType t_ucode_pram;
+
+/*--------------------------------------------------------------------------*/
+/*                MAIN DEFINITION OF MPC8260 INTERNAL MEMORY MAP            */
+/*--------------------------------------------------------------------------*/
+
+typedef _Packed struct 
+{
+
+/* cpm_ram */
+    t_Mch_Pram    mch_pram[256]; /* MCC logical channels parameter ram */
+    volatile CYG_BYTE reserved0[0x4000];    /* Reserved area */
+    
+/* DPR_BASE+0x8000*/
+    union 
+    {
+    
+    /*for access to the PRAM structs for SCCs, FCCs, and MCCs */ 
+       struct serials 
+       {
+           t_Scc_Pram scc_pram[4];
+           t_Fcc_Pram fcc_pram[3];
+           t_Mcc_Pram mcc_pram[2];
+           volatile CYG_BYTE reserved1[0x700];
+       } serials;
+        
+    /* for access to ATM PRAM structs */
+       struct atm
+       {
+           volatile CYG_BYTE reserved2[0x400];
+           t_Atm_Pram atm_pram[2];
+           volatile CYG_BYTE reserved3[0xa00];
+       } atm;
+        
+    /* for access to the memory locations holding user-defined 
+       base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */     
+       struct standard
+       {
+            volatile CYG_BYTE scc1[0x100];
+            volatile CYG_BYTE scc2[0x100];
+            volatile CYG_BYTE scc3[0x100];
+            volatile CYG_BYTE scc4[0x100];
+            volatile CYG_BYTE fcc1[0x100];
+            volatile CYG_BYTE fcc2[0x100];
+            volatile CYG_BYTE fcc3[0x100];
+            volatile CYG_BYTE mcc1[0x80];
+            volatile CYG_BYTE reserved_0[0x7c];
+            volatile CYG_WORD16 smc1;  // Pointer to SMC1 DPRAM
+            volatile CYG_BYTE idma1[0x2];
+            volatile CYG_BYTE mcc2[0x80];
+            volatile CYG_BYTE reserved_1[0x7c];
+            volatile CYG_WORD16 smc2;  // Pointer to SMC2 DPRAM
+            volatile CYG_BYTE idma2[0x2];
+            volatile CYG_BYTE reserved_2[0xfc];
+            volatile CYG_BYTE spi[0x2];
+            volatile CYG_BYTE idma3[0x2];
+            volatile CYG_BYTE reserved_3[0xe0];
+            volatile CYG_BYTE timers[0x10];
+            volatile CYG_BYTE Rev_num[0x2];
+            volatile CYG_BYTE D_ptr[0x2];
+            volatile CYG_BYTE reserved_4[0x4];
+            volatile CYG_BYTE rand[0x4];
+            volatile CYG_BYTE i2c[0x2];
+            volatile CYG_BYTE idma4[0x2];
+            volatile CYG_BYTE reserved_5[0x500];
+       } standard;
+        
+    } pram;
+    
+    volatile CYG_BYTE reserved11[0x2000];      /* Reserved area */
+    volatile CYG_BYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */
+    volatile CYG_BYTE reserved12[0x4000];      /* Reserved area */
+
+/* siu */
+    volatile CYG_WORD siu_siumcr;        /* SIU Module Configuration Register */
+    volatile CYG_WORD siu_sypcr;         /* System Protection Control Register */
+    volatile CYG_BYTE reserved13[0x6];   /* Reserved area */
+    volatile CYG_WORD16 siu_swsr;         /* Software Service Register */
+
+/* buses */
+    volatile CYG_BYTE reserved14[0x14];  /* Reserved area */
+    volatile CYG_WORD bcr;               /* Bus Configuration Register */
+    volatile CYG_BYTE ppc_acr;           /* Arbiter Configuration Register */
+    volatile CYG_BYTE reserved15[0x3];   /* Reserved area */
+    volatile CYG_WORD ppc_alrh;          /* Arbitration level Register (First clients)*/
+    volatile CYG_WORD ppc_alrl;          /* Arbitration Level Register (Next clients) */
+    volatile CYG_BYTE lcl_acr;           /* LCL Arbiter Configuration Register */
+    volatile CYG_BYTE reserved16[0x3];   /* Reserved area */
+    volatile CYG_WORD lcl_alrh;        /* LCL Arbitration level Register (First clients)*/
+    volatile CYG_WORD lcl_alrl;        /* LCL Arbitration Level Register (Next clients) */
+    volatile CYG_WORD tescr1;       /* PPC bus transfer error status control register 1 */
+    volatile CYG_WORD tescr2;       /* PPC bus transfer error status control register 2 */
+    volatile CYG_WORD ltescr1;    /* Local bus transfer error status control register 1 */
+    volatile CYG_WORD ltescr2;    /* Local bus transfer error status control register 2 */
+    volatile CYG_WORD pdtea;             /* PPC bus DMA Transfer Error Address */
+    volatile CYG_BYTE pdtem;             /* PPC bus DMA Transfer Error MSNUM  */
+    volatile CYG_BYTE reserved17[0x3];   /* Reserved area */
+    volatile CYG_WORD ldtea;             /* PPC bus DMA Transfer Error Address */
+    volatile CYG_BYTE ldtem;             /* PPC bus DMA Transfer Error MSNUM  */
+    volatile CYG_BYTE reserved18[0xa3];  /* Reserved area */
+
+/* memc */
+    struct mem_regs 
+    {
+        volatile CYG_WORD memc_br;       /* Base Register */
+        volatile CYG_WORD memc_or;       /* Option Register */
+    } mem_regs[12];
+    volatile CYG_BYTE reserved19[0x8];   /* Reserved area */
+    volatile CYG_WORD memc_mar;          /* Memory Address Register */
+    volatile CYG_BYTE reserved20[0x4];   /* Reserved area */
+    volatile CYG_WORD memc_mamr;         /* Machine A Mode Register */
+    volatile CYG_WORD memc_mbmr;         /* Machine B Mode Register */
+    volatile CYG_WORD memc_mcmr;         /* Machine C Mode Register */
+    volatile CYG_WORD memc_mdmr;         /* Machine D Mode Register */
+    volatile CYG_BYTE reserved21[0x4];   /* Reserved area */
+    volatile CYG_WORD16 memc_mptpr;       /* Memory Periodic Timer Prescaler */
+    volatile CYG_BYTE reserved22[0x2];   /* Reserved area */
+    volatile CYG_WORD memc_mdr;          /* Memory Data Register */
+    volatile CYG_BYTE reserved23[0x4];   /* Reserved area */
+    volatile CYG_WORD memc_psdmr;        /* PowerPC Bus SDRAM machine Mode Register */
+    volatile CYG_WORD memc_lsdmr;        /* Local Bus SDRAM machine Mode Registe */
+    volatile CYG_BYTE memc_purt;         /* PowerPC Bus assigned UPM Refresh Timer */
+    volatile CYG_BYTE reserved24[0x3];   /* Reserved area */
+    volatile CYG_BYTE memc_psrt;         /* PowerPC BusBus assigned SDRAM Refresh Timer */
+    volatile CYG_BYTE reserved25[0x3];   /* Reserved area */
+    volatile CYG_BYTE memc_lurt;         /* Local Bus assigned UPM Refresh Timer */
+    volatile CYG_BYTE reserved26[0x3];   /* Reserved area */
+    volatile CYG_BYTE memc_lsrt;         /* Local Bus assigned SDRAM Refresh Timer */
+    volatile CYG_BYTE reserved27[0x3];   /* Reserved area */
+    volatile CYG_WORD memc_immr;         /* Internal Memory Map Register */
+
+/* pci */
+    volatile CYG_WORD pcibr0;            /* Base address+valid for PCI window 1 */
+    volatile CYG_WORD pcibr1;            /* Base address+valid for PCI window 2 */
+    volatile CYG_BYTE reserved28[0x10];  /* Reserved area */
+    volatile CYG_WORD pcimsk0;           /* Mask for PCI window 1 */
+    volatile CYG_WORD pcimsk1;           /* Mask for PCI window 2 */
+    volatile CYG_BYTE reserved29[0x54];  /* Reserved area */
+
+/* si_timers */
+    volatile CYG_WORD16 si_timers_tmcntsc; /* Time Counter Status and Control Register */
+    volatile CYG_BYTE reserved30[0x2];    /* Reserved area */
+    volatile CYG_WORD si_timers_tmcnt;    /* Time Counter Register */
+    volatile CYG_WORD si_timers_tmcntsec; /* Time Counter Seconds*/
+    volatile CYG_WORD si_timers_tmcntal;  /* Time Counter Alarm Register */
+    volatile CYG_BYTE reserved31[0x10];   /* Reserved area */
+    volatile CYG_WORD16 si_timers_piscr;   /* Periodic Interrupt Status and Control Reg. */
+    volatile CYG_BYTE reserved32[0x2];    /* Reserved area */
+    volatile CYG_WORD si_timers_pitc;     /* Periodic Interrupt Count Register */
+    volatile CYG_WORD si_timers_pitr;     /* Periodic Interrupt Timer Register */
+    volatile CYG_BYTE reserved33[0x54];   /* Reserved area */
+
+/* test module registers */
+    volatile CYG_WORD tstmhr;             
+    volatile CYG_WORD tstmlr;
+    volatile CYG_WORD16 tster;
+    volatile CYG_BYTE reserved34[0x156]; /* Reserved area */
+    
+/* pci, part 2 */
+    volatile CYG_WORD pci_pci;           /* PCI Configuration space */
+    volatile CYG_BYTE reserved35[0x7fc]; /* Reserved area */
+    
+/* ic */
+    volatile CYG_WORD16 ic_sicr;         /* Interrupt Configuration Register */
+    volatile CYG_BYTE reserved36[0x2];   /* Reserved area */
+    volatile CYG_BYTE ic_sivec;          /* CP Interrupt Vector Register */
+    volatile CYG_BYTE reserved36a[0x3];  /* Reserved area */
+    volatile CYG_WORD ic_sipnr_h;        /* Interrupt Pending Register (HIGH) */
+    volatile CYG_WORD ic_sipnr_l;        /* Interrupt Pending Register (LOW)    */
+    volatile CYG_WORD ic_siprr;          /* SIU Interrupt Priority Register     */
+    volatile CYG_WORD ic_scprr_h;        /* Interrupt Priority Register (HIGH) */
+    volatile CYG_WORD ic_scprr_l;        /* Interrupt Priority Register (LOW)   */
+    volatile CYG_WORD ic_simr_h;         /* Interrupt Mask Register (HIGH)      */
+    volatile CYG_WORD ic_simr_l;         /* Interrupt Mask Register (LOW)       */
+    volatile CYG_WORD ic_siexr;          /* External Interrupt Control Register */
+    volatile CYG_BYTE reserved37[0x58];  /* Reserved area */
+
+/* clocks */
+    volatile CYG_WORD clocks_sccr;       /* System Clock Control Register */
+    volatile CYG_BYTE reserved38[0x4];   /* Reserved area */
+    volatile CYG_WORD clocks_scmr;       /* System Clock Mode Register  */
+    volatile CYG_BYTE reserved39[0x4];   /* Reserved area */
+    volatile CYG_WORD clocks_rsr;        /* Reset Status Register */
+    volatile CYG_WORD clocks_rmr;        /* Reset Mode Register  */
+    volatile CYG_BYTE reserved40[0x68];  /* Reserved area */
+
+/* io_ports */
+    struct io_regs 
+    {
+       volatile CYG_WORD pdir;              /* Port A-D Data Direction Register */
+       volatile CYG_WORD ppar;              /* Port A-D Pin Assignment Register */
+       volatile CYG_WORD psor;              /* Port A-D Special Operation Register */
+       volatile CYG_WORD podr;              /* Port A-D Open Drain Register */
+       volatile CYG_WORD pdat;              /* Port A-D Data Register */
+       volatile CYG_BYTE reserved41[0xc];   /* Reserved area */
+    } io_regs[4];
+
+/* cpm_timers */
+    volatile CYG_BYTE cpm_timers_tgcr1;   /* Timer Global Configuration Register */
+    volatile CYG_BYTE reserved42[0x3];    /* Reserved area */
+    volatile CYG_BYTE cpm_timers_tgcr2;   /* Timer Global Configuration Register */
+    volatile CYG_BYTE reserved43[0xb];    /* Reserved area */
+    volatile CYG_WORD16 cpm_timers_tmr1;   /* Timer Mode Register */
+    volatile CYG_WORD16 cpm_timers_tmr2;   /* Timer Mode Register */
+    volatile CYG_WORD16 cpm_timers_trr1;   /* Timer Reference Register */
+    volatile CYG_WORD16 cpm_timers_trr2;   /* Timer Reference Register */
+    volatile CYG_WORD16 cpm_timers_tcr1;   /* Timer Capture Register */
+    volatile CYG_WORD16 cpm_timers_tcr2;   /* Timer Capture Register */
+    volatile CYG_WORD16 cpm_timers_tcn1;   /* Timer Counter */
+    volatile CYG_WORD16 cpm_timers_tcn2;   /* Timer Counter */
+    volatile CYG_WORD16 cpm_timers_tmr3;   /* Timer Mode Register */
+    volatile CYG_WORD16 cpm_timers_tmr4;   /* Timer Mode Register */
+    volatile CYG_WORD16 cpm_timers_trr3;   /* Timer Reference Register */
+    volatile CYG_WORD16 cpm_timers_trr4;   /* Timer Reference Register */
+    volatile CYG_WORD16 cpm_timers_tcr3;   /* Timer Capture Register */
+    volatile CYG_WORD16 cpm_timers_tcr4;   /* Timer Capture Register */
+    volatile CYG_WORD16 cpm_timers_tcn3;   /* Timer Counter */
+    volatile CYG_WORD16 cpm_timers_tcn4;   /* Timer Counter */
+    volatile CYG_WORD16 cpm_timers_ter[4]; /* Timer Event Register */
+    volatile CYG_BYTE reserved44[0x260];  /* Reserved area */
+
+/* sdma general */
+    volatile CYG_BYTE sdma_sdsr;         /* SDMA Status Register */
+    volatile CYG_BYTE reserved45[0x3];   /* Reserved area */
+    volatile CYG_BYTE sdma_sdmr;         /* SDMA Mask Register */
+    volatile CYG_BYTE reserved46[0x3];   /* Reserved area */
+
+/* idma */
+    volatile CYG_BYTE idma_idsr1;        /* IDMA Status Register */
+    volatile CYG_BYTE reserved47[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idmr1;        /* IDMA Mask Register */
+    volatile CYG_BYTE reserved48[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idsr2;        /* IDMA Status Register */
+    volatile CYG_BYTE reserved49[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idmr2;        /* IDMA Mask Register */
+    volatile CYG_BYTE reserved50[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idsr3;        /* IDMA Status Register */
+    volatile CYG_BYTE reserved51[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idmr3;        /* IDMA Mask Register */
+    volatile CYG_BYTE reserved52[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idsr4;        /* IDMA Status Register */
+    volatile CYG_BYTE reserved53[0x3];   /* Reserved area */
+    volatile CYG_BYTE idma_idmr4;        /* IDMA Mask Register */
+    volatile CYG_BYTE reserved54[0x2c3]; /* Reserved area */
+    
+/* fcc */
+    struct fcc_regs 
+    {
+        volatile CYG_WORD fcc_gfmr;        /* FCC General Mode Register */
+        volatile CYG_WORD fcc_psmr;        /* FCC Protocol Specific Mode Register */
+        volatile CYG_WORD16 fcc_todr;       /* FCC Transmit On Demand Register */
+        volatile CYG_BYTE reserved55[0x2]; /* Reserved area */
+        volatile CYG_WORD16 fcc_dsr;        /* FCC Data Sync. Register */
+        volatile CYG_BYTE reserved56[0x2]; /* Reserved area */
+        volatile CYG_WORD16 fcc_fcce;        /* FCC Event Register */
+        volatile CYG_BYTE reserved56a[0x2]; /* Reserved area */
+        volatile CYG_WORD16 fcc_fccm;        /* FCC Mask Register */
+        volatile CYG_BYTE reserved56b[0x2]; /* Reserved area */
+        volatile CYG_BYTE fcc_fccs;        /* FCC Status Register */
+        volatile CYG_BYTE reserved57[0x3]; /* Reserved area */
+        volatile CYG_WORD fcc_ftprr;       /* FCC Transmit Partial Rate Register */
+    } fcc_regs[3];
+    volatile CYG_BYTE reserved58[0x290];   /* Reserved area */
+    
+/* brgs 5 through 8 */
+    volatile CYG_WORD brgs_brgc5;          /* Baud Rate Generator 5 Config Register */
+    volatile CYG_WORD brgs_brgc6;          /* Baud Rate Generator 6 Config Register */
+    volatile CYG_WORD brgs_brgc7;          /* Baud Rate Generator 7 Config Register */
+    volatile CYG_WORD brgs_brgc8;          /* Baud Rate Generator 8 Config Register */
+    volatile CYG_BYTE reserved59[0x260]; /* Reserved area */
+    
+/* i2c */
+    volatile CYG_BYTE i2c_i2mod;         /* IC Mode Register */
+    volatile CYG_BYTE reserved60[0x3];   /* Reserved area */
+    volatile CYG_BYTE i2c_i2add;         /* IC Address Register */
+    volatile CYG_BYTE reserved61[0x3];   /* Reserved area */
+    volatile CYG_BYTE i2c_i2brg;         /* IC BRG Register */
+    volatile CYG_BYTE reserved62[0x3];   /* Reserved area */
+    volatile CYG_BYTE i2c_i2com;         /* IC Command Register */
+    volatile CYG_BYTE reserved63[0x3];   /* Reserved area */
+    volatile CYG_BYTE i2c_i2cer;         /* IC Event Register */
+    volatile CYG_BYTE reserved64[0x3];   /* Reserved area */
+    volatile CYG_BYTE i2c_i2cmr;         /* IC Mask Register */
+    volatile CYG_BYTE reserved65[0x14b]; /* Reserved area */
+    
+/* cpm */
+    volatile CYG_WORD  cpm_cpcr;         /* Communication Processor Command Register */
+    volatile CYG_WORD  cpm_rccr;         /* RISC Configuration Register */
+    volatile CYG_WORD  cpm_rmdr;         /* RISC Microcode Dev. Support Control Reg. */
+    volatile CYG_WORD16 cpm_rctr1;        /* RISC Controller Trap Register */
+    volatile CYG_WORD16 cpm_rctr2;        /* RISC Controller Trap Register */
+    volatile CYG_WORD16 cpm_rctr3;        /* RISC Controller Trap Register */
+    volatile CYG_WORD16 cpm_rctr4;        /* RISC Controller Trap Register */
+    volatile CYG_BYTE  reserved66[0x2];  /* Reserved area */
+    volatile CYG_WORD16 cpm_rter;         /* RISC Timers Event Register */
+    volatile CYG_BYTE  reserved67[0x2];  /* Reserved area */
+    volatile CYG_WORD16 cpm_rtmr;         /* RISC Timers Mask Register */
+    volatile CYG_WORD16 cpm_rtscr;        /* RISC Time-Stamp Timer Control Register */
+    volatile CYG_WORD16 cpm_rmds;         /* RISC Development Support Status Register */
+    volatile CYG_WORD  cpm_rtsr;         /* RISC Time-Stamp Register */
+    volatile CYG_BYTE  reserved68[0xc];  /* Reserved area */
+
+/* brgs 1 through 4 */
+    volatile CYG_WORD brgs_brgc1;          /* Baud Rate Generator 5 Config Register */
+    volatile CYG_WORD brgs_brgc2;          /* Baud Rate Generator 2 Config Register */
+    volatile CYG_WORD brgs_brgc3;          /* Baud Rate Generator 3 Config Register */
+    volatile CYG_WORD brgs_brgc4;          /* Baud Rate Generator 4 Config Register */
+    
+/* scc */
+    struct scc_regs_8260
+    {
+        volatile CYG_WORD  gsmr_l;          /* SCC General Mode Register */
+        volatile CYG_WORD  gsmr_h;          /* SCC General Mode Register */
+        volatile CYG_WORD16 psmr;            /* SCC Protocol Specific Mode Register */
+        volatile CYG_BYTE  reserved69[0x2]; /* Reserved area */
+        volatile CYG_WORD16 todr;            /* SCC Transmit-On-Demand Register */
+        volatile CYG_WORD16 dsr;             /* SCC Data Synchronization Register */
+        volatile CYG_WORD16 scce;            /* SCC Event Register */
+        volatile CYG_BYTE  reserved70[0x2]; /* Reserved area */
+        volatile CYG_WORD16 sccm;            /* SCC Mask Register */
+        volatile CYG_BYTE  reserved71;      /* Reserved area */
+        volatile CYG_BYTE  sccs;            /* SCC Status Register */
+        volatile CYG_BYTE  reserved72[0x8]; /* Reserved area */
+    } scc_regs[4];
+    
+/* smc */
+    struct smc_regs_8260
+    {
+        volatile CYG_BYTE reserved73[0x2]; /* Reserved area */
+        volatile CYG_WORD16 smc_smcmr;      /* SMC Mode Register */
+        volatile CYG_BYTE reserved74[0x2]; /* Reserved area */
+        volatile CYG_BYTE smc_smce;        /* SMC Event Register */
+        volatile CYG_BYTE reserved75[0x3]; /* Reserved area */
+        volatile CYG_BYTE smc_smcm;        /* SMC Mask Register */
+        volatile CYG_BYTE reserved76[0x5]; /* Reserved area */
+    } smc_regs[2];
+    
+/* spi */
+    volatile CYG_WORD16 spi_spmode;       /* SPI Mode Register */
+    volatile CYG_BYTE reserved77[0x4];   /* Reserved area */
+    volatile CYG_BYTE spi_spie;          /* SPI Event Register */
+    volatile CYG_BYTE reserved78[0x3];   /* Reserved area */
+    volatile CYG_BYTE spi_spim;          /* SPI Mask Register */
+    volatile CYG_BYTE reserved79[0x2];   /* Reserved area */
+    volatile CYG_BYTE spi_spcom;         /* SPI Command Register */
+    volatile CYG_BYTE reserved80[0x52];  /* Reserved area */
+    
+/* cpm_mux */
+
+    volatile CYG_BYTE  cpm_mux_cmxsi1cr;    /* CPM MUX SI Clock Route Register */
+    volatile CYG_BYTE  reserved81;          /* Reserved area */
+    volatile CYG_BYTE  cpm_mux_cmxsi2cr;    /* CPM MUX SI Clock Route Register */
+    volatile CYG_BYTE  reserved82;          /* Reserved area */
+    volatile CYG_WORD  cpm_mux_cmxfcr;      /* CPM MUX FCC Clock Route Register */
+    volatile CYG_WORD  cpm_mux_cmxscr;      /* CPM MUX SCC Clock Route Register */
+    volatile CYG_BYTE  cpm_mux_cmxsmr;      /* CPM MUX SMC Clock Route Register */
+    volatile CYG_BYTE  reserved83;          /* Reserved area */
+    volatile CYG_WORD16 cpm_mux_cmxuar;      /* CPM MUX UTOPIA Address Register */
+    volatile CYG_BYTE  reserved84[0x10];    /* Reserved area */
+    
+/* si */
+    struct si_regs 
+    {
+        volatile CYG_WORD16 si_si1mr[4];    /* SI TDM Mode Registers */
+        volatile CYG_BYTE si_si1gmr;       /* SI Global Mode Register */
+        volatile CYG_BYTE reserved85;      /* Reserved area */
+        volatile CYG_BYTE si_si1cmdr;      /* SI Command Register */
+        volatile CYG_BYTE reserved86;      /* Reserved area */
+        volatile CYG_BYTE si_si1str;       /* SI Status Register */
+        volatile CYG_BYTE reserved87;      /* Reserved area */
+        volatile CYG_WORD16 si_si1rsr;      /* SI RAM Shadow Address Register */
+        volatile CYG_WORD16 mcc_mcce;       /* MCC Event Register */
+        volatile CYG_BYTE reserved88[0x2]; /* Reserved area */
+        volatile CYG_WORD16 mcc_mccm;       /* MCC Mask Register */
+        volatile CYG_BYTE reserved89[0x2]; /* Reserved area */
+        volatile CYG_BYTE mcc_mccf;        /* MCC Configuration Register */
+        volatile CYG_BYTE reserved90[0x7]; /* Reserved area */
+    } si_regs[2];
+    volatile CYG_BYTE reserved91[0x4a0];   /* Reserved area */
+    
+/* si_ram */
+    struct si_ram 
+    {
+        CYG_WORD16 si1_ram_si1_tx_ram[0x100]; /* SI Transmit Routing RAM */
+        volatile CYG_BYTE reserved92[0x200];         /* Reserved area */
+        CYG_WORD16 si1_ram_si1_rx_ram[0x100]; /* SI Receive Routing RAM */
+        volatile CYG_BYTE reserved93[0x200];         /* Reserved area */
+    } si_ram[2];
+    volatile CYG_BYTE reserved94[0x1000];  /* Reserved area */
+
+} _PackedType t_PQ2IMM;
+
+extern volatile t_PQ2IMM  *IMM;   /* IMM base pointer */
+
+/***************************************************************************/
+/*                   General Global Definitions                            */
+/***************************************************************************/
+
+#define PAGE1     0         /* SCC1 Index into SCC Param RAM Array */
+#define PAGE2     1         /* SCC2 Index into SCC Param RAM Array */
+#define PAGE3     2         /* SCC3 Index into SCC Param RAM Array */
+#define PAGE4     3         /* SCC4 Index into SCC Param RAM Array */
+
+#define SCC1      0         /* SCC1 Index into SCC Regs Array  */          
+#define SCC2      1         /* SCC2 Index into SCC Regs Array  */          
+#define SCC3      2         /* SCC3 Index into SCC Regs Array  */          
+#define SCC4      3         /* SCC4 Index into SCC Regs Array  */          
+
+#define SMC1      0         /* SMC1 Index into SMC Regs Array  */          
+#define SMC2      1         /* SMC2 Index into SMC Regs Array  */          
+
+#define PORT_A    0         /* Parallel port A registers */
+#define PORT_B    1         /* Parallel port B registers */
+#define PORT_C    2         /* Parallel port C registers */
+#define PORT_D    3         /* Parallel port D registers */
+
+/*--------------------------------*/
+/* KEEP ALIVE POWER REGISTERS KEY */
+/*--------------------------------*/
+
+#define KEEP_ALIVE_KEY 0x55ccaa33
+
+/*------------------------------------------*
+* CPM Command Register (CPCR)               *
+*-------------------------------------------*
+* NOTE: This register is cleared by reset.  *
+*       See MPC8260 User's Manual.          *
+*-------------------------------------------*/
+
+#define CPCR_RST                 0x80000000  /* Software Reset Command */
+#define CPCR_FLG                 0x00010000  /* Command Semaphore Flag */
+
+#define CPCR_SUBBLOCK(page,code) ((page<<26)|(code<<21))
+
+/*-----------------------------------------------*/
+/* Definitions for SCC CPCR Subblock/Page codes. */
+/*-----------------------------------------------*/
+
+#define  SCC1_PAGE_SUBBLOCK    CPCR_SUBBLOCK(0,4)
+#define  SCC2_PAGE_SUBBLOCK    CPCR_SUBBLOCK(1,5)
+#define  SCC3_PAGE_SUBBLOCK    CPCR_SUBBLOCK(2,6)
+#define  SCC4_PAGE_SUBBLOCK    CPCR_SUBBLOCK(3,7)
+
+/*-----------------------------------------------*/
+/* Definitions for SMC CPCR Subblock/Page codes. */
+/*-----------------------------------------------*/
+
+#define  SMC1_PAGE_SUBBLOCK    CPCR_SUBBLOCK(7,8)
+#define  SMC2_PAGE_SUBBLOCK    CPCR_SUBBLOCK(8,9)
+
+/*-----------------------------------------------*/
+/* Definitions for FCC CPCR Subblock/Page codes. */
+/*-----------------------------------------------*/
+
+#define  FCC1_PAGE_SUBBLOCK    CPCR_SUBBLOCK(4,0x10)
+#define  FCC2_PAGE_SUBBLOCK    CPCR_SUBBLOCK(5,0x11)
+#define  FCC3_PAGE_SUBBLOCK    CPCR_SUBBLOCK(6,0x12)
+
+/*-----------------------------*/
+/* Opcode definitions for SCCs, opcodes for SMC's are the same
+ * except not all codes are valid for SMC */
+/*-----------------------------*/
+
+#define CPCR_INIT_TX_RX_PARAMS   0x00000000   /* Opcode 0 */
+#define CPCR_INIT_RX_PARAMS      0x00000001   /* Opcode 1 */
+#define CPCR_INIT_TX_PARAMS      0x00000002   /* Opcode 2 */
+#define CPCR_ENTER_HUNT_MODE     0x00000003   /* Opcode 3 */
+#define CPCR_STOP_TX             0x00000004   /* Opcode 4 */
+#define CPCR_GRACEFUL_STOP_TX    0x00000005   /* Opcode 5 */
+#define CPCR_RESTART_TX          0x00000006   /* Opcode 6 */
+#define CPCR_CLOSE_RX_BD         0x00000007   /* Opcode 7 */
+#define CPCR_SET_GRP_ADDR        0x00000008   /* Opcode 8 */
+#define CPCR_RESET_BCS           0x0000000A   /* Opcode 10 */
+
+/*-----------------------------------------------------*/
+/* General Definitions for SCC CPCR Command Operations */
+/*-----------------------------------------------------*/
+
+#define READY_TO_RX_CMD          0x00000000
+
+/*-------------------------*/
+/* General SCC Definitions */
+/*-------------------------*/
+
+#define  DISABLE_TX_RX   0xFFFFFFCF  /* Clear the ENT/ENR bits in the GSMR
+                                        Disables the transmit & Receive
+                                        port                              */
+
+#define  GSMR_L1_ENT  0x00000010     /* ENT bit for the GSMR low register */
+#define  GSMR_L1_ENR  0x00000020     /* ENR bit for the GSMR low register */
+
+
+#define  ALL_ONES    0xFFFF
+
+//
+// Routines which help manage the CPM
+//
+externC void _mpc8xxx_reset_cpm(void);
+externC unsigned int _mpc8xxx_allocBd(int len);
+
+#endif // ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
Index: hal/powerpc/mpc8xxx/current/include/var_cache.h
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/include/var_cache.h
diff -N hal/powerpc/mpc8xxx/current/include/var_cache.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/include/var_cache.h	19 Aug 2003 16:45:09 -0000
@@ -0,0 +1,374 @@
+#ifndef CYGONCE_VAR_CACHE_H
+#define CYGONCE_VAR_CACHE_H
+//=============================================================================
+//
+//      var_cache.h
+//
+//      Variant HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   pfine
+// Contributors:nickg, jskov
+// Date:        2001-12-12
+// Purpose:     Variant cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+//              cache control operations on the MPC8260 variant CPU.
+// Usage:       Is included via the architecture cache header:
+//              #include <cyg/hal/hal_cache.h>
+//              ...
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/ppc_regs.h>
+#include <cyg/hal/var_regs.h>
+
+#include <cyg/hal/plf_cache.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+#define HAL_DCACHE_SIZE                 16384    // Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE            32       // Size of a data cache line
+#define HAL_DCACHE_WAYS                 4        // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE                 16384    // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE            32       // Size of a cache line
+#define HAL_ICACHE_WAYS                 4        // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()                 \
+    CYG_MACRO_START                         \
+    cyg_uint32 tmp1, tmp2;                  \
+    asm volatile (                          \
+        "mfspr %1, %2;"                     \
+        "li %0, 0x4000;"                     \
+        "rlwimi %1,%0,0,17,17;"             \
+        "sync;"                             \
+        "mtspr %2,%1;"                      \
+        "isync;"                            \
+        "sync;"                             \
+        : "=r" (tmp1), "=r" (tmp2)          \
+        : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
+    CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()                \
+    CYG_MACRO_START                         \
+    register cyg_uint32 tmp1;               \
+    register cyg_uint32 tmp2;               \
+    for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \
+        tmp2 = *((cyg_uint32 *) tmp1);      \
+    asm volatile (                          \
+        "mfspr %1, %2;"                     \
+        "li %0, 0x0;"                       \
+        "rlwimi %1,%0,0,17,17;"             \
+        "sync;"                             \
+        "mtspr %2,%1;"                      \
+        "isync;"                            \
+        "sync;"                             \
+        : "=r" (tmp1), "=r" (tmp2)          \
+        : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
+    CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()                   \
+    CYG_MACRO_START                                   \
+    cyg_uint32 tmp1, tmp2;                            \
+    asm volatile ("sync;"                             \
+                  "mfspr %0, %2;"                     \
+                  "ori   %0, %0, 0x0400;"             \
+                  "mtspr %2, %0;"                     \
+                  "li    %1, 0;"                      \
+                  "rlwimi %0,%1,0,21,21;"             \
+                  "mtspr %2, %0;"                     \
+                  "sync;"                             \
+                  : "=r" (tmp1), "=r" (tmp2)          \
+                  : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
+    CYG_MACRO_END
+
+
+// Synchronize the contents of the cache with memory.
+// Modifications to this macro should mirror modifications to the
+// identically named one in the ppc60x variant.
+// We step through twice the number of lines in the cache in order
+// to ensure that all dirty lines are flushed to main memory.
+// (Consider the case where one of the dirty lines is in the
+// first 16Kbytes of RAM -- it won't get flushed by loading
+// in words from the first 16Kbytes of RAM).
+#define HAL_DCACHE_SYNC()                                       \
+    CYG_MACRO_START                                             \
+    cyg_int32 i;                                                \
+    cyg_uint32 *__base = (cyg_uint32 *) (0);                    \
+    for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){                                                 \
+        asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0");     \
+    }                                                           \
+    CYG_MACRO_END
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_)                          \
+    asm volatile ("mfspr  %0, %1;"                              \
+                  "rlwinm %0,%0,18,31,31;"                      \
+                  : "=r" (_state_) : "I" (CYGARC_REG_HID0))     
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE       0
+//#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+#define HAL_DCACHE_UNLOCK_ALL()                       \
+    asm volatile ("isync;"                            \
+                  "mfspr %0, %2;"                     \
+                  "oris  %1, 0,0xFFFF;"               \
+                  "ori   %1,%1,0xEFFF;"               \
+                  "and   %0,%0,%1;"                   \
+                  "mtspr %2,%0;"                      \
+                  "isync;"                            \
+                  "sync;"                             \
+                  : /* No output */                   \
+                  : "I" (5) /* %0 ==> r5 */,          \
+                    "I" (6) /* %1 ==> r6 */,          \
+                    "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
+
+
+// Invalidate cache lines in the given range without writing to memory.
+// NOTE: The errata for the 603e processor indicates use of the dcbf
+// command as the dcbi command will only invalidate modified blocks.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
+
+// Write dirty cache lines to memory for the given address range.
+#define HAL_DCACHE_STORE( _base_ , _size_ )                     \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbst 0,%0;sync;" : : "r" (__base));     \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()                 \
+    CYG_MACRO_START                         \
+    cyg_uint32 tmp1, tmp2;                  \
+    asm volatile (                          \
+        "mfspr %1, %2;"                     \
+        "li %0, 0x4000;"                    \
+        "rlwimi %1,%0,1,16,16;"             \
+        "sync;"                             \
+        "isync;"                            \
+        "mtspr %2,%1;"                      \
+        "isync;"                            \
+        "sync;"                             \
+        : "=r" (tmp1), "=r" (tmp2)          \
+        : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
+    CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()                          \
+    CYG_MACRO_START                         \
+    cyg_uint32 tmp1, tmp2;                  \
+    asm volatile (                          \
+        "mfspr %1, %2;"                     \
+        "li %0, 0x0;"                       \
+        "rlwimi %1,%0,0,16,16;"             \
+        "sync;"                             \
+        "isync;"                            \
+        "mtspr %2,%1;"                      \
+        "isync;"                            \
+        "sync;"                             \
+        : "=r" (tmp1), "=r" (tmp2)          \
+        : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
+    CYG_MACRO_END
+
+// Invalidate the entire cache
+#if 1
+#define HAL_ICACHE_INVALIDATE_ALL()                   \
+    CYG_MACRO_START                                   \
+    cyg_uint32 tmp1, tmp2;                            \
+    asm volatile ("sync;"                             \
+                  "mfspr %0, %2;"                     \
+                  "ori   %1, %0, 0x8000;"             \
+                  "mtspr %2, %1;"                     \
+                  "isync;"                            \
+                  "sync;"                             \
+                  "ori   %1, %1, 0x0800;"             \
+                  "mtspr %2, %1;"                     \
+                  "isync;"                            \
+                  "sync;"                             \
+                  "mtspr %2, %0;"                     \
+                  "isync;"                            \
+                  "sync;"                             \
+                  : "=r" (tmp1), "=r" (tmp2)          \
+                  : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
+    CYG_MACRO_END
+#else
+#define HAL_ICACHE_INVALIDATE_ALL()                   \
+    CYG_MACRO_START                                   \
+    cyg_uint32 tmp1, tmp2;                            \
+    asm volatile ("sync;"                             \
+                  "mfspr %0, %2;"                     \
+                  "ori   %0, %0, 0x0800;"             \
+                  "isync;"                            \
+                  "mtspr %2, %0;"                     \
+                  "li    %1, 0;"                      \
+                  "rlwimi %0,%1,0,20,20;"             \
+                  "isync;"                            \
+                  "mtspr %2, %0;"                     \
+                  "isync;"                            \
+                  "sync;"                             \
+                  : "=r" (tmp1), "=r" (tmp2)          \
+                  : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
+    CYG_MACRO_END
+#endif
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()                             \
+    HAL_ICACHE_INVALIDATE_ALL()
+
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_)                          \
+    asm volatile ("mfspr  %0, %1;"                              \
+                  "rlwinm %0,%0,17,31,31;"                      \
+                  : "=r" (_state_) : "I" (CYGARC_REG_HID0))
+
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+#define HAL_ICACHE_UNLOCK_ALL()                       \
+    asm volatile ("isync;"                            \
+                  "mfspr %0, %2;"                     \
+                  "oris  %1, 0,0xFFFF;"               \
+                  "ori   %1,%1,0xDFFF;"               \
+                  "and   %0,%0,%1;"                   \
+                  "isync;"                            \
+                  "mtspr %2,%0;"                      \
+                  "isync;"                            \
+                  "sync;"                             \
+                  : /* No output */                   \
+                  : "I" (5) /* %0 ==> r5 */,          \
+                    "I" (6) /* %1 ==> r6 */,          \
+                    "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_VAR_CACHE_H
+// End of var_cache.h
Index: hal/powerpc/mpc8xxx/current/include/var_intr.h
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/include/var_intr.h
diff -N hal/powerpc/mpc8xxx/current/include/var_intr.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/include/var_intr.h	19 Aug 2003 14:52:04 -0000
@@ -0,0 +1,359 @@
+#ifndef CYGONCE_VAR_INTR_H
+#define CYGONCE_VAR_INTR_H
+//=============================================================================
+//
+//      var_intr.h
+//
+//      Variant HAL interrupt and clock support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   mtek, pfine
+// Contributors:nickg, jskov, jlarmour, hmt
+// Date:        2001-12-12
+// Purpose:     Variant interrupt support
+// Description: The macros defined here provide the HAL APIs for handling
+//              interrupts and the clock on the MPC8xxx PowerQUICCII CPU.
+// Usage:       Is included via the architecture interrupt header:
+//              #include <cyg/hal/hal_intr.h>
+//              ...
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+#include <pkgconf/hal.h>
+#include <cyg/hal/plf_intr.h>
+#include <cyg/hal/mpc8xxx.h>            // Memory map
+#include <cyg/infra/cyg_type.h>         // types
+#include <cyg/hal/hal_io.h>             // io macros
+#include <cyg/infra/cyg_ass.h>          // CYG_FAIL
+
+#include <cyg/infra/diag.h>
+
+// Interrupts
+
+// The first level of external interrupts
+#define CYGNUM_HAL_INTERRUPT_I2C                 1
+#define CYGNUM_HAL_INTERRUPT_SPI                 2
+#define CYGNUM_HAL_INTERRUPT_RISC_TIMERS         3
+#define CYGNUM_HAL_INTERRUPT_SMC1                4
+#define CYGNUM_HAL_INTERRUPT_SMC2                5
+#define CYGNUM_HAL_INTERRUPT_IDMA1               6
+#define CYGNUM_HAL_INTERRUPT_IDMA2               7
+#define CYGNUM_HAL_INTERRUPT_IDMA3               8
+#define CYGNUM_HAL_INTERRUPT_IDMA4               9
+#define CYGNUM_HAL_INTERRUPT_SDMA               10
+
+#define CYGNUM_HAL_INTERRUPT_TIMER1             12
+#define CYGNUM_HAL_INTERRUPT_TIMER2             13
+#define CYGNUM_HAL_INTERRUPT_TIMER3             14
+#define CYGNUM_HAL_INTERRUPT_TIMER4             15
+#define CYGNUM_HAL_INTERRUPT_TMCNT              16
+#define CYGNUM_HAL_INTERRUPT_PIT                17
+
+#define CYGNUM_HAL_INTERRUPT_IRQ1               19
+#define CYGNUM_HAL_INTERRUPT_IRQ2               20
+#define CYGNUM_HAL_INTERRUPT_IRQ3               21
+#define CYGNUM_HAL_INTERRUPT_IRQ4               22
+#define CYGNUM_HAL_INTERRUPT_IRQ5               23
+#define CYGNUM_HAL_INTERRUPT_IRQ6               24
+#define CYGNUM_HAL_INTERRUPT_IRQ7               25
+
+#define CYGNUM_HAL_INTERRUPT_FCC1               32
+#define CYGNUM_HAL_INTERRUPT_FCC2               33
+#define CYGNUM_HAL_INTERRUPT_FCC3               34
+
+#define CYGNUM_HAL_INTERRUPT_MCC1               36
+#define CYGNUM_HAL_INTERRUPT_MCC2               37
+
+#define CYGNUM_HAL_INTERRUPT_SCC1               40
+#define CYGNUM_HAL_INTERRUPT_SCC2               41
+#define CYGNUM_HAL_INTERRUPT_SCC3               42
+#define CYGNUM_HAL_INTERRUPT_SCC4               43
+
+#define CYGNUM_HAL_INTERRUPT_PC15               48
+#define CYGNUM_HAL_INTERRUPT_PC14               49
+#define CYGNUM_HAL_INTERRUPT_PC13               50
+#define CYGNUM_HAL_INTERRUPT_PC12               51
+#define CYGNUM_HAL_INTERRUPT_PC11               52
+#define CYGNUM_HAL_INTERRUPT_PC10               53
+#define CYGNUM_HAL_INTERRUPT_PC9                54
+#define CYGNUM_HAL_INTERRUPT_PC8                55
+#define CYGNUM_HAL_INTERRUPT_PC7                56
+#define CYGNUM_HAL_INTERRUPT_PC6                57
+#define CYGNUM_HAL_INTERRUPT_PC5                58
+#define CYGNUM_HAL_INTERRUPT_PC4                59
+#define CYGNUM_HAL_INTERRUPT_PC3                60
+#define CYGNUM_HAL_INTERRUPT_PC2                61
+#define CYGNUM_HAL_INTERRUPT_PC1                62
+#define CYGNUM_HAL_INTERRUPT_PC0                63
+
+#define CYGNUM_HAL_INTERRUPT_ERROR          0
+
+#define CYGNUM_HAL_ISR_MAX                   CYGNUM_HAL_INTERRUPT_PC0
+
+//--------------------------------------------------------------------------
+// Interrupt controller access
+
+#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
+#ifdef CYGPKG_HAL_POWERPC_MPC8XXX
+
+static __inline__ void
+cyg_hal_interrupt_mask ( cyg_uint32 vector )
+{
+  volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
+  cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h);
+  cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l);
+
+  switch (vector) {
+    
+  case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
+    *reg_simr_h &= ~( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
+    *reg_simr_h &= ~( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_TMCNT:
+    *reg_simr_h &= ~(0x00000004);
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_PIT:
+    *reg_simr_h &= ~(0x00000002);
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
+    *reg_simr_l &= ~( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
+    *reg_simr_l &= ~( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
+    *reg_simr_l &= ~( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
+    break;
+    
+  case  CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
+    *reg_simr_l &= ~( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
+    *reg_simr_l &= ~( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
+    break;
+
+  default:
+    CYG_FAIL("Unknown Interrupt in mask !!!");
+    break;
+  }
+
+}
+
+static __inline__ void
+cyg_hal_interrupt_unmask ( cyg_uint32 vector )
+{
+
+  volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
+  cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h);
+  cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l);
+
+  switch (vector) {
+    
+  case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
+    *reg_simr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
+    *reg_simr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_TMCNT:
+    *reg_simr_h |= (0x00000004);
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_PIT:
+    *reg_simr_h |= (0x00000002);
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
+    *reg_simr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
+    *reg_simr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
+    *reg_simr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
+    break;
+    
+  case  CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
+    *reg_simr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
+    *reg_simr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
+    break;
+
+  default:
+    CYG_FAIL("Unknown Interrupt in unmask !!!");
+    break;
+  }
+
+}
+
+static __inline__ void
+cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
+{
+
+  volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
+  cyg_uint32 *reg_sipnr_h = (cyg_uint32 *) &(IMM->ic_sipnr_h);
+  cyg_uint32 *reg_sipnr_l = (cyg_uint32 *) &(IMM->ic_sipnr_l);
+
+  switch (vector) {
+    
+  case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
+    *reg_sipnr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
+    *reg_sipnr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_TMCNT:
+    *reg_sipnr_h |= (0x00000004);
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_PIT:
+    *reg_sipnr_h |= (0x00000002);
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
+    *reg_sipnr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
+    *reg_sipnr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
+    *reg_sipnr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
+    break;
+    
+  case  CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
+    *reg_sipnr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
+    break;
+
+  case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
+    *reg_sipnr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
+    break;
+
+  default:
+    CYG_FAIL("Unknown Interrupt in unmask !!!");
+    break;
+  }
+
+}
+
+static __inline__ void
+cyg_hal_interrupt_configure ( cyg_uint32 vector,
+                              cyg_bool level,
+                              cyg_bool up )
+{
+  // NOT IMPLEMENTED ...
+}
+
+
+static __inline__ void
+cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
+{
+
+  // NOT IMPLEMENTED  ....
+  // FACT : USER should not program the same interrupt to more than
+  // one priority position. 
+  // FACT : Every interrupt has an assigned default priority.
+
+  // PROBLEM : One has to find the previous priority of the given vector
+  // and swap(?) it with the requested priority owner (Not nice because
+  // it changes another interrupt's priority inadvertently)
+
+}
+
+// The decrementer interrupt cannnot be masked, configured or acknowledged.
+
+#define HAL_INTERRUPT_MASK( _vector_ )                    \
+    CYG_MACRO_START                                       \
+    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
+        cyg_hal_interrupt_mask ( (_vector_) );            \
+    CYG_MACRO_END
+
+#define HAL_INTERRUPT_UNMASK( _vector_ )                  \
+    CYG_MACRO_START                                       \
+    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
+        cyg_hal_interrupt_unmask ( (_vector_) );          \
+    CYG_MACRO_END
+
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )             \
+    CYG_MACRO_START                                       \
+    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
+        cyg_hal_interrupt_acknowledge ( (_vector_) );     \
+    CYG_MACRO_END
+
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )              \
+    CYG_MACRO_START                                                     \
+    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))                 \
+        cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) );  \
+    CYG_MACRO_END
+
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )            \
+    CYG_MACRO_START                                             \
+    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))         \
+        cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
+    CYG_MACRO_END
+
+#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
+
+#endif
+#endif
+
+
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_VAR_INTR_H
+// End of var_intr.h
Index: hal/powerpc/mpc8xxx/current/include/var_regs.h
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/include/var_regs.h
diff -N hal/powerpc/mpc8xxx/current/include/var_regs.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/include/var_regs.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,275 @@
+#ifndef CYGONCE_HAL_VAR_REGS_H
+#define CYGONCE_HAL_VAR_REGS_H
+
+//==========================================================================
+//
+//      var_regs.h
+//
+//      PowerPC MPC8xxx CPU definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    pfine
+// Contributors: jskov
+// Date:         2001-12-12
+// Purpose:      Provide MPC8260 register definitions
+// Description:  Provide MPC8260 register definitions
+//               The short definitions (sans CYGARC_REG_) are exported only
+//               if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
+// Usage:        Included via the acrhitecture register header:
+//               #include <cyg/hal/ppc_regs.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+//--------------------------------------------------------------------------
+#define CYGARC_REG_LR   8              // Link Register
+#define CYGARC_REG_CTR   9              // Counter Register
+
+#define CYGARC_REG_DSISR  18
+#define CYGARC_REG_DAR    19
+#define CYGARC_REG_DEC    22
+#define CYGARC_REG_SDR1   25
+
+#define CYGARC_REG_TBL  268
+#define CYGARC_REG_TBU  269
+
+#define CYGARC_REG_SPRG0  272
+#define CYGARC_REG_SPRG1  273
+#define CYGARC_REG_SPRG2  274
+#define CYGARC_REG_SPRG3  275
+#define CYGARC_REG_EAR    282
+#define CYGARC_REG_PVR    287
+
+#define CYGARC_REG_IBAT0U          528
+#define CYGARC_REG_IBAT0L          529
+#define CYGARC_REG_IBAT1U          530
+#define CYGARC_REG_IBAT1L          531
+#define CYGARC_REG_IBAT2U          532
+#define CYGARC_REG_IBAT2L          533
+#define CYGARC_REG_IBAT3U          534
+#define CYGARC_REG_IBAT3L          535
+
+#define CYGARC_REG_DBAT0U          536
+#define CYGARC_REG_DBAT0L          537
+#define CYGARC_REG_DBAT1U          538
+#define CYGARC_REG_DBAT1L          539
+#define CYGARC_REG_DBAT2U          540
+#define CYGARC_REG_DBAT2L          541
+#define CYGARC_REG_DBAT3U          542
+#define CYGARC_REG_DBAT3L          543
+
+#define CYGARC_REG_DMISS   976
+#define CYGARC_REG_DCMP    977
+#define CYGARC_REG_HASH1   978
+#define CYGARC_REG_HASH2   979
+#define CYGARC_REG_IMISS   980
+#define CYGARC_REG_ICMP    981
+#define CYGARC_REG_RPA     982
+
+
+// Hardware Implementation Defined Special Purpose Registers
+#define CYGARC_REG_HID0   1008
+#define CYGARC_REG_HID1   1009
+#define CYGARC_REG_IABR   1010
+#define CYGARC_REG_HID2   1011
+#define CYGARC_REG_DABR   1013
+
+// MPC8260 Internal Memory Mapped Registers
+// These values are the offsets from the base memory address, which
+// is stored in the IMMR register (0x101A8).
+#define CYGARC_REG_IMM_SIUMCR    0x0000   // SIU Module Configuration Register
+#define CYGARC_REG_IMM_SYPCR     0x0004   // System Protection Control Register
+#define CYGARC_REG_IMM_SWSR      0x000E   // Software Service Register
+#define CYGARC_REG_IMM_BCR       0x0024   // Bus Configuration Register
+#define CYGARC_REG_IMM_PPC_ACR   0x0028   // .60x Bus Arbiter Config Register
+#define CYGARC_REG_IMM_PPC_ALRH  0x002C   // .60x Bus Arb-Level[High] Register
+#define CYGARC_REG_IMM_PPC_ALRL  0x0030   // .60x Bus Arb-Level[Low] Register
+#define CYGARC_REG_IMM_LCL_ACR   0x0034   // Local Arbiter Config Register
+#define CYGARC_REG_IMM_LCL_ALRH  0x0038   // Local Arb-Level[High] Register
+#define CYGARC_REG_IMM_LCL_ALRL  0x003C   // Local Arb-Level[Low] Register
+#define CYGARC_REG_IMM_TESCR1    0x0040   // .60x Bus Transfer Error Status and
+                                          //    Control Register 1
+#define CYGARC_REG_IMM_TESCR2    0x0044   // .60x Bus Transfer Error Status and
+                                          //    Control Register 2
+
+#define CYGARC_REG_IMM_LTESCR1   0x0048   // Local Bus Transfer Error Status
+                                          //    and Control Register 1
+#define CYGARC_REG_IMM_LTESCR2   0x004C   // Local Bus Transfer Error Status and
+                                          // //Control Register 2
+
+#define CYGARC_REG_IMM_PDTEA     0x0050   // .60x Bus DMA Transfer
+                                          //    Error Address
+#define CYGARC_REG_IMM_PDTEM     0x0054   // .60x Bus DMA Transfer Error MSNUM
+#define CYGARC_REG_IMM_LDTEA     0x0058   // Local Bus DMA Xfer Error Address
+#define CYGARC_REG_IMM_LDTEM     0x005C   // Local Bus DMA Transfer Error MSNUM
+ 
+#define CYGARC_REG_IMM_SCCR      0x0C80   // System Clock Control Register
+#define CYGARC_REG_IMM_SCMR      0x0C88   // System Clock Mode Register
+#define CYGARC_REG_IMM_BR0       0x0100   // Base Register Bank 0
+#define CYGARC_REG_IMM_OR0       0x0104   // Option Register Bank 0
+#define CYGARC_REG_IMM_BR1       0x0108   // Base Register Bank 1
+#define CYGARC_REG_IMM_OR1       0x010C   // Option Register Bank 1
+#define CYGARC_REG_IMM_BR2       0x0110   // Base Register Bank 2
+#define CYGARC_REG_IMM_OR2       0x0114   // Option Regiser Bank 2
+#define CYGARC_REG_IMM_BR3       0x0118   // Base Register Bank 3
+#define CYGARC_REG_IMM_OR3       0x011C   // Option Register Bank 3
+#define CYGARC_REG_IMM_BR4       0x0120   // Base Register Bank 4
+#define CYGARC_REG_IMM_OR4       0x0124   // Option Register Bank 4
+#define CYGARC_REG_IMM_BR5       0x0128   // Base Register Bank 5
+#define CYGARC_REG_IMM_OR5       0x012C   // Option Register Bank 5
+#define CYGARC_REG_IMM_BR6       0x0130   // Base Register Bank 6
+#define CYGARC_REG_IMM_OR6       0x0134   // Option Register Bank 6
+#define CYGARC_REG_IMM_BR7       0x0138   // Base Register Bank 7
+#define CYGARC_REG_IMM_OR7       0x013C   // Option Register Bank 7
+#define CYGARC_REG_IMM_BR8       0x0140   // Base Register Bank 8
+#define CYGARC_REG_IMM_OR8       0x0144   // Option Regiser Bank 8
+#define CYGARC_REG_IMM_BR9       0x0148   // Base Register Bank 9
+#define CYGARC_REG_IMM_OR9       0x014C   // Option Register Bank 9
+#define CYGARC_REG_IMM_BR10      0x0150   // Base Register Bank 10
+#define CYGARC_REG_IMM_OR10      0x0154   // Option Register Bank 10
+#define CYGARC_REG_IMM_BR11      0x0158   // Base Register Bank 11
+#define CYGARC_REG_IMM_OR11      0x015C   // Option Register Bank 11
+
+#define CYGARC_REG_IMM_MAR       0x0168   // Memory Address Register
+#define CYGARC_REG_IMM_MAMR      0x0170   // Machine A mode Register
+#define CYGARC_REG_IMM_MBMR      0x0174   // Machine B mode Register
+#define CYGARC_REG_IMM_MCMR      0x0178   // Machine C mode Register
+
+#define CYGARC_REG_IMM_MPTPR     0x0184   // Memory Periodic Timer
+                                          //    Prescaler Register
+#define CYGARC_REG_IMM_MDR       0x0188   // Memory Data Register
+#define CYGARC_REG_IMM_PSDMR     0x0190   // PowerPC Bus SDRAM Machine
+                                          //    Mode Register
+#define CYGARC_REG_IMM_LSDMR     0x0194   // Local Bus SDRAM Machine
+                                          //    Mode Register
+#define CYGARC_REG_IMM_PURT      0x0198   // .60x Bus-assigned UPM Refresh timer
+#define CYGARC_REG_IMM_PSRT      0x019C   // .60x Bus Assigned SDRAM
+                                          //    Refresh Timer
+#define CYGARC_REG_IMM_LURT      0x01A0   // Local Bus-assigned UPM
+                                          //    Refresh timer
+#define CYGARC_REG_IMM_LSRT      0x01A4   // Local Bus Assigned SDRAM
+                                          //    Refresh Timer
+#define CYGARC_REG_IMM_IMMR      0x01A8   // Internal I/O base register offset
+
+// Interrupt Controller
+#define CYGARC_REG_IMM_SICR      0x0C00   // SIU Interrupt Config Register
+#define CYGARC_REG_IMM_SIVEC     0x0C04   // SIU Interrupt Vector Register
+#define CYGARC_REG_IMM_SIPNR_H   0x0C08   // SIU Interrupt Pending Reg. High
+#define CYGARC_REG_IMM_SIPNR_L   0x0C0C   // SIU Interrupt Pending Reg. Low
+#define CYGARC_REG_IMM_SIPRR     0x0C10   // SIU Interrupt Priority Register
+#define CYGARC_REG_IMM_SCPRR_H   0x0C14   // CPM Interrupt Priority Reg. High
+#define CYGARC_REG_IMM_SCPRR_L   0x0C18   // CPM Interrupt Priority Reg. Low
+#define CYGARC_REG_IMM_SIMR_H    0x0C1C   // SIU Interrupt Mask Register High
+#define CYGARC_REG_IMM_SIMR_L    0x0C20   // SIU Interrupt Mask Register High
+#define CYGARC_REG_IMM_SIEXR     0x0C24   // SIU External Interrupt Ctrl Reg.
+
+// Parallel I/O (GPIO) 
+#define CYGARC_REG_IMM_PDIRA     0x0D00   // Port A data direction
+#define CYGARC_REG_IMM_PPARA     0x0D04   // Port A pin assignment
+#define CYGARC_REG_IMM_PSORA     0x0D08   // Port A special options
+#define CYGARC_REG_IMM_PODRA     0x0D0C   // Port A open drain
+#define CYGARC_REG_IMM_PDATA     0x0D10   // Port A data
+#define CYGARC_REG_IMM_PDIRB     0x0D20   // Port B data direction
+#define CYGARC_REG_IMM_PPARB     0x0D24   // Port B pin assignment
+#define CYGARC_REG_IMM_PSORB     0x0D28   // Port B special options
+#define CYGARC_REG_IMM_PODRB     0x0D2C   // Port A open drain
+#define CYGARC_REG_IMM_PDATB     0x0D30   // Port A data
+#define CYGARC_REG_IMM_PDIRC     0x0D40   // Port C data direction
+#define CYGARC_REG_IMM_PPARC     0x0D44   // Port C pin assignment
+#define CYGARC_REG_IMM_PSORC     0x0D48   // Port C special options
+#define CYGARC_REG_IMM_PODRC     0x0D4C   // Port A open drain
+#define CYGARC_REG_IMM_PDATC     0x0D50   // Port A data
+#define CYGARC_REG_IMM_PDIRD     0x0D60   // Port D data direction
+#define CYGARC_REG_IMM_PPARD     0x0D64   // Port D pin assignment
+#define CYGARC_REG_IMM_PSORD     0x0D68   // Port D special options
+#define CYGARC_REG_IMM_PODRD     0x0D6C   // Port A open drain
+#define CYGARC_REG_IMM_PDATD     0x0D70   // Port A data
+
+#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#define HID0       CYGARC_REG_HID0
+#define HID1       CYGARC_REG_HID1
+#define HID2       CYGARC_REG_HID2
+#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+
+//--------------------------------------------------------------------------
+#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+
+// BATs
+#define IBAT0U          528
+#define IBAT0L          529
+#define IBAT1U          530
+#define IBAT1L          531
+#define IBAT2U          532
+#define IBAT2L          533
+#define IBAT3U          534
+#define IBAT3L          535
+
+#define DBAT0U          536
+#define DBAT0L          537
+#define DBAT1U          538
+#define DBAT1L          539
+#define DBAT2U          540
+#define DBAT2L          541
+#define DBAT3U          542
+#define DBAT3L          543
+
+#define UBAT_BEPIMASK   0xfffe0000      // effective address mask
+#define UBAT_BLMASK     0x00001ffc      // block length mask
+#define UBAT_VS         0x00000002      // supervisor mode valid bit
+#define UBAT_VP         0x00000001      // problem mode valid bit
+
+#define LBAT_BRPNMASK   0xfffe0000      // real address mask
+#define LBAT_W          0x00000040      // write-through
+#define LBAT_I          0x00000020      // caching-inhibited
+#define LBAT_M          0x00000010      // memory coherence
+#define LBAT_G          0x00000008      // guarded
+
+#define LBAT_PP_NA      0x00000000      // no access
+#define LBAT_PP_RO      0x00000001      // read-only
+#define LBAT_PP_RW      0x00000002      // read/write
+
+
+#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+
+//-----------------------------------------------------------------------------
+#endif // ifdef CYGONCE_HAL_VAR_REGS_H
+// End of var_regs.h
Index: hal/powerpc/mpc8xxx/current/include/variant.inc
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/include/variant.inc
diff -N hal/powerpc/mpc8xxx/current/include/variant.inc
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/include/variant.inc	19 Aug 2003 16:48:00 -0000
@@ -0,0 +1,279 @@
+#ifndef CYGONCE_HAL_VARIANT_INC
+#define CYGONCE_HAL_VARIANT_INC
+##=============================================================================
+##
+##	variant.inc
+##
+##	MPC8xxx family assembler header file
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002, 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): 	pfine
+## Contributors:jskov, gthomas
+## Date:	2001-12-12
+## Purpose:	MPC8260 family definitions.
+## Description:	This file contains various definitions and macros that are
+##              useful for writing assembly code for the MPC8260 CPU family.
+## Usage:
+##		#include <cyg/hal/variant.inc>
+##		...
+##		
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <pkgconf/hal.h>
+	
+#include <cyg/hal/arch.inc>
+#include <cyg/hal/plf_regs.h>   // For CYGARC_IMM_BASE
+
+##-----------------------------------------------------------------------------
+#ifndef SPRG0
+#define SPRG0 272     # Counter Register
+#endif
+#ifndef SPRG1
+#define SPRG1 273     # Counter Register
+#endif
+#ifndef SPRG2
+#define SPRG2 274     # Counter Register
+#endif
+#ifndef SPRG3
+#define SPRG3 275     # Counter Register
+#endif
+
+##-----------------------------------------------------------------------------
+## MPC8260 defined vectors
+	.macro mpc8260_vector name
+        .p2align 8
+        .globl  __exception_\name
+__exception_\name:
+   	#-------------------------------------------#
+   	# save off registers used in vector routine #
+   	#-------------------------------------------#
+
+   	mtspr SPRG3,r3    # save r3
+   	mfspr r3,8
+   	mtspr SPRG2,r3    # save LR
+
+   	#-----------------------------------------------------------------------
+   	# Load the vector offset value in SPRG0 for handler shifted down 8 bits.
+   	#----------------------------------------------------------------------- 
+
+   	#addi  r3,r0,0x0010
+   	addi  r3,r0,__exception_\name@l #load low 16 bits of exception vector
+	srawi r3,r3,8                   #shift right by 8
+   	mtspr SPRG0,r3
+
+   	#---------------------------------------------------------
+   	# load link register in order to jump to physical address
+   	#---------------------------------------------------------
+
+   	addis    r3,0,handler@h    
+   	ori      r3,r3,handler@l
+   	mtspr    8,r3 
+   	bclr     20,0                 # jump unconditionally to address in Link 
+        	                      # Register (LR)
+	.endm
+
+//
+// This is for debugging purposes only
+//
+        .macro  infinite_loop_vector name
+        .p2align 8
+        .globl  __exception_\name
+__exception_\name:
+	mflr	r0
+	lwi	r1,CYGARC_IMMM_BASE
+	lwi	r2,0x12345678
+	stw	r0,0(r1)
+	lwi	r3,__exception_\name
+	stw	r3,4(r1)
+	stw	r2,8(r1)
+1:
+	nop
+	nop
+	nop
+	b 1b
+        .endm
+
+	.macro hal_reserved_vector_00000
+	infinite_loop_vector	reserved
+	.endm
+#define CYG_HAL_RESERVED_VECTOR_00000
+        
+        .macro hal_extra_vectors
+        infinite_loop_vector        itbl_miss
+        infinite_loop_vector        dltlb_miss
+        infinite_loop_vector        dstlb_miss
+        infinite_loop_vector        iaddr_brkpt
+        infinite_loop_vector        sys_mngmnt_intrpt
+        .endm
+
+##-----------------------------------------------------------------------------
+## MPC8xxx CPU initialization
+##
+## Initialize CPU to a post-reset state, ensuring the ground doesn''t
+## shift under us while we try to set things up.
+        
+        .macro hal_cpu_init
+        # Set up MSR (disable MMU for now)
+        lwi     r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
+        sync
+        mtmsr   r3
+        sync
+        .endm
+
+##-----------------------------------------------------------------------------
+## MPC8xxx monitor initialization
+
+#ifndef CYGPKG_HAL_PPC_MON_DEFINED
+
+#if     defined(CYG_HAL_STARTUP_ROM) ||                 \
+        defined(CYG_HAL_STARTUP_ROMRAM) ||                 \
+        (       defined(CYG_HAL_STARTUP_RAM) &&         \
+                !defined(CYGSEM_HAL_USE_ROM_MONITOR))
+
+        .macro  hal_mon_init
+#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
+        # If we are starting up from ROM and want vectors in RAM
+        # or we are starting in RAM and NOT using a ROM monitor,
+        # copy exception handler code to 0.
+        lwi     r3,rom_vectors          # r3 = rom start
+        lwi     r4,0                    # r4 = ram start
+        lwi     r5,rom_vectors_end      # r5 = rom end
+        cmplw   r3,r5                   # skip if no vectors
+        beq     2f
+
+        subi    r3,r3,4
+        subi    r4,r4,4
+        subi    r5,r5,4
+1:
+        lwzu    r0,4(r3)                # get word from ROM
+        stwu    r0,4(r4)                # store in RAM
+        cmplw   r3,r5                   # compare
+        blt     1b                      # loop if not yet done
+2:
+
+        # Next initialize the VSR table. This happens whether the
+        # vectors were copied to RAM or not.
+
+        # First fill with exception handlers
+        lwi     r3,cyg_hal_default_exception_vsr
+        lwi     r4,hal_vsr_table
+        subi    r4,r4,4
+        li      r5,CYGNUM_HAL_VSR_COUNT
+1:      stwu    r3,4(r4)
+        subi    r5,r5,1
+        cmpwi   r5,0
+        bne     1b
+#endif
+
+        # Then fill in the special vectors
+        lwi     r3,cyg_hal_default_interrupt_vsr
+        lwi     r4,hal_vsr_table
+        stw     r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
+        stw     r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
+        .endm
+
+#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
+
+        # Initialize the VSR table entries
+        # We only take control of the interrupt vectors,
+        # the rest are left to the ROM for now...
+
+        .macro  hal_mon_init
+        lwi     r3,cyg_hal_default_interrupt_vsr
+        lwi     r4,hal_vsr_table
+        stw     r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
+        stw     r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
+        .endm
+
+
+#else
+
+        .macro  hal_mon_init
+
+        .endm
+
+#endif
+
+
+#define CYGPKG_HAL_PPC_MON_DEFINED
+
+#endif // CYGPKG_HAL_PPC_MON_DEFINED
+
+##-----------------------------------------------------------------------------
+## MPC8xxx exception state handling
+        .macro	hal_variant_save regs
+        .endm
+
+        .macro	hal_variant_load regs
+        .endm
+
+##-----------------------------------------------------------------------------
+## Indicate that the ISR tables are defined in variant.S
+
+#define CYG_HAL_PPC_ISR_TABLES_DEFINED
+
+##-----------------------------------------------------------------------------
+## MPC8260 interrupt handling.
+
+#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED
+
+## First level decoding of MPC8xxx SIU interrupt controller.
+
+        # decode the interrupt
+	.macro  hal_intc_decode dreg,state
+        lwz     \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
+        rlwinm. \dreg,\dreg,22,31,31            # isolate bit 21
+        beq     0f                              # done if decrementer (vec 0)
+        lis     \dreg,(CYGARC_IMM_BASE+0x10000)>>16 # load register base
+        lbz     \dreg,CYGARC_REG_IMM_SIVEC(\dreg)      # if external, get SIU vector
+        srwi    \dreg,\dreg,2			# shift SIVEC value by 2
+	//addi    \dreg,\dreg,1                   # Skip decrementer vector
+0:      stw     \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
+        slwi    \dreg,\dreg,2                   # convert to byte offset.
+        .endm                              
+
+
+#define CYGPKG_HAL_POWERPC_INTC_DEFINED
+#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED
+#------------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_VARIANT_INC
+# end of variant.inc
Index: hal/powerpc/mpc8xxx/current/src/cpm.c
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/src/cpm.c
diff -N hal/powerpc/mpc8xxx/current/src/cpm.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/src/cpm.c	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,125 @@
+//==========================================================================
+//
+//      cpm.c
+//
+//      PowerPC QUICC2 support functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Gary Thomas 
+// Contributors: 
+// Date:         2003-03-04
+// Purpose:      Common support for the QUICC2/CPM
+// Description:  
+//               
+// Usage:
+// Notes:        
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_arch.h>
+#include <string.h>           // memset
+
+// eCos headers decribing PowerQUICC2:
+#include <cyg/hal/mpc8xxx.h>
+
+// Information about DPRAM usage
+// This lets the CPM/DPRAM information be shared by all environments
+//
+static struct dpram_info {
+    unsigned int offset, len;
+} CPM_DPRAM[] = {
+    { DPRAM_BD_OFFSET, 0x1000 },
+    { 0xB000, 0x1000 },
+    { 0, 0}
+};
+static int *nextBd = (int *)(CYGHWR_HAL_VSR_TABLE + 0x1F0);
+static struct dpram_info **info = (struct dpram_info **)(CYGHWR_HAL_VSR_TABLE + 0x1F4);
+
+/*
+ * Reset the communications processor
+ */
+
+void
+_mpc8xxx_reset_cpm(void)
+{
+    static int init_done = 0;
+
+    if (init_done) return;
+    init_done++;
+
+    IMM->cpm_cpcr = CPCR_RST | CPCR_FLG;
+    while (IMM->cpm_cpcr & CPCR_FLG)
+        CYG_EMPTY_STATEMENT;
+
+    *nextBd = CPM_DPRAM[0].offset;
+    *info = CPM_DPRAM;
+    // Set up SMCx offsets
+    IMM->pram.standard.smc1 = DPRAM_SMC1_OFFSET;
+    IMM->pram.standard.smc2 = DPRAM_SMC2_OFFSET;
+}
+
+//
+// Allocate a chunk of memory in the shared CPM memory, typically
+// used for buffer descriptors, etc.  The length will be aligned
+// to a multiple of 8 bytes.  This is somewhat complicated on the 
+// QUICC2/CPM since there are multiple regions of shared DPRAM
+// which are legal to use, of varying size and spread all over.
+//
+unsigned int
+_mpc8xxx_allocBd(int len)
+{
+    struct dpram_info *ip = *info;
+    unsigned int bd;
+
+    bd = *nextBd;
+    len = (len + 7) & ~7;  // Multiple of 8 bytes
+    *nextBd += len;
+    if (*nextBd >= (ip->offset+ip->len)) {
+        ip++;
+        *nextBd = ip->offset;
+        *info = ip;
+    }
+    return bd;
+}
+
+// EOF cpm.c
Index: hal/powerpc/mpc8xxx/current/src/quicc2_diag.c
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/src/quicc2_diag.c
diff -N hal/powerpc/mpc8xxx/current/src/quicc2_diag.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/src/quicc2_diag.c	19 Aug 2003 16:49:28 -0000
@@ -0,0 +1,573 @@
+//=============================================================================
+//
+//      quicc2_diag.c
+//
+//      HAL diagnostic I/O support routines for MPC8xxx/QUICC2
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   hmt
+// Contributors:hmt, gthomas
+// Date:        1999-06-08
+// Purpose:     HAL diagnostics I/O support
+// Description: 
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_mem.h>            // HAL memory definitions
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>             // hal_if_init
+#include <cyg/hal/hal_io.h>             // hal_if_init
+#include <cyg/hal/hal_misc.h>           // cyg_hal_is_break
+
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/mpc8xxx.h>            // Needed for IMMR structure
+
+struct cp_bufdesc {
+    volatile unsigned short ctrl;	/* status/control register */
+    volatile unsigned short length;	/* buffer length */
+    volatile char  	    *buffer;	/* buffer pointer */
+};
+
+// Buffer descriptor control bits
+#define _BD_CTL_Ready          0x8000  // Buffer contains data (tx) or is empty (rx)
+#define _BD_CTL_Wrap           0x2000  // Last buffer in list
+#define _BD_CTL_Int            0x1000  // Generate interrupt when empty (tx) or full (rx)
+#define _BD_CTL_Last           0x0800  // Last buffer in a sequence
+#define _BD_CTL_MASK           0xB000  // User settable bits
+
+#define SCCE_Rx 0x0001                 // Rx buffer interrupt
+#define SMCE_Rx 0x0001                 // Rx buffer interrupt
+
+#define PORT_IS_SMC 1
+#define PORT_IS_SCC 0
+
+#define NUM(t) sizeof(t)/sizeof(t[0])
+
+struct port_info {
+    short                             Txnum;   // Number of Tx buffers
+    short                             Rxnum;   // Number of Rx buffers
+    short                             intnum;  // Interrupt bit
+    short                             is_smc;  // 1 => SMC, 0=> SCC
+    int                               cpm_page;
+    int                               timeout; // Timeout in msec
+    int                               pram;    // [Pointer] to PRAM data
+    int                               regs;    // [Pointer] to control registers
+    int                               brg;     // Baud rate generator
+    volatile struct cp_bufdesc *next_rxbd;
+    int                               irq_state;// Interrupt state
+    int                               init;    // Has port been initialized?
+};
+
+static struct port_info ports[] = {
+#if CYGNUM_HAL_MPC8XXX_SMC1 > 0
+    { 1, 4, CYGNUM_HAL_INTERRUPT_SMC1, PORT_IS_SMC, SMC1_PAGE_SUBBLOCK, 1000,
+      DPRAM_SMC1_OFFSET,
+      (int)&((t_PQ2IMM *)0)->smc_regs[SMC1],
+      (int)&((t_PQ2IMM *)0)->brgs_brgc7
+    }, 
+#endif
+#if CYGNUM_HAL_MPC8XXX_SCC1 > 0
+    { 1, 4, CYGNUM_HAL_INTERRUPT_SCC1, PORT_IS_SCC, SCC1_PAGE_SUBBLOCK, 1000,
+      (int)&((t_PQ2IMM *)0)->pram.serials.scc_pram[SCC1],
+      (int)&((t_PQ2IMM *)0)->scc_regs[SCC1],
+      (int)&((t_PQ2IMM *)0)->brgs_brgc1
+    }, 
+#endif
+};
+
+// For Baud Rate Calculation, see MPC8260 PowerQUICC II User's Manual
+// 16.3 UART Baud Rate Examples, page 16-5.
+#define UART_BIT_RATE(n) \
+    (((int)(((CYGHWR_HAL_POWERPC_CPM_SPEED*2)*1000000)/16))/(n * 16))
+#define UART_BAUD_RATE CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
+
+
+// Function prototypes
+static cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data);
+static cyg_bool  cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch);
+static cyg_bool  cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch);
+static void      cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch);
+static void      cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                                          cyg_uint32 __len);
+static void      cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len);
+static void      cyg_hal_plf_smcx_init_channel(struct port_info *info, int page);
+static void      cyg_hal_plf_sccx_init_channel(struct port_info *info, int page);
+static int       cyg_hal_plf_smcx_isr(void *__ch_data, int* __ctrlc, 
+                                      CYG_ADDRWORD __vector, CYG_ADDRWORD __data);
+static int       cyg_hal_plf_sccx_isr(void *__ch_data, int* __ctrlc, 
+                                      CYG_ADDRWORD __vector, CYG_ADDRWORD __data);
+static int       cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...);
+
+static int       
+cyg_hal_plf_sccx_isr(void *__ch_data, int* __ctrlc, 
+                     CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    struct port_info *info = (struct port_info *)__ch_data;
+    volatile struct scc_regs_8260 *regs = (volatile struct scc_regs_8260*)((char *)IMM + info->regs);
+    volatile t_Scc_Pram *pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
+    char ch;
+    int res = 0;
+    volatile struct cp_bufdesc *bd;
+
+    *__ctrlc = 0;
+    if (regs->scce & SCCE_Rx) {
+        regs->scce = SMCE_Rx;
+
+        /* rx buffer descriptors */
+        bd = info->next_rxbd;
+
+        if ((bd->ctrl & _BD_CTL_Ready) == 0) {
+            
+            // then there be a character waiting
+            ch = bd->buffer[0];
+            bd->length = 1;
+            bd->ctrl   |= _BD_CTL_Ready | _BD_CTL_Int;
+            if (bd->ctrl & _BD_CTL_Wrap) {
+                bd = (struct cp_bufdesc *)((char *)IMM + pram->rbase);
+            } else {
+                bd++;
+            }
+            info->next_rxbd = bd;
+        
+            if( cyg_hal_is_break( &ch , 1 ) )
+                *__ctrlc = 1;
+        }
+
+        // Interrupt handled. Acknowledge it.
+        HAL_INTERRUPT_ACKNOWLEDGE(info->intnum);
+        res = CYG_ISR_HANDLED;
+    }
+    return res;
+}
+
+static int       
+cyg_hal_plf_smcx_isr(void *__ch_data, int* __ctrlc, 
+                     CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    struct port_info *info = (struct port_info *)__ch_data;
+    volatile struct smc_regs_8260 *regs = (volatile struct smc_regs_8260*)((char *)IMM + info->regs);
+    t_Smc_Pram *pram = (t_Smc_Pram *)((char *)IMM + info->pram);
+    char ch;
+    int res = 0;
+    volatile struct cp_bufdesc *bd;
+
+    *__ctrlc = 0;
+    if (regs->smc_smce & SMCE_Rx) {
+        regs->smc_smce = SMCE_Rx;
+
+        /* rx buffer descriptors */
+        bd = info->next_rxbd;
+
+        if ((bd->ctrl & _BD_CTL_Ready) == 0) {
+            
+            // then there be a character waiting
+            ch = bd->buffer[0];
+            bd->length = 1;
+            bd->ctrl   |= _BD_CTL_Ready | _BD_CTL_Int;
+            if (bd->ctrl & _BD_CTL_Wrap) {
+                bd = (struct cp_bufdesc *)((char *)IMM + pram->rbase);
+            } else {
+                bd++;
+            }
+            info->next_rxbd = bd;
+        
+            if( cyg_hal_is_break( &ch , 1 ) )
+                *__ctrlc = 1;
+        }
+
+        // Interrupt handled. Acknowledge it.
+        HAL_INTERRUPT_ACKNOWLEDGE(info->intnum);
+        res = CYG_ISR_HANDLED;
+    }
+    return res;
+}
+
+/* Early initialization of comm channels.
+ */
+void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+    int chan = 0;
+    struct port_info *port;
+    static int init = 0;
+
+    if (init) return;
+    init++;
+
+    // Setup procs in the vector table    
+    for (port = ports, chan = 0;  chan < NUM(ports);  chan++, port++) {        
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, port);
+        CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+        if (port->is_smc) {
+            cyg_hal_plf_smcx_init_channel(port, port->cpm_page);
+            CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_smcx_isr);
+        } else {
+            cyg_hal_plf_sccx_init_channel(port, port->cpm_page);
+            CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_sccx_isr);
+        }
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+static void
+cyg_hal_plf_sccx_init_channel(struct port_info *info, int cpm_page)
+{
+    unsigned int rxbase, txbase;
+    int i;
+    struct cp_bufdesc *rxbd, *txbd;
+    volatile struct scc_regs_8260 *regs = (volatile struct scc_regs_8260*)((char *)IMM + info->regs);
+    volatile t_Scc_Pram *pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
+
+    if (info->init) return;
+    info->init = 1;
+
+    // Make sure device is stopped
+    regs->gsmr_l &= DISABLE_TX_RX;
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+    IMM->cpm_cpcr = cpm_page |
+        CPCR_STOP_TX |
+        CPCR_FLG;             /* ISSUE COMMAND */
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+
+    // Allocate buffer descriptors + buffers (adjacent to descriptors)
+    rxbase = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+    txbase = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+
+    // setup RX buffer descriptors 
+    rxbd = (struct cp_bufdesc *)((char *)IMM + rxbase);
+    info->next_rxbd = rxbd;
+    for (i = 0;  i < info->Rxnum;  i++) {
+        rxbd->length = 0;
+        rxbd->buffer = ((char *)IMM + (rxbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
+        rxbd->ctrl   = _BD_CTL_Ready | _BD_CTL_Int;
+        rxbd++;
+    }
+    rxbd--;
+    rxbd->ctrl   |= _BD_CTL_Wrap;
+
+    // setup TX buffer descriptor
+    txbd = (struct cp_bufdesc *)((char *)IMM + txbase);
+    txbd->length = 1;
+    txbd->buffer = ((char *)IMM + (txbase+(info->Txnum*sizeof(struct cp_bufdesc))));
+    txbd->ctrl   = _BD_CTL_Wrap;
+
+    // Set the baud rate generator.  Note: on the MPC8xxx, 
+    // there are a number of BRGs, but the usage/layout is
+    // somewhat restricted, so we rely on a fixed mapping.
+    // See the setup in the platform init code for details.
+    *(unsigned long *)((char *)IMM + info->brg) = 0x00010000 | (UART_BIT_RATE(UART_BAUD_RATE) << 1);
+
+    // Rx, Tx function codes (used for access)
+    pram->rfcr = 0x18;
+    pram->tfcr = 0x18;
+    regs->psmr = 0xB000;
+
+    // Pointers to Rx & Tx buffer descriptor rings
+    pram->rbase = rxbase;
+    pram->tbase = txbase;
+
+    // Max receive buffer length
+    pram->mrblr = 1;
+   
+    // Mode register for 8N1
+    regs->gsmr_h = 0x00000060;
+    regs->gsmr_l = 0x00028004;  
+
+    // Clear events
+    regs->scce = ALL_ONES;
+    regs->sccm = SCCE_Rx;
+
+    // Init channel
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+    IMM->cpm_cpcr = cpm_page | 
+        CPCR_INIT_TX_RX_PARAMS |
+        CPCR_FLG;                 /* ISSUE COMMAND */
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+
+    /*-------------------------------------------------------------*/
+    /* Set the ENT/ENR bits in the GSMR -- Enable Transmit/Receive */
+    /*-------------------------------------------------------------*/
+
+    regs->gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR;
+#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
+    || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
+    // Fill out the control Character Table.  Make the first entry 
+    // an end of table line. 
+    // cc[0] = 0x4003 ==> reject if char = 0x3, write to RCCR
+    pram->SpecificProtocol.u.cc[0] = 0x4003;
+    {
+        int i;
+        for (i = 0; i < 8; i++){
+            pram->SpecificProtocol.u.cc[i] = 0x8000;
+        }
+    }
+    
+    pram->SpecificProtocol.u.rccm  = 0xc000;
+#endif
+}
+
+static void
+cyg_hal_plf_smcx_init_channel(struct port_info *info, int cpm_page)
+{
+    unsigned int rxbase, txbase;
+    int i;
+    struct cp_bufdesc *rxbd, *txbd;
+    volatile struct smc_regs_8260 *regs = (volatile struct smc_regs_8260*)((char *)IMM + info->regs);
+    t_Smc_Pram *uart_pram = (t_Smc_Pram *)((char *)IMM + info->pram);
+
+    if (info->init) return;
+    info->init = 1;
+
+    // Make sure device is stopped
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+    IMM->cpm_cpcr = cpm_page |
+        CPCR_STOP_TX |
+        CPCR_FLG;             /* ISSUE COMMAND */
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+
+    // Allocate buffer descriptors + buffers (adjacent to descriptors)
+    rxbase = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+    txbase = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
+
+    // setup RX buffer descriptors 
+    rxbd = (struct cp_bufdesc *)((char *)IMM + rxbase);
+    info->next_rxbd = rxbd;
+    for (i = 0;  i < info->Rxnum;  i++) {
+        rxbd->length = 0;
+        rxbd->buffer = ((char *)IMM + (rxbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
+        rxbd->ctrl   = _BD_CTL_Ready | _BD_CTL_Int;
+        rxbd++;
+    }
+    rxbd--;
+    rxbd->ctrl   |= _BD_CTL_Wrap;
+
+    // setup TX buffer descriptor
+    txbd = (struct cp_bufdesc *)((char *)IMM + txbase);
+    txbd->length = 1;
+    txbd->buffer = ((char *)IMM + (txbase+(info->Txnum*sizeof(struct cp_bufdesc))));
+    txbd->ctrl   = _BD_CTL_Wrap;
+
+    // Set the baud rate generator.  Note: on the MPC8xxx, 
+    // there are a number of BRGs, but the usage/layout is
+    // somewhat restricted, so we rely on a fixed mapping.
+    // See the setup in the platform init code for details.
+    *(unsigned long *)((char *)IMM + info->brg) = 0x00010000 | (UART_BIT_RATE(UART_BAUD_RATE) << 1);
+
+    // Rx, Tx function codes (used for access)
+    uart_pram->rfcr = 0x18;
+    uart_pram->tfcr = 0x18;
+
+    // Pointers to Rx & Tx buffer descriptor rings
+    uart_pram->rbase = rxbase;
+    uart_pram->tbase = txbase;
+
+    // Max receive buffer length
+    uart_pram->mrblr = 1;
+   
+    // Mode register for 8N1
+    regs->smc_smcmr = 0x4823;
+
+    // Clear events
+    regs->smc_smce = 0xFFFF;
+    regs->smc_smcm = SMCE_Rx;
+
+    // Init channel
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+    IMM->cpm_cpcr = cpm_page | 
+        CPCR_INIT_TX_RX_PARAMS |
+        CPCR_FLG;                 /* ISSUE COMMAND */
+    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
+}
+
+static void
+cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch)
+{
+    volatile struct cp_bufdesc *bd;
+    struct port_info *info = (struct port_info *)__ch_data;
+    volatile t_Scc_Pram *uart_pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
+//    int cache_state;
+
+    /* tx buffer descriptor */
+    bd = (struct cp_bufdesc *)((char *)IMM + uart_pram->tbptr);
+    while (bd->ctrl & _BD_CTL_Ready) ;  // Wait for buffer free
+    if (bd->ctrl & _BD_CTL_Int) {
+        // This buffer has just completed interrupt output.  Reset bits
+        bd->ctrl &= ~_BD_CTL_Int;
+    }
+    bd->length = 1;
+    bd->buffer[0] = ch;
+    bd->ctrl      |= _BD_CTL_Ready;
+#if 0 //??
+    // Flush cache if necessary - buffer may be in cacheable memory
+    HAL_DCACHE_IS_ENABLED(cache_state);
+    if (cache_state) {
+      HAL_DCACHE_FLUSH(bd->buffer, 1);
+    }
+#endif
+
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    volatile struct cp_bufdesc *bd;
+    struct port_info *info = (struct port_info *)__ch_data;
+    volatile t_Scc_Pram *uart_pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
+//    int cache_state;
+
+    /* rx buffer descriptor */
+    bd = info->next_rxbd;
+
+    if (bd->ctrl & _BD_CTL_Ready)
+        return false;
+
+    *ch = bd->buffer[0];
+
+    bd->length = 0;
+    bd->buffer[0] = '\0';
+    bd->ctrl |= _BD_CTL_Ready;
+    if (bd->ctrl & _BD_CTL_Wrap) {
+        bd = (struct cp_bufdesc *)((char *)IMM + uart_pram->rbase);
+    } else {
+        bd++;
+    }
+    info->next_rxbd = bd;
+
+#if 0
+    // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
+    HAL_DCACHE_IS_ENABLED(cache_state);
+    if (cache_state) {
+        HAL_DCACHE_INVALIDATE(bd->buffer, uart_pram->mrblr);  // Make sure no stale data
+    }
+#endif
+    return true;
+}
+
+static cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+    return ch;
+}
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+}
+
+cyg_int32 msec_timeout = 1000;
+
+static cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count = msec_timeout * 10; // delay in .1 ms steps
+    cyg_bool res;
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    int ret = 0;
+    struct port_info *info = (struct port_info *)__ch_data;
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        HAL_INTERRUPT_UNMASK(info->intnum);
+        info->irq_state = 1;
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = info->irq_state;
+        info->irq_state = 0;
+        HAL_INTERRUPT_MASK(info->intnum);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = info->intnum;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+        va_start(ap, __func);
+
+        ret = msec_timeout;
+        msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    default:
+        break;
+    }
+    return ret;
+}
+
+// EOF hal_aux.c
Index: hal/powerpc/mpc8xxx/current/src/var_intr.c
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/src/var_intr.c
diff -N hal/powerpc/mpc8xxx/current/src/var_intr.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/src/var_intr.c	19 Aug 2003 16:49:56 -0000
@@ -0,0 +1,74 @@
+//==========================================================================
+//
+//      var_intr.c
+//
+//      PowerPC variant interrupt handlers
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    pfine
+// Contributors: jskov, gthomas
+// Date:         2001-12-11
+// Purpose:      PowerPC variant interrupt handlers
+// Description:  This file contains code to handle interrupt related issues
+//               on the PowerPC variant.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_mem.h>            // HAL memory definitions
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/mpc8xxx.h>            // For IMM structures
+#include <cyg/hal/hal_if.h>
+
+externC void
+hal_variant_IRQ_init(void)
+{
+    // Clear any pending interrupts & reset masks
+    IMM->ic_simr_h = 0;
+    IMM->ic_simr_l = 0;
+    IMM->ic_sipnr_h = 0xFFFFFFFF;
+    IMM->ic_sipnr_l = 0xFFFFFFFF;
+}
+
+// -------------------------------------------------------------------------
+// EOF var_intr.c
Index: hal/powerpc/mpc8xxx/current/src/var_misc.c
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/src/var_misc.c
diff -N hal/powerpc/mpc8xxx/current/src/var_misc.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/src/var_misc.c	19 Aug 2003 16:50:31 -0000
@@ -0,0 +1,187 @@
+//==========================================================================
+//
+//      var_misc.c
+//
+//      HAL implementation miscellaneous functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    pfine
+// Contributors: jskov, gthomas
+// Date:         2001-12-12
+// Purpose:      HAL miscellaneous functions
+// Description:  This file contains miscellaneous functions provided by the
+//               HAL.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#include <cyg/hal/ppc_regs.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_mem.h>
+#include <cyg/hal/mpc8xxx.h>
+
+volatile t_PQ2IMM  *IMM;   /* IMM base pointer */
+
+//--------------------------------------------------------------------------
+void hal_variant_init(void)
+{
+    IMM =  (t_PQ2IMM *)CYGARC_IMM_BASE;  /* MPC8xxx internal register map  */
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
+    // Reset CPM
+    _mpc8xxx_reset_cpm();
+#endif
+}
+
+
+//--------------------------------------------------------------------------
+// Variant specific idle thread action.
+bool
+hal_variant_idle_thread_action( cyg_uint32 count )
+{
+    // Let architecture idle thread action run
+    return true;
+}
+
+//---------------------------------------------------------------------------
+// Use MMU resources to map memory regions.  
+// Takes and returns an int used to ID the MMU resource to use. This ID
+// is increased as resources are used and should be used for subsequent
+// invocations.
+int
+cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, 
+                    cyg_int32 size, cyg_uint8 flags)
+{
+    // Use BATs to map the memory.
+    cyg_uint32 ubat, lbat;
+
+    ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP;
+    lbat = (phys & LBAT_BRPNMASK);
+    if (flags & CYGARC_MEMDESC_CI) 
+        lbat |= LBAT_I;
+    if (flags & CYGARC_MEMDESC_GUARDED) 
+        lbat |= LBAT_G;
+#define IWASPATRICK
+#ifdef IWASPATRICK
+    lbat |= LBAT_PP_RW; // Always enable for Read-Write
+#else
+    if (flags & CYGARC_MEMDESC_RO) // Memory is Read Only
+        lbat |= LBAT_PP_RO;
+    if (flags & CYGARC_MEMDESC_RW) // Memory is RW 
+        lbat |= LBAT_PP_RW;
+#endif
+    // There are 4 BATs, size is programmable.
+    while (id < 4 && size > 0) {
+        cyg_uint32 blk_size = 128*1024;
+        cyg_uint32 bl = 0;
+        while (blk_size < 256*1024*1024 && blk_size < size) {
+            blk_size *= 2;
+            bl = (bl << 1) | 1;
+        }
+        ubat = (ubat & ~UBAT_BLMASK) | (bl << 2);
+        
+        switch (id) {
+        case 0:
+            CYGARC_MTSPR (IBAT0U, ubat);
+            CYGARC_MTSPR (IBAT0L, lbat);
+            CYGARC_MTSPR (DBAT0U, ubat);
+            CYGARC_MTSPR (DBAT0L, lbat);
+            break;
+        case 1:
+            CYGARC_MTSPR (IBAT1U, ubat);
+            CYGARC_MTSPR (IBAT1L, lbat);
+            CYGARC_MTSPR (DBAT1U, ubat);
+            CYGARC_MTSPR (DBAT1L, lbat);
+            break;
+        case 2:
+            CYGARC_MTSPR (IBAT2U, ubat);
+            CYGARC_MTSPR (IBAT2L, lbat);
+            CYGARC_MTSPR (DBAT2U, ubat);
+            CYGARC_MTSPR (DBAT2L, lbat);
+            break;
+        case 3:
+            CYGARC_MTSPR (IBAT3U, ubat);
+            CYGARC_MTSPR (IBAT3L, lbat);
+            CYGARC_MTSPR (DBAT3U, ubat);
+            CYGARC_MTSPR (DBAT3L, lbat);
+            break;
+        }
+        
+        size -= blk_size;
+        id++;
+    }
+
+    return id;
+}
+
+
+// Initialize MMU to a sane (NOP) state.
+void
+cyg_hal_clear_MMU (void)
+{
+    cyg_uint32 ubat, lbat;
+        
+    // Initialize BATs with 0 -- VS&VP are unset, making all matches fail
+    ubat = 0;
+    lbat = 0;
+
+    CYGARC_MTSPR (IBAT0U, ubat);
+    CYGARC_MTSPR (IBAT0L, lbat);
+    CYGARC_MTSPR (DBAT0U, ubat);
+    CYGARC_MTSPR (DBAT0L, lbat);
+    CYGARC_MTSPR (IBAT1U, ubat);
+    CYGARC_MTSPR (IBAT1L, lbat);
+    CYGARC_MTSPR (DBAT1U, ubat);
+    CYGARC_MTSPR (DBAT1L, lbat);
+    CYGARC_MTSPR (IBAT2U, ubat);
+    CYGARC_MTSPR (IBAT2L, lbat);
+    CYGARC_MTSPR (DBAT2U, ubat);
+    CYGARC_MTSPR (DBAT2L, lbat);
+    CYGARC_MTSPR (IBAT3U, ubat);
+    CYGARC_MTSPR (IBAT3L, lbat);
+    CYGARC_MTSPR (DBAT3U, ubat);
+    CYGARC_MTSPR (DBAT3L, lbat);
+}
+
+//--------------------------------------------------------------------------
+// End of var_misc.c
Index: hal/powerpc/mpc8xxx/current/src/variant.S
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/src/variant.S
diff -N hal/powerpc/mpc8xxx/current/src/variant.S
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/src/variant.S	19 Aug 2003 16:51:11 -0000
@@ -0,0 +1,87 @@
+##=============================================================================
+##
+##	variant.S
+##
+##	PowerPC MPC8xxx variant code
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002, 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): 	pfine
+## Contributors:jskov
+## Date:	2001-12-12
+## Purpose:	PowerPC MPC8xxx variant code
+## Description:	Variant specific code for PowerPC MPC8xxx CPUs.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <cyg/hal/variant.inc>
+
+#---------------------------------------------------------------------------
+# Interrupt vector tables.
+# These tables contain the isr, data and object pointers used to deliver
+# interrupts to user code.
+
+        .data
+
+        .extern hal_default_decrementer_isr
+        .extern hal_default_isr
+
+        .globl  hal_interrupt_handlers
+hal_interrupt_handlers:
+        .long   hal_default_decrementer_isr
+        .rept   CYGNUM_HAL_ISR_COUNT-1
+        .long   hal_default_isr
+        .endr
+
+        .globl  hal_interrupt_data
+hal_interrupt_data:
+        .rept   CYGNUM_HAL_ISR_COUNT
+        .long   0
+        .endr
+
+        .globl  hal_interrupt_objects
+hal_interrupt_objects:
+        .rept   CYGNUM_HAL_ISR_COUNT
+        .long   0
+        .endr
+
+##-----------------------------------------------------------------------------
+## end of variant.S
+	
Index: hal/powerpc/rattler/current/ChangeLog
===================================================================
RCS file: hal/powerpc/rattler/current/ChangeLog
diff -N hal/powerpc/rattler/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/ChangeLog	19 Aug 2003 16:56:36 -0000
@@ -0,0 +1,62 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/redboot_linux_exec.c: 
+	* src/rattler.S: 
+	* src/hal_diag.c: 
+	* src/hal_aux.c: 
+	* misc/redboot_ROMRAM.ecm: 
+	* misc/redboot_ROMRAM+PCI.ecm: 
+	* misc/redboot_ROM.ecm: 
+	* misc/redboot_RAM.ecm: 
+	* include/pkgconf/mlt_powerpc_rattler_romram.mlt: 
+	* include/pkgconf/mlt_powerpc_rattler_romram.ldi: 
+	* include/pkgconf/mlt_powerpc_rattler_romram.h: 
+	* include/pkgconf/mlt_powerpc_rattler_rom.mlt: 
+	* include/pkgconf/mlt_powerpc_rattler_rom.ldi: 
+	* include/pkgconf/mlt_powerpc_rattler_rom.h: 
+	* include/pkgconf/mlt_powerpc_rattler_ram.mlt: 
+	* include/pkgconf/mlt_powerpc_rattler_ram.ldi: 
+	* include/pkgconf/mlt_powerpc_rattler_ram.h: 
+	* include/plf_stub.h: 
+	* include/plf_regs.h: 
+	* include/plf_intr.h: 
+	* include/plf_cache.h: 
+	* include/hal_diag.h: 
+	* cdl/hal_powerpc_rattler.cdl: New file(s) - platform HAL for
+	Analogue & Micro Rattler (Motorola MPC8250)
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/powerpc/rattler/current/cdl/hal_powerpc_rattler.cdl
===================================================================
RCS file: hal/powerpc/rattler/current/cdl/hal_powerpc_rattler.cdl
diff -N hal/powerpc/rattler/current/cdl/hal_powerpc_rattler.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/cdl/hal_powerpc_rattler.cdl	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,383 @@
+# ====================================================================
+#
+#      hal_powerpc_rattler.cdl
+#
+#      Analogue & Micro Rattler (MPC8250) HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  hmt
+# Contributors:
+# Date:           2003-06-30
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_POWERPC_RATTLER {
+    display       "Analogue & Micro Rattler board"
+    parent        CYGPKG_HAL_POWERPC
+    requires      CYGPKG_HAL_POWERPC_MPC8XXX
+    define_header hal_powerpc_rattler.h
+    include_dir   cyg/hal
+    description   "
+        The RATTLER HAL package provides the support needed to run
+        eCos on an Analogue & Micro Rattler board."
+
+    compile       hal_diag.c hal_aux.c rattler.S
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    requires      CYGSEM_HAL_POWERPC_RESET_USES_JUMP        
+
+    implements    CYGNUM_HAL_MPC8XXX_SCC1
+    implements    CYGNUM_HAL_MPC8XXX_SMC1
+
+# Note: uncomment this to get old-style debug behaviour
+#   implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_powerpc_mpc8xxx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_rattler.h>"
+
+	puts $::cdl_header "#define HAL_PLATFORM_CPU    \"PowerPC MPC8250\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Rattler\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        legal_values  { "RAM" "ROM" "ROMRAM" }
+        default_value { "RAM" }
+	no_define
+	define -file system.h CYG_HAL_STARTUP
+        description   "
+           This option is used to control where the application program will
+           run, either from RAM or ROM (flash) memory.  ROM based applications
+           must be self contained, while RAM applications will typically assume
+           the existence of a debug environment, such as GDB stubs."
+    }
+
+    cdl_option CYGHWR_HAL_POWERPC_DISABLE_MMU {
+        display       "DISABLE MMU"
+        flavor        bool
+        default_value 0
+	#        calculated    1
+        description   "
+            This option will disable the MMU enabled."
+    }
+
+    cdl_option CYGHWR_HAL_POWERPC_BUS_SPEED {
+        display          "Development board clock speed (MHz)"
+        flavor           data
+        legal_values     66
+        default_value    66
+        description      "
+	   The Rattler currently only runs at 66MHz"
+    }
+ 
+    cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
+        display          "Development board clock speed (MHz)"
+        flavor           data
+        legal_values     200
+        default_value    200
+        description      "
+	   The Rattler is configured to run the CPU at 3.5x"           
+    }
+
+    cdl_option CYGHWR_HAL_POWERPC_CPM_SPEED {
+        display          "Development board clock speed (MHz)"
+        flavor           data
+        legal_values     166 133
+        default_value    { (CYGHWR_HAL_POWERPC_RATTLER_PCI == 0) ? 166 : 133 }
+        description      "
+	   The Rattler is configured to run the CPM at 2.5x
+           This clock is used by the baud rate generators"
+    }
+
+    cdl_option CYGHWR_HAL_POWERPC_RATTLER_PCI {
+        display          "Rattler with PCI (agent) support"
+        flavor           bool
+        default_value    0
+        description      "
+	   The Rattler comes in two variants - one with PCI
+           and another without."
+    }
+
+    # Real-time clock/counter specifics
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants."
+        description   "
+            Period is busclock/4/CYGNUM_HAL_RTC_DENOMINATOR.  VERIFY THIS!!!"
+        flavor        none
+        no_define
+    
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            calculated    1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+            description   "
+              This option selects the number of system clock 'ticks'
+              per second.  This rate is sometimes known as the heartbeat rate."
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            calculated    { (((CYGHWR_HAL_POWERPC_BUS_SPEED*1000000)/4)/CYGNUM_HAL_RTC_DENOMINATOR) }
+        }
+    }
+    
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+        parent  CYGPKG_NONE
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "powerpc-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-msoft-float -mcpu=603e -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by
+                default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-msoft-float -mcpu=603e -g -nostdlib -Wl,--gc-sections -Wl,-static" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+
+        cdl_option CYGBLD_BUILD_GDB_STUBS {
+            display "Build GDB stub ROM image"
+            default_value 0
+            requires { (CYG_HAL_STARTUP == "ROM") || (CYG_HAL_STARTUP == "ROMRAM") }
+            requires CYGSEM_HAL_ROM_MONITOR
+            requires CYGBLD_BUILD_COMMON_GDB_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+            no_define
+            description "
+                This option enables the building of the GDB stubs for the
+                board. The common HAL controls takes care of most of the
+                build process, but the platform CDL takes care of creating
+                an S-Record data file. -- This needs more work"
+
+            make -priority 320 {
+                <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec --srec-forceS3 $< $(@:.bin=.s19)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_HAL_POWERPC_RATTLER_OPTIONS {
+        display "MPC8260 RATTLER build options"
+        flavor  none
+        description   "
+	    Package specific build options including control over
+	    compiler flags used only in building this package,
+	    and details of which tests are built."
+
+
+        cdl_option CYGPKG_HAL_POWERPC_RATTLER_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the RATTLER HAL. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_POWERPC_RATTLER_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the RATTLER HAL. These flags are removed from
+                the set of global flags if present."
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_rattler_ram" : \
+                     CYG_HAL_STARTUP == "ROM" ? "powerpc_rattler_rom" : \
+                                                "powerpc_rattler_romram" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { CYG_HAL_STARTUP == "RAM"          ? "<pkgconf/mlt_powerpc_rattler_ram.ldi>"     : \
+                         CYG_HAL_STARTUP == "ROM"          ? "<pkgconf/mlt_powerpc_rattler_rom.ldi>"     : \
+							     "<pkgconf/mlt_powerpc_rattler_romram.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { CYG_HAL_STARTUP == "RAM"          ? "<pkgconf/mlt_powerpc_rattler_ram.h>"     : \
+                         CYG_HAL_STARTUP == "ROM"          ? "<pkgconf/mlt_powerpc_rattler_rom.h>"     : \
+							     "<pkgconf/mlt_powerpc_rattler_romram.h>" }
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { (CYG_HAL_STARTUP == "ROM") || (CYG_HAL_STARTUP == "ROMRAM") }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        bool
+        default_value { (CYG_HAL_STARTUP == "RAM" &&
+                        !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS &&
+                        !CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED &&
+                        !CYGSEM_HAL_POWERPC_COPY_VECTORS) ? 1 : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        requires      ! CYGSEM_HAL_POWERPC_COPY_VECTORS
+        requires      ! CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        requires      ! CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED
+        description   "
+            Allow coexistence with ROM monitor (CygMon or GDB stubs) by
+            only initializing interrupt vectors on startup, thus leaving
+            exception handling to the ROM monitor."
+    }
+
+
+    # FIXME: the option above should be adjusted to select between monitor
+    #        variants
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs {
+        parent        CYGPKG_HAL_ROM_MONITOR
+        display "Bad CDL workaround"
+        calculated 1
+        active_if CYGSEM_HAL_USE_ROM_MONITOR
+    }
+
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGSEM_REDBOOT_HAL_LINUX_BOOT {
+            active_if      CYGBLD_BUILD_REDBOOT_WITH_EXEC
+            display        "Support booting Linux via RedBoot"
+            flavor         bool
+            default_value  1
+            description    "
+               This option enables RedBoot to support booting of a Linux kernel."
+
+            compile -library=libextras.a redboot_linux_exec.c
+        }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming.
+			 This needs more work."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+}
Index: hal/powerpc/rattler/current/include/hal_diag.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/hal_diag.h
diff -N hal/powerpc/rattler/current/include/hal_diag.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/hal_diag.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,67 @@
+#ifndef CYGONCE_HAL_HAL_DIAG_H
+#define CYGONCE_HAL_HAL_DIAG_H
+
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:nickg
+// Date:        1998-03-02
+// Purpose:     HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage:       #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#endif // CYGONCE_HAL_HAL_DIAG_H
Index: hal/powerpc/rattler/current/include/plf_cache.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/plf_cache.h
diff -N hal/powerpc/rattler/current/include/plf_cache.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/plf_cache.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,76 @@
+#ifndef CYGONCE_PLF_CACHE_H
+#define CYGONCE_PLF_CACHE_H
+
+//=============================================================================
+//
+//      plf_cache.h
+//
+//      Platform HAL cache details
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov
+// Date:        2000-01-26
+// Purpose:     Platform cache control API
+// Description: The macros defined here provide the platform specific
+//              cache control operations / behavior.
+// Usage:       Is included via the architecture cache header:
+//              #include <cyg/hal/hal_cache.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//---------------------------------------------------------------------------
+// Initial cache enabling
+#if 1
+#ifdef CYGSEM_HAL_ROM_MONITOR
+# define CYGPRI_INIT_CACHES
+# define CYGPRI_ENABLE_CACHES
+#endif
+#else
+// Disable caches for now
+# define CYGPRI_INIT_CACHES
+# define CYGPRI_ENABLE_CACHES
+
+#endif
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_PLF_CACHE_H
+// End of plf_cache.h
Index: hal/powerpc/rattler/current/include/plf_intr.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/plf_intr.h
diff -N hal/powerpc/rattler/current/include/plf_intr.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/plf_intr.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,73 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+
+//==========================================================================
+//
+//      plf_intr.h
+//
+//      A&M Rattler (MPC8250) platform specific interrupt definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jskov
+// Contributors: jskov, gthomas
+// Date:         2000-06-13
+// Purpose:      Define platform specific interrupt support
+//              
+// Usage:
+//              #include <cyg/hal/plf_intr.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+//----------------------------------------------------------------------------
+// Reset.
+
+externC void _rattler_reset(void);
+#define HAL_PLATFORM_RESET() _rattler_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0xFE000100
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_PLF_INTR_H
+// End of plf_intr.h
Index: hal/powerpc/rattler/current/include/plf_regs.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/plf_regs.h
diff -N hal/powerpc/rattler/current/include/plf_regs.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/plf_regs.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,65 @@
+#ifndef CYGONCE_HAL_PLF_REGS_H
+#define CYGONCE_HAL_PLF_REGS_H
+
+//==========================================================================
+//
+//      plf_regs.h
+//
+//      A&M Rattler (MPC8250) platform specific interrupt definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jskov
+// Contributors: jskov, gthomas
+// Date:         2000-06-13
+// Purpose:      Define platform specific interrupt support
+//              
+// Usage:
+//              #include <cyg/hal/plf_regs.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGARC_IMM_BASE      0xFF000000
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_PLF_REGS_H
+// End of plf_regs.h
Index: hal/powerpc/rattler/current/include/plf_stub.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/plf_stub.h
diff -N hal/powerpc/rattler/current/include/plf_stub.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/plf_stub.h	19 Aug 2003 16:53:40 -0000
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   pfine
+// Contributors:jskov
+// Date:        2001-11-29
+// Purpose:     Platform HAL stub support for MPC8260 VADS board
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/ppc_stub.h>           // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+
+externC int  wpd_stub_get_char(void);
+externC void wpd_stub_put_char(int);
+#define HAL_STUB_PLATFORM_GET_CHAR            cyg_hal_plf_serial_getc
+#define HAL_STUB_PLATFORM_PUT_CHAR            cyg_hal_plf_serial_putc
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.h
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,37 @@
+// eCos memory layout - Fri Oct 20 10:35:23 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x1000000)  /* 16MB */
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vectors) [];
+#endif
+#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
+#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
+#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
+#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_for_rom) [];
+#endif
+#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom))
+#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x1cd00)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.ldi
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.ldi
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.ldi	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,31 @@
+// eCos memory layout - Fri Oct 20 10:35:23 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0x0000000, LENGTH = 0x1000000 // 16MB
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
+    CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
+    CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
+    CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x3cd00;
+    SECTION_vectors (ram, ALIGN (0x10), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.mlt
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.mlt
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.mlt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_ram.mlt	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,17 @@
+version 0
+region ram 0 100000 0 !
+section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
+section reserved_vsr_table 200 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
+section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom !
+section reserved_for_rom 3cd00 10 0 0 0 1 0 1 vectors vectors !
+section vectors 0 10 0 1 0 1 0 1 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 1 0 1 data data !
+section data 0 8 0 1 0 1 0 1 sbss sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.h
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,35 @@
+// eCos memory layout - Thu May 30 10:21:41 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x1000000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xfe010000)
+#define CYGMEM_REGION_rom_SIZE (0x800000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vectors) [];
+#endif
+#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
+#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
+#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
+#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.ldi
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.ldi
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.ldi	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,31 @@
+// eCos memory layout - Thu May 30 10:21:41 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x1000000
+    rom : ORIGIN = 0xfe010000, LENGTH = 0x800000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_vectors (rom, 0xfe010000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
+    CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
+    CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
+    SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table))
+    SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.mlt
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.mlt
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.mlt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_rom.mlt	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,17 @@
+version 0
+region ram 0 1000000 0 !
+region rom fe010000 800000 1 !
+section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
+section reserved_vsr_table 200 1 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
+section reserved_virtual_table 100 1 0 0 0 1 0 0 data !
+section data 0 10 1 1 0 1 0 0 sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section vectors 0 1 0 1 1 1 1 1 fe000000 fe000000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 0 0 1 data !
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.h
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.h
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.h	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,19 @@
+// eCos memory layout - Thu May 30 10:05:45 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x1000000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xfe010000)
+#define CYGMEM_REGION_rom_SIZE (0x800000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.ldi
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.ldi
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.ldi	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,28 @@
+// eCos memory layout - Thu May 30 10:05:45 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x1000000
+    rom : ORIGIN = 0xfe010000, LENGTH = 0x800000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_vectors (ram, 0, LMA_EQ_VMA)
+    SECTION_text (ram, 0x3400, LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.mlt
===================================================================
RCS file: hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.mlt
diff -N hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.mlt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/include/pkgconf/mlt_powerpc_rattler_romram.mlt	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,14 @@
+version 0
+region ram 0 1000000 0 !
+region rom fe010000 800000 1 !
+section vectors 0 1 0 1 1 0 1 0 0 0 !
+section text 0 1 0 1 1 1 1 1 3400 3400 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 1 0 1 data data !
+section data 0 8 0 1 0 1 0 1 sbss sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
Index: hal/powerpc/rattler/current/misc/redboot_RAM.ecm
===================================================================
RCS file: hal/powerpc/rattler/current/misc/redboot_RAM.ecm
diff -N hal/powerpc/rattler/current/misc/redboot_RAM.ecm
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/misc/redboot_RAM.ecm	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,103 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    rattler ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_POWERPC current ;
+    package -hardware CYGPKG_HAL_POWERPC_MPC8XXX current ;
+    package -hardware CYGPKG_HAL_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+    package -hardware CYGPKG_DEVS_ETH_POWERPC_FCC current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_NS_DNS current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+    inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+    user_value 0x10000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+    inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV320D {
+    inferred_value 1
+};
+
+
Index: hal/powerpc/rattler/current/misc/redboot_ROM.ecm
===================================================================
RCS file: hal/powerpc/rattler/current/misc/redboot_ROM.ecm
diff -N hal/powerpc/rattler/current/misc/redboot_ROM.ecm
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/misc/redboot_ROM.ecm	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,111 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    rattler ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_POWERPC current ;
+    package -hardware CYGPKG_HAL_POWERPC_MPC8XXX current ;
+    package -hardware CYGPKG_HAL_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+    package -hardware CYGPKG_DEVS_ETH_POWERPC_FCC current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_NS_DNS current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+    inferred_value 1
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+    user_value 0x10000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+    inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV320D {
+    inferred_value 1
+};
+
+
Index: hal/powerpc/rattler/current/misc/redboot_ROMRAM+PCI.ecm
===================================================================
RCS file: hal/powerpc/rattler/current/misc/redboot_ROMRAM+PCI.ecm
diff -N hal/powerpc/rattler/current/misc/redboot_ROMRAM+PCI.ecm
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/misc/redboot_ROMRAM+PCI.ecm	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,121 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    rattler ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_POWERPC current ;
+    package -hardware CYGPKG_HAL_POWERPC_MPC8XXX current ;
+    package -hardware CYGPKG_HAL_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+    package -hardware CYGPKG_DEVS_ETH_POWERPC_FCC current ;
+    package -hardware CYGPKG_DEVS_ETH_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_ETH_PHY current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_NS_DNS current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+    inferred_value 1
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROMRAM
+};
+
+cdl_option CYGHWR_HAL_POWERPC_RATTLER_PCI {
+    user_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+    user_value 0x10000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+    inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV320D {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV640 {
+    inferred_value 1
+};
+
+
Index: hal/powerpc/rattler/current/misc/redboot_ROMRAM.ecm
===================================================================
RCS file: hal/powerpc/rattler/current/misc/redboot_ROMRAM.ecm
diff -N hal/powerpc/rattler/current/misc/redboot_ROMRAM.ecm
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/misc/redboot_ROMRAM.ecm	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,117 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    rattler ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_POWERPC current ;
+    package -hardware CYGPKG_HAL_POWERPC_MPC8XXX current ;
+    package -hardware CYGPKG_HAL_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+    package -hardware CYGPKG_DEVS_ETH_POWERPC_FCC current ;
+    package -hardware CYGPKG_DEVS_ETH_POWERPC_RATTLER current ;
+    package -hardware CYGPKG_DEVS_ETH_PHY current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_NS_DNS current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+    inferred_value 1
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROMRAM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+    user_value 0x10000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+    inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV320D {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV640 {
+    inferred_value 1
+};
+
+
Index: hal/powerpc/rattler/current/src/hal_aux.c
===================================================================
RCS file: hal/powerpc/rattler/current/src/hal_aux.c
diff -N hal/powerpc/rattler/current/src/hal_aux.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/src/hal_aux.c	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,356 @@
+//=============================================================================
+//
+//      hal_aux.c
+//
+//      HAL auxiliary objects and code; per platform
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   hmt
+// Contributors:hmt, gthomas
+// Date:        1999-06-08
+// Purpose:     HAL aux objects: startup tables.
+// Description: Tables for per-platform initialization
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_mem.h>            // HAL memory definitions
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/mpc8xxx.h>            // For IMM structures
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_intr.h>
+
+// The memory map is weakly defined, allowing the application to redefine
+// it if necessary. The regions defined below are the minimum requirements.
+CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
+    // Mapping for the Rattler board
+    CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x SDRAM
+    CYGARC_MEMDESC_CACHE( 0xFE000000, 0x00800000 ), // ROM region
+    CYGARC_MEMDESC_NOCACHE( 0x80000000, 0x00100000 ), // Extended I/O
+    CYGARC_MEMDESC_NOCACHE( 0xFF000000, 0x00100000 ), // IMMR registers
+
+    CYGARC_MEMDESC_TABLE_END
+};
+
+//--------------------------------------------------------------------------
+// Platform init code.
+void
+hal_platform_init(void)
+{
+    volatile t_PQ2IMM  *IMM = (volatile t_PQ2IMM *)CYGARC_IMM_BASE;
+    cyg_bool old_board_layout = *(unsigned long *)0xFE0000FC == 0;
+
+    // Configure the I/O pins used by this board
+    //   + = PARx = 0, PSORx = 0, PDIRx = 0
+    //   A = PARX = 1, PSORx = 0, PDIRx = 0
+    //   B = PARX = 1, PSORx = 1, PDIRx = 0
+    //   C = PARX = 1, PSORx = 0, PDIRx = 1
+    //   D = PARX = 1, PSORx = 1, PDIRx = 1
+
+    // Port A
+    //             1111111111222222222233
+    //   01234567890123456789012345678901
+    //   _______________________________________
+    //                                  B  FCC1 - COL/MII
+    //                                 B-  FCC1 - SRC/MII
+    //                                D--  FCC1 - TX_ER/MII
+    //                               D---  FCC1 - TX_EN/MII
+    //                              B----  FCC1 - RX_DV/MII
+    //                             B-----  FCC1 - RX_ER/MII
+    //                            +------
+    //                           +-------
+    //                          +--------
+    //                         +---------
+    //                        C----------  FCC1 - TX[3]/MII
+    //                       C-----------  FCC1 - TX[2]/MII
+    //                      C------------  FCC1 - TX{1]/MII
+    //                     C-------------  FCC1 - TX[0]/MII
+    //                    A--------------  FCC1 - RX[3]/MII
+    //                   A---------------  FCC1 - RX[2]/MII
+    //                  A----------------  FCC1 - RX[1]/MII
+    //                 A-----------------  FCC1 - RX[0]/MII
+    //                +------------------
+    //               +-------------------
+    //              +--------------------
+    //             +---------------------
+    //            +----------------------
+    //           +-----------------------
+    //          +------------------------
+    //         +-------------------------
+    //        +--------------------------
+    //       +---------------------------
+    //      +----------------------------
+    //     +-----------------------------
+    //    +------------------------------
+    //   +-------------------------------
+    //   ++++ ++++ ++++ ++AA AACC CC++ ++BB DDBB
+    //   0000 0000 0000 0011 1111 1100 0011 1111 PAR
+    //   0000 0000 0000 0000 0000 0000 0011 1111 SOR
+    //   0000 0000 0000 0000 0011 1100 0000 1100 DIR
+    IMM->io_regs[PORT_A].ppar = 0x0003FC3F;
+    IMM->io_regs[PORT_A].psor = 0x0000003F;
+    IMM->io_regs[PORT_A].pdir = 0x00003C0C;
+    IMM->io_regs[PORT_A].podr = 0x00000000;
+
+    // Port B
+    //             1111111111222222222233
+    //   01234567890123456789012345678901
+    //   ________________________________
+    //                                  C FCC2 - TX_ER
+    //                                 A- FCC2 - RX_DV
+    //                                D-- FCC2 - TX_EN
+    //                               A--- FCC2 - RX_ER
+    //                              A---- FCC2 - COL
+    //                             A----- FCC2 - CRS
+    //                            C------ FCC2 - TxD[3]
+    //                           C------- FCC2 - TxD[2]
+    //                          C-------- FCC2 - TxD[1]
+    //                         C--------- FCC2 - TxD[0]
+    //                        A---------- FCC2 - RxD[0]
+    //                       A----------- FCC2 - RxD[1]
+    //                      A------------ FCC2 - RxD[2]
+    //                     A------------- FCC2 - RxD[3]
+    //                    +--------------
+    //                   +---------------
+    //                  +----------------
+    //                 +-----------------
+    //                +------------------
+    //               +-------------------
+    //              +--------------------
+    //             +---------------------
+    //            +----------------------
+    //           +-----------------------
+    //          +------------------------
+    //         +-------------------------
+    //        +--------------------------
+    //       +---------------------------
+    //      +----------------------------
+    //     +-----------------------------
+    //    +------------------------------
+    //   +-------------------------------
+    //   ++++ ++++ ++++ ++++ ++AA AACC CCAA ADAC
+    //   0000 0000 0000 0000 0011 1111 1111 1111 PAR
+    //   0000 0000 0000 0000 0000 0000 0000 0100 SOR
+    //   0000 0000 0000 0000 0000 0011 1100 0101 DIR
+    IMM->io_regs[PORT_B].ppar = 0x00003FFF;
+    IMM->io_regs[PORT_B].psor = 0x00000004;
+    IMM->io_regs[PORT_B].pdir = 0x000003C5;
+    IMM->io_regs[PORT_B].podr = 0x00000000;
+
+    // Port C
+    //             1111111111222222222233
+    //   01234567890123456789012345678901
+    //   ________________________________
+    //                                  +
+    //                                 +-
+    //                                +--
+    //                               +---
+    //                              +----
+    //                             +-----
+    //                            +------
+    //                           +-------
+    //                          +--------
+    //                         A--------- CLK10 (FCC1 Rx) [new board layout]
+    //                        A---------- CLK11 (FCC1 Tx)
+    //                       A----------- CLK12 (FCC1 Rx) [old board layout]
+    //                      +------------
+    //                     A------------- CLK14 (FCC2 Tx)
+    //                    A-------------- CLK15 (FCC2 Rx)
+    //                   +--------------- 
+    //                  A---------------- SCC1 - CTS
+    //                 A----------------- SCC1 - CD
+    //                +------------------
+    //               +-------------------
+    //              +--------------------
+    //             +---------------------
+    //            +----------------------
+    //           +-----------------------
+    //          +------------------------
+    //         +-------------------------
+    //        +--------------------------
+    //       +---------------------------
+    //      +----------------------------
+    //     +-----------------------------
+    //    +------------------------------
+    //   +-------------------------------
+    //   ++++ ++++ ++++ ++AA +AA+ AAA+ ++++ ++++
+    //   0000 0000 0000 0011 0110 ?1?0 0000 0000 PAR  (depending on board layout)
+    //   0000 0000 0000 0000 0000 0000 0000 0000 SOR
+    //   0000 0000 0000 0000 0000 0000 0000 0000 DIR
+// #define SCC1_FULL_HANDSHAKE
+#ifdef SCC1_FULL_HANDSHAKE
+    IMM->io_regs[PORT_C].ppar = 0x00036000;
+#else
+    IMM->io_regs[PORT_C].ppar = 0x00006000;
+#endif
+    if (old_board_layout) {
+        IMM->io_regs[PORT_C].ppar |= 0x00000C00;
+    } else {
+        IMM->io_regs[PORT_C].ppar |= 0x00000600;
+    }
+    IMM->io_regs[PORT_C].psor = 0x00000000;
+    IMM->io_regs[PORT_C].pdir = 0x00000000;
+    IMM->io_regs[PORT_C].podr = 0x00000000;
+
+    // Port D
+    //             1111111111222222222233
+    //   01234567890123456789012345678901
+    //   ________________________________
+    //                                  A SCC1 - RxD
+    //                                 D- SCC1 - TxD
+    //                                C-- SCC1 - RTS
+    //                               +---
+    //                              +----
+    //                             +-----
+    //                            +------
+    //                           +-------
+    //                          +--------
+    //                         +---------
+    //                        +----------
+    //                       +-----------
+    //                      +------------
+    //                     +-------------
+    //                    +--------------
+    //                   +---------------
+    //                  +----------------
+    //                 +-----------------
+    //                +------------------
+    //               +-------------------
+    //              +--------------------
+    //             +---------------------
+    //            C---------------------- SMC1 - TxD
+    //           A----------------------- SMC1 - RxD
+    //          +------------------------
+    //         +-------------------------
+    //        +--------------------------
+    //       +---------------------------
+    //      +----------------------------
+    //     +-----------------------------
+    //    +------------------------------
+    //   +-------------------------------
+    //   ++++ ++++ AC++ ++++ ++++ ++++ ++++ +CDA
+    //   0000 0000 1100 0000 0000 0000 0000 0111 PAR
+    //   0000 0000 0000 0000 0000 0000 0000 0010 SOR
+    //   0000 0000 0100 0000 0000 0000 0000 0110 DIR
+#ifdef SCC1_FULL_HANDSHAKE
+    IMM->io_regs[PORT_D].ppar = 0x00C00003;
+    IMM->io_regs[PORT_D].psor = 0x00000002;
+    IMM->io_regs[PORT_D].pdir = 0x00400006;
+    IMM->io_regs[PORT_D].podr = 0x00000000;
+#else
+    IMM->io_regs[PORT_D].ppar = 0x00C00007;
+    IMM->io_regs[PORT_D].psor = 0x00000002;
+    IMM->io_regs[PORT_D].pdir = 0x00400002;
+    IMM->io_regs[PORT_D].podr = 0x00000000;
+#endif
+
+    // Misc I/O bits
+    IMM->io_regs[PORT_B].pdir |= 0x03000000;  // PB7 = Reset FCC1 PHY
+                                              // PB6 = Reset FCC2 PHY
+
+    IMM->io_regs[PORT_B].pdat |= 0x03000000;
+
+    IMM->io_regs[PORT_C].pdir |= 0x3C000000;  // PC5 = FCC2 MDIO
+                                              // PC4 = FCC2 MDC
+                                              // PC3 = FCC1 MDIO
+                                              // PC2 = FCC1 MDC
+    IMM->io_regs[PORT_C].pdat |= 0x3C000000;
+
+    // Clock steering
+    IMM->cpm_mux_cmxuar = 0x00000000;        // Utopia address reg
+    if (old_board_layout) {
+        // Mux for FCC
+        // --11 0111 --11 0101 ---- ---- ---- ----
+        //   xx x                                   FCC1 - Tx clock 11
+        //       xxx                                FCC1 - Rx clock 12
+        //             xx x                         FCC2 - Tx clock 14
+        //                 xxx                      FCC2 - Rx clock 15
+        IMM->cpm_mux_cmxfcr = 0x37350000;
+    } else {
+        // Mux for FCC
+        // --11 0101 --11 0101 ---- ---- ---- ----
+        //   xx x                                   FCC1 - Tx clock 11
+        //       xxx                                FCC1 - Rx clock 10
+        //             xx x                         FCC2 - Tx clock 14
+        //                 xxx                      FCC2 - Rx clock 15
+        IMM->cpm_mux_cmxfcr = 0x35350000;
+    }
+    // Mux for SCCx
+    // --00 0000 --00 1001 --01 0010 --01 1011 
+    //   xx x                                   SCC1 - Rx clock BRG1
+    //       xxx                                SCC1 - Tx clock BRG1
+    //             xx x                         SCC2 - Rx clock BRG2
+    //                 xxx                      SCC2 - Tx clock BRG2
+    //                       xx x               SCC3 - Rx clock BRG3
+    //                           xxx            SCC3 - Tx clock BRG3
+    //                                 xx x     SCC4 - Rx clock BRG4
+    //                                     xxx  SCC4 - Tx clock BRG4
+    IMM->cpm_mux_cmxscr = 0x0009121B;
+    // Mux for SMCx
+    // --01 --01
+    //   xx                                     SMC1 - clock on BRG7
+    //        xx                                SMC2 - clock on BRG8
+    IMM->cpm_mux_cmxsmr = 0x11;
+    
+    // Start up system I/O
+    hal_if_init();
+}
+
+//
+// Cause the platform to reset
+//
+void
+_rattler_reset(void)
+{
+    unsigned long hid0, int_state;
+
+    // Need interrupts off to force checkstop
+    HAL_DISABLE_INTERRUPTS(int_state);
+    IMM->clocks_rmr = 0x01;  // Checkstop Reset Enable
+    // Force a checkstop by turning on parity which is not implemented
+    CYGARC_MFSPR(CYGARC_REG_HID0, hid0); 
+    hid0 |= 0x30000000;
+    CYGARC_MTSPR(CYGARC_REG_HID0, hid0); 
+    diag_printf("...RESET\n");
+    while (1) ;
+}
+
+// EOF hal_aux.c
Index: hal/powerpc/rattler/current/src/hal_diag.c
===================================================================
RCS file: hal/powerpc/rattler/current/src/hal_diag.c
diff -N hal/powerpc/rattler/current/src/hal_diag.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/src/hal_diag.c	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,86 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   hmt
+// Contributors:hmt, jskov
+// Date:        1999-06-08
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt macros
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#include <cyg/hal/hal_stub.h>           // hal_output_gdb_string
+#endif
+
+#include <cyg/hal/ppc_regs.h>
+#include <cyg/hal/mpc8xxx.h>
+
+// This prototype probably needs to be in an include file
+void cyg_hal_plf_serial_init(void);
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+
+// EOF hal_diag.c
Index: hal/powerpc/rattler/current/src/rattler.S
===================================================================
RCS file: hal/powerpc/rattler/current/src/rattler.S
diff -N hal/powerpc/rattler/current/src/rattler.S
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/src/rattler.S	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,260 @@
+#==============================================================================
+##
+##      rattler.S
+##
+##      MPC8250 RATTLER board hardware setup
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    nickg
+## Contributors: wpd, gthomas
+## Date:         2003-06-30
+## Purpose:      RATTLER MPC8250 board hardware setup
+## Description:  This file contains any code needed to initialize the
+##               hardware on the Analogue & Micro Rattler (MPC8250) board.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <pkgconf/hal.h>
+        
+#include <cyg/hal/arch.inc>
+#include <cyg/hal/ppc_regs.h>		/* on-chip resource layout, special */
+#------------------------------------------------------------------------------
+
+        .globl  hal_hardware_init
+hal_hardware_init:
+#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM)
+   #----------------------------------------------
+   # Load the IMMR register with the base address
+   #----------------------------------------------
+
+   addis    r30,0,0xFF01   # IMMR base addr = 0xFF000000+10000. We add 
+                          # 0x10000 because using relative addressing
+                          # in load and store instructions only allow a
+                          # offset from the base of +/-32767.
+        
+        // Setup for LEDS, using PA[0..2]
+        lwi     r3,0xE0000000
+        stw     r3,CYGARC_REG_IMM_PDIRA(r30)
+        li      r3,0    // All LEDs on
+        stw     r3,CYGARC_REG_IMM_PDATA(r30)
+
+        // Force BR0 to map everything
+        lwi     r3,0x00000E76
+        stw     r3,CYGARC_REG_IMM_OR0(r30)
+	
+// Need to set the PC into the FLASH (ROM) before the address map changes
+	lwi	r3,10f
+        lwi     r5,CYGMEM_REGION_rom
+	or	r3,r3,r5
+	mtctr	r3
+	bctr
+10:	
+
+        // Running in FLASH address space
+        lwi     r3,0xC0000000
+        stw     r3,CYGARC_REG_IMM_PDATA(r30)
+
+   #*******************************************
+   # Main System Clock Configuration Registers 
+   #*******************************************
+
+
+// SC  SIUMCR           fF010000  0E24c000 SIU              
+// SC  SYPCR            fF010004  FFFFFFC3 SIU              
+// SC  SWSR             fF01000E  0000     SIU              
+        
+        lwi     r3,0xFFFFFFC3
+        stw     r3,CYGARC_REG_IMM_SYPCR(r30)
+        lwi     r3,0x00000001
+        stw     r3,CYGARC_REG_IMM_SCCR(r30)
+        lwi     r3,0x0E24C000
+        stw     r3,CYGARC_REG_IMM_SIUMCR(r30)
+        li      r3,0x0000
+        sth     r3,CYGARC_REG_IMM_SWSR(r30)
+
+// SC  BCR              fF010024  00000000 SIU              
+// SC  PPC_ACR          fF010028  02       SIU              
+// SC  PPC_ALRH         fF01002C  01234567 SIU              
+// SC  PPC_ALRL         fF010030  89ABCDEF SIU              
+// SC  LCL_ACR          fF010034  02       SIU              
+// SC  LCL_ALRH         fF010038  01234567 SIU              
+// SC  LCL_ALRL         fF01003C  89ABCDEF SIU              
+// SC  TESCR1           fF010040  00000000 SIU              
+// SC  TESCR2           fF010044  00000000 SIU              
+// SC  LTESCR1          fF010048  00000000 SIU              
+// SC  LTESCR2          fF01004C  00000000 SIU              
+// SC  PDTEA            fF010050  00000000 SIU              
+// SC  PDTEM            fF010054  00       SIU              
+// SC  LDTEA            fF010058  00000000 SIU              
+// SC  LDTEM            fF01005C  00       SIU  
+ 
+        li      r3,0x00000000
+        stw     r3,CYGARC_REG_IMM_BCR(r30)
+        li      r3,0x02
+        stb     r3,CYGARC_REG_IMM_PPC_ACR(r30)
+        lwi     r3,0x01234567
+        stw     r3,CYGARC_REG_IMM_PPC_ALRH(r30)
+        lwi     r3,0x89ABCDEF
+        stw     r3,CYGARC_REG_IMM_PPC_ALRL(r30)
+        li      r3,0x02
+        stb     r3,CYGARC_REG_IMM_LCL_ACR(r30)
+        lwi     r3,0x01234567
+        stw     r3,CYGARC_REG_IMM_LCL_ALRH(r30)
+        lwi     r3,0x89ABCDEF
+        stw     r3,CYGARC_REG_IMM_LCL_ALRL(r30)
+        li      r3,0x00000000
+        stw     r3,CYGARC_REG_IMM_TESCR1(r30)
+        li      r3,0x00000000
+        stw     r3,CYGARC_REG_IMM_TESCR2(r30)
+        li      r3,0x00000000
+        stw     r3,CYGARC_REG_IMM_PDTEA(r30)
+        li      r3,0x00
+        stw     r3,CYGARC_REG_IMM_PDTEM(r30)
+        li      r3,0x00000000
+        stw     r3,CYGARC_REG_IMM_LDTEA(r30)
+        li      r3,0x00
+        stw     r3,CYGARC_REG_IMM_LDTEM(r30)
+
+
+   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+   # Initialize the memory controller and SDRAM
+   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ 
+        // Memory layout
+
+        // CS0 - 8MB FLASH
+        lwi     r3,0xFE001001
+        stw     r3,CYGARC_REG_IMM_BR0(r30)
+        lwi     r3,0xFF800E76
+        stw     r3,CYGARC_REG_IMM_OR0(r30)
+
+        // CS1 - 16MB DRAM
+        lwi     r3,0xFF003080
+        stw     r3,CYGARC_REG_IMM_OR1(r30)
+        lwi     r3,0x00000041        
+        stw     r3,CYGARC_REG_IMM_BR1(r30)
+ 
+        // CS4 - 1MB external
+        lwi     r3,0xFFF00000
+        stw     r3,CYGARC_REG_IMM_OR4(r30)
+        lwi     r3,0x80001801
+        stw     r3,CYGARC_REG_IMM_BR4(r30)
+
+        // SDRAM controller
+        li      r5,0
+        li      r6,0xFF
+        lwi     r3,0x2000
+        sth     r3,CYGARC_REG_IMM_MPTPR(r30)
+        li      r3,0x1F
+        stb     r3,CYGARC_REG_IMM_PSRT(r30)
+#define SDRAM_MUX_SETUP 0x0269A452
+        lwi     r3,0xE8000000|SDRAM_MUX_SETUP
+        stw     r3,CYGARC_REG_IMM_PSDMR(r30)
+        stb     r6,0(r5)
+        lwi     r3,0xC8000000|SDRAM_MUX_SETUP
+        stw     r3,CYGARC_REG_IMM_PSDMR(r30)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        stb     r6,0(r5)
+        lwi     r3,0xD8000000|SDRAM_MUX_SETUP
+        stw     r3,CYGARC_REG_IMM_PSDMR(r30)
+        stb     r6,0(r5)
+        lwi     r3,0xC0000000|SDRAM_MUX_SETUP
+        stw     r3,CYGARC_REG_IMM_PSDMR(r30)
+
+        // Registers programmed, starting up DRAM
+        lwi     r3,0xA0000000
+        stw     r3,CYGARC_REG_IMM_PDATA(r30)
+        
+        lwi     r3,0x10000
+        mtctr   r3
+10:     nop     
+        bdnz    10b        
+
+        // Ready to return
+        lwi     r3,0x80000000
+        stw     r3,CYGARC_REG_IMM_PDATA(r30)
+
+#ifdef CYG_HAL_STARTUP_ROM
+	# move return address to where the ROM is
+	mflr	r3
+        lwi     r4,0x00FFFFFF        // CAUTION!! Assumes only low 16M for ROM
+        and     r3,r3,r4
+	oris	r3,r3,CYGMEM_REGION_rom>>16
+	mtlr	r3
+#endif
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+        // Copy image from ROM to RAM
+        mflr    r3              
+        lwi     r4,(CYGMEM_REGION_rom&0xFE000000)
+        lwi     r5,0x01FFFFFF   // ROM/FLASH base
+        and     r3,r3,r5        // segment relative
+        lwi     r6,_hal_hardware_init_done
+        mtlr    r6
+        sub     r6,r3,r6        // Absolute address
+        add     r6,r6,r4        // FLASH address
+        lwi     r7,0            // where to copy to
+        lwi     r8,__ram_data_end
+10:     lwz     r5,0(r6)
+        stw     r5,0(r7)
+        addi    r6,r6,4
+        addi    r7,r7,4
+        cmplw   r7,r8
+        bne     10b
+#endif                
+
+        // Ready to return
+        lwi     r3,0xE0000000
+        stw     r3,CYGARC_REG_IMM_PDATA(r30)
+
+#endif // ROM/ROMRAM
+                
+hardware_init_done:
+        blr
+
+#------------------------------------------------------------------------------
+# end of rattler.S
Index: hal/powerpc/rattler/current/src/redboot_linux_exec.c
===================================================================
RCS file: hal/powerpc/rattler/current/src/redboot_linux_exec.c
diff -N hal/powerpc/rattler/current/src/redboot_linux_exec.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/rattler/current/src/redboot_linux_exec.c	19 Aug 2003 14:52:05 -0000
@@ -0,0 +1,282 @@
+//==========================================================================
+//
+//      redboot_linux_boot.c
+//
+//      RedBoot command to boot Linux
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####OTHERCOPYRIGHTBEGIN####
+//
+//  The structure definitions below are taken from arch/ppc/platforms/rattler8260.h in
+//  the Linux kernel, Copyright (c) 2002, 2003 Gary Thomas, Copyright (c) 1997 Dan Malek. 
+//  Their presence here is for the express purpose of communication with the Linux 
+//  kernel being booted and is considered 'fair use' by the original author and
+//  are included with their permission.
+//
+//####OTHERCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    msalter
+// Contributors: gthomas,msalter
+// Date:         2002-01-14
+// Purpose:      
+// Description:  
+//              
+// This code is part of RedBoot (tm).
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <redboot.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+
+#ifdef CYGPKG_REDBOOT_NETWORKING
+#include <net/net.h>
+#endif
+
+#ifdef CYGPKG_IO_ETH_DRIVERS
+#include <cyg/io/eth/eth_drv.h>            // Logical driver interfaces
+#endif
+
+#ifdef CYGSEM_REDBOOT_HAL_LINUX_BOOT
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//=========================================================================
+
+// Exported CLI function(s)
+static void do_exec(int argc, char *argv[]);
+RedBoot_cmd("exec", 
+            "Execute a Linux image - with MMU off", 
+            "[-w timeout]\n"
+            "        [-c \"kernel command line\"] [<entry_point>]",
+            do_exec
+    );
+
+//=========================================================================
+// Imported from Linux kernel arch/ppc/platforms/rattler8260.h
+//   Copyright (c) 2002, 2003 Gary Thomas (<gary@mlbassoc.com>
+//   Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+//   Used with permission of author(s).
+
+
+/* A Board Information structure that is given to a program when
+ * RedBoot starts it up.
+ */
+typedef struct bd_info {
+	unsigned int	bi_tag;		/* Should be 0x42444944 "BDID" */
+	unsigned int	bi_size;	/* Size of this structure */
+	unsigned int	bi_revision;	/* revision of this structure */
+	unsigned int	bi_bdate;	/* EPPCbug date, i.e. 0x11061997 */
+	unsigned int	bi_memstart;	/* Memory start address */
+	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
+	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
+	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
+	unsigned int	bi_cpmfreq;	/* CPM Freq, in Hz */
+	unsigned int	bi_brgfreq;	/* BRG Freq, in Hz */
+	unsigned int	bi_vco;		/* VCO Out from PLL */
+	unsigned int	bi_baudrate;	/* Default console baud rate */
+	unsigned int	bi_immr;	/* IMMR when called from boot rom */
+	unsigned char	bi_enetaddr[6];
+        unsigned char   *bi_cmdline;    /*  Pointer to command line */
+} bd_t;
+
+//
+// Execute a Linux kernel - this is a RedBoot CLI command
+//
+static void 
+do_exec(int argc, char *argv[])
+{
+    unsigned long entry;
+    bool wait_time_set, cmd_line_set;
+    int  wait_time;
+    char *cmd_line;
+    char *cline;
+    struct option_info opts[2];
+    hal_virtual_comm_table_t *__chan;
+    int baud_rate;
+
+    bd_t *board_info;
+    CYG_INTERRUPT_STATE oldints;
+    unsigned long sp = CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE;
+    
+    init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM, 
+              (void **)&wait_time, (bool *)&wait_time_set, "wait timeout");
+    init_opts(&opts[1], 'c', true, OPTION_ARG_TYPE_STR, 
+              (void **)&cmd_line, (bool *)&cmd_line_set, "kernel command line");
+    entry = entry_address;  // Default from last 'load' operation
+    if (!scan_opts(argc, argv, 1, opts, 2, (void *)&entry, OPTION_ARG_TYPE_NUM, 
+                   "[physical] starting address")) {
+        return;
+    }
+
+    // Determine baud rate on current console
+    __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+    baud_rate = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_GETBAUD);
+    if (baud_rate <= 0) {
+        baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+    }
+
+    // Make a little space at the top of the stack, and align to
+    // 64-bit boundary.
+    sp = (sp-128) & ~7;  // The Linux boot code uses this space for FIFOs
+    
+    // Copy the commandline onto the stack, and set the SP to just below it.
+    if (cmd_line_set) {
+	int len,i;
+
+	// get length of string
+	for( len = 0; cmd_line[len] != '\0'; len++ );
+
+	// decrement sp by length of string and align to
+	// word boundary.
+	sp = (sp-(len+1)) & ~3;
+
+	// assign this SP value to command line start
+	cline = (char *)sp;
+
+	// copy command line over.
+	for( i = 0; i < len; i++ )
+	    cline[i] = cmd_line[i];
+	cline[len] = '\0';
+
+    } else {
+        cline = (char *)NULL;
+    }
+    
+    // Set up parameter struct at top of stack
+    sp = sp-sizeof(bd_t);
+    board_info = (bd_t *)sp;
+    memset(board_info, sizeof(*board_info), 0);
+    
+    board_info->bi_tag		= 0x42444944;
+    board_info->bi_size		= sizeof(board_info);
+    board_info->bi_revision	= 1;
+    board_info->bi_bdate	= 0x06012002;
+    board_info->bi_memstart	= CYGMEM_REGION_ram;
+    board_info->bi_memsize	= CYGMEM_REGION_ram_SIZE;
+    board_info->bi_intfreq	= CYGHWR_HAL_POWERPC_CPU_SPEED*1000000;
+    board_info->bi_busfreq	= CYGHWR_HAL_POWERPC_BUS_SPEED*1000000;
+    board_info->bi_cpmfreq	= CYGHWR_HAL_POWERPC_CPM_SPEED*1000000;
+    board_info->bi_brgfreq      = ((CYGHWR_HAL_POWERPC_CPM_SPEED*2)*1000000)/16;
+    board_info->bi_baudrate     = baud_rate;
+    board_info->bi_cmdline      = cline;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+    memcpy(board_info->bi_enetaddr, __local_enet_addr, sizeof(enet_addr_t));
+#endif
+
+    // adjust SP to 64 bit boundary, and leave a little space
+    // between it and the commandline for PowerPC calling
+    // conventions.
+	
+    sp = (sp-32)&~7;
+
+    if (wait_time_set) {
+        int script_timeout_ms = wait_time * 1000;
+#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
+        unsigned char *hold_script = script;
+        script = (unsigned char *)0;
+#endif
+        diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
+                    (void *)entry, wait_time);
+        while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
+            int res;
+            char line[80];
+            res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
+            if (res == _GETS_CTRLC) {
+#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
+                script = hold_script;  // Re-enable script
+#endif
+                return;
+            }
+            script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
+        }
+    }
+
+#ifdef CYGPKG_IO_ETH_DRIVERS
+    eth_drv_stop();
+#endif
+
+    // Disable interrupts
+    HAL_DISABLE_INTERRUPTS(oldints);
+
+    // Put the caches to sleep.
+    HAL_DCACHE_SYNC();
+    HAL_ICACHE_DISABLE();
+    HAL_DCACHE_DISABLE();
+    HAL_DCACHE_SYNC();
+    HAL_ICACHE_INVALIDATE_ALL();
+    HAL_DCACHE_INVALIDATE_ALL();
+
+//    diag_printf("entry %08x, sp %08x, info %08x, cmd line %08x, baud %d\n",
+//		entry, sp, board_info, cline, baud_rate);
+//    breakpoint();
+    
+    // Call into Linux
+    __asm__ volatile (        
+	               // Start by disabling MMU - the mappings are
+	               // 1-1 so this should not cause any problems
+	               "mfmsr	3\n"
+		       "li      4,0xFFFFFFCF\n"
+		       "and	3,3,4\n"
+		       "sync\n"
+		       "mtmsr	3\n"
+		       "sync\n"
+
+		       // Now set up parameters to jump into linux
+
+		       "mtlr	%0\n"		// set entry address in LR
+		       "mr	1,%1\n"		// set stack pointer
+		       "mr	3,%2\n"		// set board info in R3
+		       "mr	4,%3\n"		// set command line in R4
+		       "blr          \n"	// jump into linux
+		       :
+		       : "r"(entry),"r"(sp),"r"(board_info),"r"(cline)
+		       : "r3", "r4"
+	             
+	             );
+}
+
+#endif // CYGSEM_REDBOOT_HAL_LINUX_BOOT
+
+//=========================================================================
+// EOF redboot_linux_exec.c
Index: hal/powerpc/viper/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/ChangeLog,v
retrieving revision 1.25
diff -u -5 -p -r1.25 ChangeLog
--- hal/powerpc/viper/current/ChangeLog	24 Jul 2003 20:24:09 -0000	1.25
+++ hal/powerpc/viper/current/ChangeLog	19 Aug 2003 16:57:42 -0000
@@ -1,5 +1,11 @@
+2003-08-19  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/viper.S: 
+	* cdl/hal_powerpc_viper.cdl: Support new model Viper which
+	has slightly different layout and 16bit FLASH (instead of 8bit)
+
 2003-07-18  Nick Garnett  <nickg@balti.calivar.com>
 
 	* cdl/hal_powerpc_viper.cdl:
         Changed values for CYGNUM_HAL_RTC_NUMERATOR,
         CYGNUM_HAL_RTC_DENOMINATOR and CYGNUM_HAL_RTC_PERIOD to
Index: hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl,v
retrieving revision 1.15
diff -u -5 -p -r1.15 hal_powerpc_viper.cdl
--- hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl	24 Jul 2003 20:24:09 -0000	1.15
+++ hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl	19 Aug 2003 14:52:05 -0000
@@ -66,19 +66,53 @@ cdl_package CYGPKG_HAL_POWERPC_VIPER {
     implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
     implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
     implements    CYGNUM_HAL_QUICC_SMC1
     implements    CYGNUM_HAL_QUICC_SCC1
 
-    requires      { (CYGHWR_HAL_POWERPC_MPC8XX == "860T") || (CYGHWR_HAL_POWERPC_MPC8XX == "862P") }
-
     define_proc {
         puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_powerpc_mpc8xx.h>"
         puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_viper.h>"
+    }
+
+    cdl_component CYGPKG_HAL_POWERPC_VIPER_MODEL {
+        display       "Viper model"
+        requires      { (CYGHWR_HAL_POWERPC_VIPER_I + CYGHWR_HAL_POWERPC_VIPER_II) == 1 }
+        default_value 1
+        no_define
+        description "
+           The sub-options of this component define the model of Viper"
+
+        cdl_option  CYGHWR_HAL_POWERPC_VIPER_I {
+            display       "Viper-I with 860T"
+            requires      !CYGHWR_HAL_POWERPC_VIPER_II
+            requires      { (CYGHWR_HAL_POWERPC_MPC8XX == "860T") ||
+                            (CYGHWR_HAL_POWERPC_MPC8XX == "862P") }
+            default_value 1
+            define_proc {
+                puts $::cdl_header "#define HAL_PLATFORM_CPU    \"PowerPC 860T\""
+                puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"A&M VIPER\""
+                puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+            }
+            description "
+                Select this model for an original Viper with the PPC860T or PPC862P processor."
+        }
 
-	puts $::cdl_header "#define HAL_PLATFORM_CPU    \"PowerPC 860\""
-        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"A&M VIPER\""
-        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        cdl_option  CYGHWR_HAL_POWERPC_VIPER_II {
+            display       "Viper-I with 860T"
+            requires      !CYGHWR_HAL_POWERPC_VIPER_I
+            requires      { (CYGHWR_HAL_POWERPC_MPC8XX == "860T") ||
+                            (CYGHWR_HAL_POWERPC_MPC8XX == "866T") }
+            default_value 0
+            define_proc {
+                puts $::cdl_header "#define HAL_PLATFORM_CPU    \"PowerPC 860T\""
+                puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"A&M VIPER\""
+                puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+            }
+            description "
+                Select this model for a Viper with the new board layout.  This
+                version will be outfitted with either a PPC860T or PPC866T processor."
+        }
     }
 
     cdl_component CYG_HAL_STARTUP {
         display       "Startup type"
         flavor        data
@@ -94,11 +128,11 @@ cdl_package CYGPKG_HAL_POWERPC_VIPER {
     }
 
     cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED {
         display          "Development board clock speed (MHz)"
         flavor           data
-        legal_values     { 47 51 55 59 63 100 }
+        legal_values     { 47 51 55 59 63 100 133 }
         default_value    63
         description      "
            VIPER Development Boards have various system clock speeds
            depending on the processor fitted.  Select the clock speed
            appropriate for your board so that the system can set the serial
Index: hal/powerpc/viper/current/src/viper.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/src/viper.S,v
retrieving revision 1.10
diff -u -5 -p -r1.10 viper.S
--- hal/powerpc/viper/current/src/viper.S	5 Mar 2003 17:15:44 -0000	1.10
+++ hal/powerpc/viper/current/src/viper.S	19 Aug 2003 14:52:05 -0000
@@ -231,14 +231,19 @@ FUNC_START( hal_hardware_init )
         blt	1b
 #endif // CYGPRI_DO_PROGRAM_UPMS
 	LED( 0x12 )
 
 	/*
-	 * Set refresh timer prescaler to divide by 8.
+	 * Set refresh timer prescaler to divide by 32 or 64
 	 */
-        li	r3,PTP_DIV32
-        sth	r3,MPTPR(r4)
+#ifdef CYGHWR_HAL_POWERPC_MPC8XX_866T
+        li      r3,PTP_DIV64 //use 64 divide as we have run out of bits in the PTA at 133Mhz core
+        sth    r3,MPTPR(r4)
+#else   
+        li     r3,PTP_DIV32
+        sth    r3,MPTPR(r4)
+#endif
 
         /*
 	 * See Table 15-16 MPC860 User's Manual.
 	 *
 // Set the value of Machine A Mode Register (MAMR) to $5E802114.
@@ -256,47 +261,57 @@ FUNC_START( hal_hardware_init )
 	 */
 
 //        
 // PTA field is (System Clock in MHz * Refresh rate in us) / Prescale
 // e.g.  ((14*3.6864)*62.5)/32 => 100.8 => 101        
-//                
+//
+#ifdef CYGHWR_HAL_POWERPC_MPC8XX_866T
+#define PLPRCR_PTX 0x1a8d4000 // (133MHz core 10meg input
+#define MAMR_PTA 129          // use 133Mhz core as reference
+#else        
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 47)
-#define PLPRCR_PTX 0x00C // (47MHz/3.6864MHz)-1
+#define PLPRCR_PTX 0x00C04000 // (47MHz/3.6864MHz)-1
 #define MAMR_PTA 94        
 #endif        
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 51)
-#define PLPRCR_PTX 0x00D // (51.6MHz/3.6864MHz)-1
+#define PLPRCR_PTX 0x00D04000 // (51.6MHz/3.6864MHz)-1
 #define MAMR_PTA 101
 #endif        
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 55)
-#define PLPRCR_PTX 0x00E // (55.3MHz/3.6864MHz)-1
+#define PLPRCR_PTX 0x00E04000 // (55.3MHz/3.6864MHz)-1
 #define MAMR_PTA 108
 #endif        
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 59)
-#define PLPRCR_PTX 0x00F // (58.9MHz/3.6864MHz)-1
+#define PLPRCR_PTX 0x00F04000 // (58.9MHz/3.6864MHz)-1
 #define MAMR_PTA 116
 #endif        
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 63)
-#define PLPRCR_PTX 0x010 // (62.7MHz/3.6864MHz)-1
+#define PLPRCR_PTX 0x01004000 // (62.7MHz/3.6864MHz)-1
 #define MAMR_PTA 123
 #endif        
 #if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 100)
-#define PLPRCR_PTX 0x01A // (99.53MHz/3.6864MHz)-1
+#define PLPRCR_PTX 0x01A04000 // (99.53MHz/3.6864MHz)-1
 #define MAMR_PTA 194
 #endif        
 //#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF)
+#endif                
         lwi     r3,0x00802114|(MAMR_PTA<<24)
         stw	r3,MAMR(r4)
         stw	r3,MBMR(r4)
 
 	/*
 	 * Base Register initialization.
 	 */
 
        	/* BOOT ROM */
+#ifdef CYGHWR_HAL_POWERPC_VIPER_I  // Old board layout
         lwi	r3,0xFE000401	# 8-bit, GPCM
         lwi	r5,0xFF800774   # 7 wait states, up to 8MB
+#else
+        lwi	r3,0xFE000801	# 16-bit, GPCM
+        lwi	r5,0xFF800774   # 7 wait states, up to 8MB
+#endif                
         stw	r3,BR0(r4)
         stw	r5,OR0(r4)
 
 	/* Misc I/O, 16 bit port */
         lwi	r3,0xFA100801
@@ -386,11 +401,11 @@ FUNC_START( hal_hardware_init )
 // 	Field CSR (bit 24) = 0
 // 	Field LOLRE (bit 25) = 0
 // 	Field FIOPD (bit 26) = 0
 // 	Field Reserved (bits 27-31) = 0
 	 */
-	lwi	r3,0x04000|(PLPRCR_PTX<<20)
+        lwi     r3,PLPRCR_PTX
 	stw	r3,PLPRCR(r4)
 
 	LED(0xE0)
 	lwi	r3,0x40000
 	mtctr	r3

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