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PowerPC - fix some debug issues


Found on the A&M Adder (850).

-- 
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: devs/eth/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.19
diff -u -5 -p -r1.19 ChangeLog
--- devs/eth/powerpc/quicc/current/ChangeLog	28 Mar 2003 18:21:02 -0000	1.19
+++ devs/eth/powerpc/quicc/current/ChangeLog	15 Jul 2003 00:55:14 -0000
@@ -1,5 +1,12 @@
+2003-07-14  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/if_quicc.c (quicc_eth_init): Only flush cache if enabled.
+
+	* cdl/quicc_eth_drivers.cdl: Force serial debug messages during
+	initialization (work around startup issues with RedBoot).
+
 2003-03-28  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/if_quicc.c: Align data buffers on cache boundary.
 
 2003-03-14  Nick Garnett  <nickg@calivar.com>
Index: devs/eth/powerpc/quicc/current/cdl/quicc_eth_drivers.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/cdl/quicc_eth_drivers.cdl,v
retrieving revision 1.5
diff -u -5 -p -r1.5 quicc_eth_drivers.cdl
--- devs/eth/powerpc/quicc/current/cdl/quicc_eth_drivers.cdl	23 May 2002 23:00:47 -0000	1.5
+++ devs/eth/powerpc/quicc/current/cdl/quicc_eth_drivers.cdl	15 Jul 2003 00:54:44 -0000
@@ -7,10 +7,11 @@
 # ====================================================================
 #####ECOSGPLCOPYRIGHTBEGIN####
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
 ## Software Foundation; either version 2 or (at your option) any later version.
 ##
@@ -59,10 +60,13 @@ cdl_package CYGPKG_DEVS_ETH_POWERPC_QUIC
 
     implements    CYGHWR_NET_DRIVERS
     implements    CYGHWR_NET_DRIVER_ETH0
     include_dir   .
     include_files ; # none _exported_ whatsoever
+
+    # Debug I/O during network stack initialization is not reliable
+    requires { !CYGPKG_NET || CYGPKG_NET_FORCE_SERIAL_CONSOLE == 1 }
 
     description   "Ethernet driver for PowerPC MPC8xx boards."
     compile       -library=libextras.a if_quicc.c
 
     cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE {
Index: devs/eth/powerpc/quicc/current/src/if_quicc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c,v
retrieving revision 1.19
diff -u -5 -p -r1.19 if_quicc.c
--- devs/eth/powerpc/quicc/current/src/if_quicc.c	28 Mar 2003 18:21:02 -0000	1.19
+++ devs/eth/powerpc/quicc/current/src/if_quicc.c	15 Jul 2003 00:55:14 -0000
@@ -7,11 +7,11 @@
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
@@ -221,12 +221,14 @@ quicc_eth_init(struct cyg_netdevtab_entr
         }
     }
 
     // Ensure consistent state between cache and what the QUICC sees
     HAL_DCACHE_IS_ENABLED(cache_state);
-    HAL_DCACHE_SYNC();
-    HAL_DCACHE_DISABLE();
+    if (cache_state) {
+        HAL_DCACHE_SYNC();
+        HAL_DCACHE_DISABLE();
+    }
 
 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
     // Set up to handle interrupts
     cyg_drv_interrupt_create(QUICC_ETH_INT,
                              CYGARC_SIU_PRIORITY_HIGH,
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.30
diff -u -5 -p -r1.30 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog	24 Jun 2003 06:24:58 -0000	1.30
+++ hal/powerpc/mpc8xx/current/ChangeLog	15 Jul 2003 00:56:51 -0000
@@ -1,5 +1,12 @@
+2003-07-14  Gary Thomas  <gary@mlbassoc.com>
+
+	* include/var_cache.h: Data cache flush on 850 fails when using 
+	cache SPR commands, so use brute force.  This fixes some problems
+	with network based debugging (RedBoot got lost because of cache
+	not being flushed properly).
+
 2003-06-24  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* include/var_intr.h (cyg_hal_interrupt_acknowledge): Don't 
 	inadvertently clear other interrupts when acknowledging the
 	intended int. Reported by Mark Retallack.
Index: hal/powerpc/mpc8xx/current/include/var_cache.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_cache.h,v
retrieving revision 1.5
diff -u -5 -p -r1.5 var_cache.h
--- hal/powerpc/mpc8xx/current/include/var_cache.h	23 Mar 2003 16:22:14 -0000	1.5
+++ hal/powerpc/mpc8xx/current/include/var_cache.h	15 Jul 2003 00:03:53 -0000
@@ -138,10 +138,21 @@
                   "mtspr %0, %1;"                       \
                   : : "I" (CYGARC_REG_DC_CST),          \
                       "r" (CYGARC_REG_DC_CMD_IA))
 
 // Synchronize the contents of the cache with memory.
+#if defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
+// Note: the data cache flush seems to be broken on this chip :-(
+#define HAL_DCACHE_SYNC()                                       \
+    CYG_MACRO_START                                             \
+    cyg_int32 i;                                                \
+    cyg_uint32 *__base = (cyg_uint32 *) (0);                    \
+    for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \
+        asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0");     \
+    }                                                           \
+    CYG_MACRO_END
+#else
 #define HAL_DCACHE_SYNC()                                                     \
     CYG_MACRO_START                                                           \
     cyg_int32 i;                                                              \
     for (i = 0; i < HAL_DCACHE_SETS; i++){                                    \
         asm volatile ("sync;"                                                 \
@@ -157,10 +168,11 @@
                         /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1                  \
                                       |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
                         /* %4 */ "r" (CYGARC_REG_DC_CMD_FL));                 \
     }                                                                         \
     CYG_MACRO_END
+#endif
 
 // Query the state of the data cache
 #define HAL_DCACHE_IS_ENABLED(_state_)                          \
     asm volatile ("mfspr  %0, %1;"                              \
                   "rlwinm %0,%0,1,31,31;"                       \

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