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uE250 fix again
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 28 May 2003 12:27:12 -0600
- Subject: uE250 fix again
- Organization: MLB Associates
Thanks to my MUA, these changes were not sent before.
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/arm/xscale/uE250/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/ChangeLog,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -5 -p -r1.8 -r1.9
--- hal/arm/xscale/uE250/current/ChangeLog 8 Mar 2003 14:39:46 -0000 1.8
+++ hal/arm/xscale/uE250/current/ChangeLog 28 May 2003 18:12:22 -0000 1.9
@@ -1,5 +1,9 @@
+2003-05-28 Gary Thomas <gary@mind.be>
+
+ * src/xilinx-load.c: Improve feedback during FPGA downloads.
+
2003-03-08 Gary Thomas <gary@mind.be>
* include/pkgconf/mlt_arm_xscale_uE250_ram.mlt:
* include/pkgconf/mlt_arm_xscale_uE250_ram.ldi:
* include/pkgconf/mlt_arm_xscale_uE250_ram.h: RAM limits were wrong.
Index: hal/arm/xscale/uE250/current/include/plf_io.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/include/plf_io.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -5 -p -r1.2 -r1.3
--- hal/arm/xscale/uE250/current/include/plf_io.h 24 Feb 2003 18:10:08 -0000 1.2
+++ hal/arm/xscale/uE250/current/include/plf_io.h 28 May 2003 18:12:22 -0000 1.3
@@ -186,11 +186,11 @@ externC void pci_io_write_32(cyg_uint32
#define CYG_PCI_MAX_DEV 6
#define CYG_PCI_MAX_BUS 1
#define CYG_PCI_MAX_FN 1
-#define HAL_IDE_NUM_CONTROLLERS 1
+#define HAL_IDE_NUM_CONTROLLERS 1 // Default card has two controllers - maybe should be 2?
#define HAL_IDE_READ_UINT8( __ctlr, __reg, __val) \
__val = cyg_hal_plf_ide_read_uint8((__ctlr), (__reg))
#define HAL_IDE_READ_UINT16( __ctlr, __reg, __val) \
Index: hal/arm/xscale/uE250/current/src/xilinx-load.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/src/xilinx-load.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -5 -p -r1.2 -r1.3
--- hal/arm/xscale/uE250/current/src/xilinx-load.c 25 Feb 2003 23:44:50 -0000 1.2
+++ hal/arm/xscale/uE250/current/src/xilinx-load.c 28 May 2003 18:12:22 -0000 1.3
@@ -131,19 +131,24 @@ _zcfree(void *opaque, void *ptr)
static int
_zchar(void)
{
int err;
struct _zchar_info *info = (struct _zchar_info *)stream.opaque;
+ static char spin[] = "|/-\\|-";
+ static int tick = 0;
if (info->avail == 0) {
stream.next_out = info->buf;
stream.avail_out = sizeof(info->buf);
info->ptr = info->buf;
err = inflate(&stream, Z_SYNC_FLUSH);
info->avail = (char *)stream.next_out - info->buf;
if (--info->feedback == 0) {
- diag_printf(".");
+ diag_printf("%c\b", spin[tick++]);
+ if (tick >= (sizeof(spin)-1)) {
+ tick = 0;
+ }
info->feedback = FEEDBACK_COUNT;
}
}
if (info->avail) {
info->avail--;
@@ -214,15 +219,13 @@ bitfile_process_string_tag(char *descrip
{
int len,i;
len = bitfile_get_len16(_bitfile);
diag_printf(description);
- diag_printf(": ");
for (i = 0; i < len; i++) {
diag_printf("%c", (*_bitfile)());
}
- diag_printf("\n");
}
/**
* Process the 'e' tag in the bit file, which is the actual code that is to
* be programmed on the fpga.
@@ -323,11 +326,11 @@ vga_bitfile_process_tag_e(_bitfile_fun *
static void
download_bitstream(char *title, _bitfile_fun *_bitfile, _download_fun *_download)
{
int len, tag;
- diag_printf("Loading %s Bitstream\n", title);
+ diag_printf("Load %s(", title);
len = bitfile_get_len16(_bitfile);
while (len-- > 0) {
(*_bitfile)(); // Skip
}
@@ -337,23 +340,23 @@ download_bitstream(char *title, _bitfile
while (tag != 'e') {
tag = bitfile_get_tag(_bitfile);
switch (tag) {
case 'a':
- bitfile_process_string_tag("Design name", _bitfile);
+ bitfile_process_string_tag("Design:", _bitfile);
break;
case 'b':
- bitfile_process_string_tag("Part name", _bitfile);
+ bitfile_process_string_tag(", Part:", _bitfile);
break;
case 'c':
- bitfile_process_string_tag("Date", _bitfile);
+ bitfile_process_string_tag(", Date:", _bitfile);
break;
case 'd':
- bitfile_process_string_tag("Time", _bitfile);
+ bitfile_process_string_tag(" ", _bitfile);
break;
case 'e':
(*_download)(_bitfile);
break;
@@ -390,13 +393,13 @@ load_fpga(cyg_uint8 *compressed_bitfile,
diag_printf("%s: Can't init stream\n", __FUNCTION__);
return;
}
// Set up to download FPGA bitstreap
*PXA2X0_GPSR0 = FPGA_PROG;
- download_bitstream("PCI Controller", _zchar, bitfile_process_tag_e);
+ download_bitstream("PCI ctlr", _zchar, bitfile_process_tag_e);
inflateEnd(&stream);
- diag_printf(" %x bytes processed\n", zchar_data.total);
+ diag_printf(") %x bytes\n", zchar_data.total);
}
/**
* Process a bitfile located at the given address.
*/
@@ -419,10 +422,10 @@ load_vga(cyg_uint8 *compressed_bitfile,
err = inflateInit(&stream);
if (err) {
diag_printf("%s: Can't init stream\n", __FUNCTION__);
return;
}
- download_bitstream("VGA Controller", _zchar, vga_bitfile_process_tag_e);
+ download_bitstream("VGA ctlr", _zchar, vga_bitfile_process_tag_e);
inflateEnd(&stream);
- diag_printf(" %x bytes processed\n", zchar_data.total);
+ diag_printf(") %x bytes\n", zchar_data.total);
}