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SH HAL tweaks
- From: Bart Veer <bartv at ecoscentric dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Sun, 19 Jan 2003 12:18:45 +0000 (GMT)
- Subject: SH HAL tweaks
The SH assembler shipped with binutils 2.13.1 is more finicky than
previous versions, and the patches below work around this.
First, when performing an immediate mov with an 8-bit constant, the
assembler now complains if the constant is e.g. 0xffffffec, even
if after sign-extending 0xec you end up with the same result. Hence
code of the form
mov #<some register>,r1
has been replaced with
mov #<some register> & 0x0FF, r1
Similarly if you try to put a number like that into a 16-bit word then
the assembler complains, so masking is now used. This technique was
used on some platforms for initialization.
.word <some register>
has been replaced with
.word (<some register) & 0x0000FFFF)
Bart
2003-01-18 Bart Veer <bartv@ecoscentric.com>
* src/variant.S, include/variant.inc:
Cope with binutils 2.13.1, gas is morefinicky about immediate
constants.
Index: variant.inc
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/sh3/current/include/variant.inc,v
retrieving revision 1.4
diff -u -u -r1.4 variant.inc
--- variant.inc 23 May 2002 23:05:02 -0000 1.4
+++ variant.inc 19 Jan 2003 12:15:43 -0000
@@ -84,15 +85,15 @@
mov.l $nCYG_SR,r1 ! Put CPU in a well-known state
ldc r1,sr
mov #0,r0
- mov #CYGARC_REG_CCR,r1 ! Disable cache
+ mov #CYGARC_REG_CCR & 0x0FF,r1 ! Disable cache
mov.l r0,@r1
- mov #CYGARC_REG_MMUCR,r1 ! Disable MMU
+ mov #CYGARC_REG_MMUCR & 0x0FF,r1 ! Disable MMU
mov.l r0,@r1
- mov #CYGARC_REG_BBRA,r1 ! Disable UBC Channel A
+ mov #CYGARC_REG_BBRA & 0x0FF,r1 ! Disable UBC Channel A
mov.w r0,@r1
- mov #CYGARC_REG_BBRB,r1 ! Disable UBC Channel B
+ mov #CYGARC_REG_BBRB & 0x0FF,r1 ! Disable UBC Channel B
mov.w r0,@r1
- mov #CYGARC_REG_BRCR,r1 ! Reset UBC common register
+ mov #CYGARC_REG_BRCR & 0x0FF,r1 ! Reset UBC common register
mov.w r0,@r1
mov.l $CYGARC_REG_TSTR,r1 ! Disable timers
mov.b r0,@r1
@@ -116,7 +117,7 @@
mov.w r0,@r1
#endif
mov.w $nCYG_WTCSR,r0 ! Clear watchdog
- mov #CYGARC_REG_WTCSR,r1
+ mov #CYGARC_REG_WTCSR & 0x0FF,r1
mov.w r0,@r1
# Initialize VBR if necessary
Index: variant.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/sh3/current/src/variant.S,v
retrieving revision 1.7
diff -u -u -r1.7 variant.S
--- variant.S 23 May 2002 23:05:03 -0000 1.7
+++ variant.S 19 Jan 2003 12:09:25 -0000
@@ -78,7 +79,7 @@
FUNC_START(cyg_hal_cache_enable)
GOTO_NONCACHED_SHADOW
- mov #CYGARC_REG_CCR,r1
+ mov #CYGARC_REG_CCR & 0x0FF,r1
mov.l @r1,r0
mov #CYGARC_REG_CCR_CE,r2
or r2,r0
@@ -89,7 +90,7 @@
FUNC_START(cyg_hal_cache_disable)
GOTO_NONCACHED_SHADOW
- mov #CYGARC_REG_CCR,r1
+ mov #CYGARC_REG_CCR & 0x0FF,r1
mov.l @r1,r0
mov #CYGARC_REG_CCR_CE,r2
not r2,r2
@@ -101,7 +102,7 @@
FUNC_START(cyg_hal_cache_invalidate_all)
GOTO_NONCACHED_SHADOW
- mov #CYGARC_REG_CCR,r1
+ mov #CYGARC_REG_CCR & 0x0FF,r1
mov.l @r1,r0
mov #CYGARC_REG_CCR_CF,r2
or r2,r0
@@ -168,7 +169,7 @@
GOTO_NONCACHED_SHADOW
# Mode argument in r4.
# Read current state and mask out the two caching mode bits
- mov #CYGARC_REG_CCR,r1
+ mov #CYGARC_REG_CCR & 0x0FF,r1
mov.l @r1,r3
mov #CYGARC_REG_CCR_CB|CYGARC_REG_CCR_WT,r2
and r2,r4
2003-01-19 Bart Veer <bartv@ecoscentric.com>
* include/platform.inc: avoid warnings with binutils 2.13.1
Index: platform.inc
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/cq7708/current/include/platform.inc,v
retrieving revision 1.7
diff -u -u -r1.7 platform.inc
--- platform.inc 23 May 2002 23:04:40 -0000 1.7
+++ platform.inc 19 Jan 2003 12:16:54 -0000
@@ -81,29 +82,29 @@
BSC_settings_table:
# These are the settings set by the ROM Monitor.
- .word CYGARC_REG_FRQCR
+ .word (CYGARC_REG_FRQCR & 0x0000FFFF)
.word CYGARC_REG_FRQCR_INIT
# BCR1: Areas 3 are SDRAM
- .word CYGARC_REG_BCR1
+ .word (CYGARC_REG_BCR1 & 0x0000FFFF)
.word 0x0010
# BCR2: Bus size of areas 2,4 are 8 bits
- .word CYGARC_REG_BCR2
+ .word (CYGARC_REG_BCR2 & 0x0000FFFF)
.word 0x3ddc
# WCR1: 3 wait-state cycles inserted for all areas
- .word CYGARC_REG_WCR1
+ .word (CYGARC_REG_WCR1 & 0x0000FFFF)
.word 0x3fff
# WCR2: cs0=8wait cs1=0wait cs2=0wait cs3=2wait cs4=4wait */
- .word CYGARC_REG_WCR2
+ .word (CYGARC_REG_WCR2 & 0x0000FFFF)
.word 0x0246
# MCR: dram setting 10 bit
- .word CYGARC_REG_MCR
+ .word (CYGARC_REG_MCR & 0x0000FFFF)
.word 0x0074
# RTCSR: refresh timer control
- .word CYGARC_REG_RTCSR
+ .word (CYGARC_REG_RTCSR & 0x0000FFFF)
.word (0xa500 | 0x0010)
# RTCOR: refresh time constant
- .word CYGARC_REG_RTCOR
+ .word (CYGARC_REG_RTCOR & 0x0000FFFF)
.word (0xa500 | 0x003a)
# Table end
2003-01-19 Bart Veer <bartv@ecoscentric.com>
* include/platform.inc (BSC_settings_table):
Avoid warnings with binutils 2.13.1
Index: platform.inc
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/sh/edk7708/current/include/platform.inc,v
retrieving revision 1.6
diff -u -u -r1.6 platform.inc
--- platform.inc 23 May 2002 23:04:45 -0000 1.6
+++ platform.inc 19 Jan 2003 12:17:26 -0000
@@ -74,44 +75,44 @@
bt 2f
mov.w @r3+,r1 // data
bra 1b
- mov.w r1,@r0 // delay slot
+ mov.w r1,@r0 // delay slot
.align 2
BSC_settings_table:
# These are the settings set by the Hitachi ROM Monitor.
- .word CYGARC_REG_FRQCR
+ .word (CYGARC_REG_FRQCR & 0x0000FFFF)
.word CYGARC_REG_FRQCR_INIT
# BCR2: Bus size of areas 1-6 to 32 bits
- .word CYGARC_REG_BCR2
+ .word (CYGARC_REG_BCR2 & 0x0000FFFF)
.word 0x3ffc
# BCR1: Areas 2 and 3 are SDRAM
- .word CYGARC_REG_BCR1
+ .word (CYGARC_REG_BCR1 & 0x0000FFFF)
.word 0x080c
# BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
- .word CYGARC_REG_BCR2
+ .word (CYGARC_REG_BCR2 & 0x0000FFFF)
.word 0x3ffc
# WCR1: 3 wait-state cycles inserted for all areas
- .word CYGARC_REG_WCR1
+ .word (CYGARC_REG_WCR1 & 0x0000FFFF)
.word 0x3fff
# WCR2: extra wait states and full pitch for burst
- .word CYGARC_REG_WCR2
+ .word (CYGARC_REG_WCR2 & 0x0000FFFF)
.word 0xffd7
# MCR: RAS/CAS & burst timing area 2/3
- .word CYGARC_REG_MCR
+ .word (CYGARC_REG_MCR & 0x0000FFFF)
.word 0x963c
# RTCNT: refresh counter (needs a5 in top byte to accept write)
- .word CYGARC_REG_RTCNT
+ .word (CYGARC_REG_RTCNT & 0x0000FFFF)
.word (0xa500 | 0x0000)
# RTCOR: refresh time constant (needs a5 in top byte to accept write)
- .word CYGARC_REG_RTCOR
+ .word (CYGARC_REG_RTCOR & 0x0000FFFF)
.word (0xa500 | 0x003b)
# RFCR: refresh count register (needs a4 in top byte to accept write)
- .word CYGARC_REG_RFCR
+ .word (CYGARC_REG_RFCR & 0x0000FFFF)
.word (0xa400 | 0x0000)
# RTCSR: refresh timer control (needs a5 in top byte to accept write)
- .word CYGARC_REG_RTCSR
+ .word (CYGARC_REG_RTCSR & 0x0000FFFF)
.word (0xa500 | 0x0008)
# Set SDMR to 0x220