This is the mail archive of the mailing list for the eCos project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [Bug 1000096] new AT91 platform: JTST

Hi Andrew,
JTST has the same AIC controller as the other AT91 platforms, but jtst uses
both line 0 (FIQ, connected with dsp halt signal) and line 1 (IRQ).
In general atmel AIC has 1 FIQ +31 IRQs always available, depends on the
board/SOC if they are used.
In this simple at91 port I included the minimum to run eCos on diopsis and
to lunch dsp applications.
It exists supplemental DSP APIs for debbuging, user support and for system
service routines. The problem is
that I have to undestand the best way to plug them into eCos.
At the moment I have a package that is situated in my local tree in
I thought magic as a device. It works, but I'm absolutely not sure that is
the right thing to do.
We have developed (work done by atmel China) an ecos driver also for the USB
(philips isp1181) included in the JTST; but I must check if we can
distribute the sources..
At the moment all JTST in the world have Redboot installed in flash and run
obviously eCos applications.

Here two links to jtst datasheets:

thank you for your patience and attention.
best regards.

> ------- Additional Comments From  2004-17-09
12:56 -------
> #define RUNMAGIC
> +#define WAITSYSTEM jtst_wait_magic();
> +
> RUNMAGIC should really be HAL_RUNMAGIC, and WAITSYSTEM should be
> Also jtst_wait_magic() would be better as cyg_hal_jtst_wait_magic(). These
> all name space polution issues. Some comments to what these do would also
be good.
> Again, it does not fit the naming convention and its not clear what its
for. Its
> not used anywhere else in the code. Is it trying to say the USB is using
> interrupt 24? If do i would call this something like
> +.macro __todo
> +  ldr     r0,=AT91_PIO
> +  ldr     r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27|BIT3
> +  str     r1,[r0,#AT91_PIO_SODR] // set this bit must be always 1,
otherwise resets
> +  ldr     r1,=BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27|BIT3
> +  str     r1,[r0,#AT91_PIO_OER]   // set to output
> A better name for this macro would be good.
> +
> +#define CYGNUM_HAL_INTERRUPT_TIMER0            1
> +#define CYGNUM_HAL_INTERRUPT_TIMER1            2
> +#define CYGNUM_HAL_INTERRUPT_TIMER2            3
> Does this use the same interrupt controller as the other at91 chips?
> From what i remember from reading a  data sheet yesterday, interrupt 0 is
> the FIQ, and 1 is reserved? Does this chip do something different?
> There are a few places where the white spacing looks wrong. Please could
> expand all tabs to spaces.
> Like i said before, overall it looks good, just some minor issues to tidy
> ------- You are receiving this mail because: -------
> You are the QA contact for the bug, or are watching the QA contact.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]