[ECOS] Strange DSR assertion on STM32

[Manuel Borchers <manuel at matronix dot de>]

Hi all,

I'm currently fiddling a bit around with a STM32 board. It's called
STM32 MINI and I got it over eBay from China. I used the STM3210E port
and modified to the memory-layout to this board (basically no external
SRAM, different serial flash [which I'm not using right now]).

I'm using the attached LCD (ILI9325 through a framebuffer API driver I
wrote) together with an AMB8420 wireless chip.

The stack fÃr the wireless chip is built using two threads. One is
handling received chars over the serial line through a statemachine to
decode the protocol and the other thread is processing completed
packets. Communication between them is done through mailboxes.

A sensor node transmits every 1.2 s a packet containing some data. The
system was running for 30 mins or so and then I got an assertion:

AMB8420: Process Rx char: Requesting new packet.
AMB8420: Process Rx char: Got one.
AMB8420: Process Rx char: Packet queued for processing.
AMB8420: Process thread: Got a packet.
AMB8420: Rx packet data: 0x02 0x81 0x10 0x01 0x01 0x02 0x00 0xff 0x00 0x01 0xee 0x01 0x02 0xa1 0x04 0xf0 0x96 0x01 0x00 

Up to here this is debug output of the last packet correctly received.

diag_printf seems to start to print out the debug statement of the next packet arriving and then the ASSERTION is raised:

AMB8420: PrASSERT FAIL: <4>intr.cxx[292]void Cyg_Interrupt::post_dsr() DSR list is not empty but its head is 0
ASSERT FAIL: <4>intr.cxx            [ 292] void Cyg_Interrupt::post_dsr()                                                                      0
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>mutex.cxx           [ 381] void Cyg_Mutex::unlock()                                                                             {{entr
TRACE: <4>sched.cxx           [ 723] void Cyg_SchedThread::disinherit_priority()                                                            {{er
TRACE: <4>sched.cxx           [ 646] void Cyg_SchedThread::clear_inherited_priority()                                                         {r
TRACE: <4>sched.cxx           [ 646] void Cyg_SchedThread::clear_inherited_priority()                                                         }!
TRACE: <4>sched.cxx           [ 723] void Cyg_SchedThread::disinherit_priority()                                                            }}R!
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                              {{er
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                                {d
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                                }d
TRACE: <1>mlqueue.cxx         [ 841] Cyg_Thread* Cyg_ThreadQueue_Implementation::dequeue()                                                  }}r0
TRACE: <4>mutex.cxx           [ 446] void Cyg_Mutex::unlock()                                                                             }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd
TRACE: <4>sched.cxx           [ 140] static void Cyg_Scheduler::unlock_inner()                                                            {{entr
TRACE: <4>sched.cxx           [ 298] static void Cyg_Scheduler::unlock_inner()                                                            }}retd

Scheduler:

Lock:                0
Current Thread:      AMB8420 Rx thread

Threads:

         Idle Thread pri =  31 state =      R id =   1
                     stack base = 20005b90 ptr = 200061f4 size = 00000800
                     sleep reason     NONE wake reason     NONE
                     queue = 00000000      wait info = 00000000

                main pri =  10 state =   U    id =   2
                     stack base = 200064e8 ptr = 200082fc size = 00002000
                     sleep reason     NONE wake reason     NONE
                     queue = 00000000      wait info = 00000000

        Display main pri =  10 state = S      id =   3
                     stack base = 20000df0 ptr = 20001bac size = 00000f50
                     sleep reason    DELAY wake reason     NONE
                     queue = 00000000      wait info = 00000000

   AMB8420 Rx thread pri =   9 state =      R id =   4
                     stack base = 20001e08 ptr = 20002b4c size = 00000f50
                     sleep reason     NONE wake reason     DONE
                     queue = 00000000      wait info = 00000000

AMB8420 Process thread pri =  10 state = S      id =   5
                     stack base = 20002e08 ptr = 20003bbc size = 00000f50
                     sleep reason     WAIT wake reason     NONE
                     queue = 20008fc4      wait info = 00000000


As the current thread is the Rx thread, I guess this comes out of the
DSR of the serial driver, which is the unmodified STM32 serial driver.

The Rx thread's main loop is quite simple:

while(s_fSerialInitialized)
{
	recv_len = sizeof(cyg_uint8);
	err = cyg_io_read(s_hSerialPort, (void*) &recv_char, &recv_len);

	if( (ENOERR == err) && (recv_len != 0) )
	{
		amb8420_process_rx_char(recv_char);
	}
}

amb8420_process_rx_char implements the statemachine for the protocol
(and posts the packets to the corresponding mailboxes on completion).

Any ideas or hints where this could come from? I'm a bit confused as I
didn't touch any driver using ISRs/DSRs. The only thing is my wireless
stack which runs in two threads and the LCD driver, which doesn't use
any IRQs at all (simple memory-mapped display with a command and a data
register).

Any help appreciated!

Cheers,
Manuel

-- 
Manuel Borchers

Web: http://www.matronix.de
eMail: manuel@matronix.de

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