Re: [ECOS] STM32 interrupt definitions

[Chris Holgate <chris at zynaptic dot com>]

On Mon, 2008-11-24 at 13:57 +0100, Simon Kallweit wrote:
> Hi
> 
> Chris Holgate discovered a little inconsistency in the interrupt vector 
> definitions, we have:
> 
> #define CYGNUM_HAL_INTERRUPT_DMA0_CH1           
> (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
> #define CYGNUM_HAL_INTERRUPT_DMA0_CH2           
> (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
> ...
> 
> and
> 
> #define CYGNUM_HAL_INTERRUPT_DMA2_CH1           
> (56+CYGNUM_HAL_INTERRUPT_EXTERNAL)
> #define CYGNUM_HAL_INTERRUPT_DMA2_CH2           
> (57+CYGNUM_HAL_INTERRUPT_EXTERNAL)
> ...
> 
> In the STM32 reference manual the first set is named only DMA, the 
> second set DMA2, which seems inconstant too. Can we agree to call them 
> DMA1/DMA2?

I suspect that this is probably a typo in ST's list of interrupt
vectors, since elsewhere in the reference document the two DMA
controllers are consistently referred to as DMA1 and DMA2.

On a related note, in my current DMA register map I've used the
following definitions for accessing the per-channel registers:

#define CYGHWR_HAL_STM32_DMA_CCR(__x)           (0x14*(__x)-0x0C)
#define CYGHWR_HAL_STM32_DMA_CNDTR(__x)         (0x14*(__x)-0x08)
#define CYGHWR_HAL_STM32_DMA_CPAR(__x)          (0x14*(__x)-0x04)
#define CYGHWR_HAL_STM32_DMA_CMAR(__x)          (0x14*(__x))

This allows me to use a common DMA setup function, parameterised by
channel number.  The question is whether this type of thing is
considered bad form or too obtuse to be included in the main register
map.

Chris.


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