[ECOS] Cortex M3 interrupt handling & context switching

["simon dot kallweit at intefo dot ch" <simon dot kallweit at intefo dot ch>]

Hi everyone

Despite all the kernel tests running perfectly, my interrupt handling 
still does not work properly, and I'm really starting to pull my hair 
out! The problems arised when testing the serial driver, which still 
cause hard faults I'll try to explain my current strategy for interrupt 
handling, which obviously is still wrong. Nick, I would be very glad if 
you could give me some pointers, as I think I'm not far from a working 
solution. May be wrong though. Btw. how is your cortex port coming 
along? Any prediction on a release date?

So, here is how my interrupt handling and context switching basically works:

* I configure the SVC exception with highest priority, and the PendSV as 
lowest priority, so it only gets called after all other 
interrupts/exceptions have been executed.
* The SVC call is basically used for context switching, calling the SVC 
automatically stores/restores some of the registers (on entering/leaving 
the exception). Inside the SVC exception I store/restore additional 
registers, as well as the base priority and the system handler control 
and state register. HAL_THREAD_SWITCH_CONTEXT is a simple SVC call, 
nothing more.
* Interrupt/exceptions are basically handled like this: On entering, 
interrupts are disabled, PendSV is posted and the scheduler lock is 
incremented (only if we entered the exception from thread mode). Next 
interrupts are enabled again, and the corresponding interrupt handler is 
called. Just before calling interrupt_end the scheduler lock is 
incremented once again, to prevent an immediate context switch during 
exception handling. After all interrupts are handled the PendSV 
exception is entered, doing a simple call to cyg_scheduler_unlock, and 
possibly calling the SVC exception to do a context switch.

This seems to work fine as long as only the SysTick is running. Trouble 
emerges when other interrupts interfere, resulting in possible hard 
faults when returning from the SVC exception. I suspect the problem is 
that the SVC can either return to the running thread or the PendSV 
exception, which does not correspond to the same state of the system 
handler. I hoped that I did take care of that by storing/restoring the 
system handler control and state register to the thread's stack during a 
context switch (this is also mentioned in the cortex-m3 manual). Any 
ideas why this could fail? I can give more details on the implementation 
if necessary.

I would be really grateful for any advice, as I tried lots of different 
strategies and did still not come up with a working solution. I'm really 
eager to understand whats going wrong and get it right, but I don't yet 
see a solution.

Simon



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