RE: [ECOS] FW: [ECOS] Is eCos running any background process?

["Paul D. DeRocco" <pderocco at ix dot netcom dot com>]

> From: Chris Zimman
>
> Turning off interrupts for a short period of time and polling may
> be the only
> way to guarantee the operation for this application.  We had a somewhat
> similar problem a few years back, and we had to disable
> interrupts during a
> critical write to meet timing requirements.
>
> Even if he was running at 180MHz, assuming perfect conditions
> otherwise and
> no external bus accesses, 4.72uSec is only about 850 clock cycles.  That
> doesn't leave a ton of overhead for an interrupt driven approach.

I haven't tallied them up, but I'd be surprised if it took anything like 850
clocks for the timer ISR to post the timer DSR, as long as all the
instrumentation crap is turned off. And it's certainly enough to read a byte
and stuff it into a buffer.

But there's still another way with the ARM, which is to use FIQ. FIQ is good
for really short handlers hand-crafted in assembly language, which perform
the function of a smart DMA controller, using only the few shadow registers
swapped by the FIQ. Such a handler can safely interrupt ISRs, as long as it
doesn't make _any_ system calls (including posting a DSR), but for this to
work well, the HAL_DISABLE_INTERRUPTS macro would have to be modified not to
mask FIQ. (I think that's a design flaw in the ARM HAL, by the way.)

--

Ciao,               Paul D. DeRocco
Paul                mailto:pderocco@ix.netcom.com


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