This is the mail archive of the
ecos-discuss@sourceware.org
mailing list for the eCos project.
Re: Cortex-M3 interrupt handling & context switching
- From: Keith Ross <kross at elands dot co dot nz>
- To: ecos-discuss at ecos dot sourceware dot org
- Date: Tue, 07 Oct 2008 21:46:04 +1300
- Subject: [ECOS] Re: Cortex-M3 interrupt handling & context switching
- References: <1223329271.1446.ezmlm@ecos.sourceware.org>
- Reply-to: kross at elands dot co dot nz
Simon Kallweit wrote:
... I'm again faced with the proper implementation of interrupt
handling and context switching. I'm still a bit puzzled, and would
really appreciate some help, if anyone knows a bit of the Cortex-M3
architecture and the ecos kernel. I would like to use the Cortex's
feature of saving/restoring some of the processors state automatically
when entering/leaving exceptions (namely pc, lr, r12, r0-r3)....
Sorry Simon, I've had a look at the manual and your code. But I haven't
written any code.
I'll continue to plod though it but without JTAG I can't check any code.
The people from ST could be well placed to do this bit (?) or maybe one
of the people who put there hand up for the cortex port in the past.
Simon, your code outline sounds good. I'll look into this a little more.
Keith
--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss