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cache configuration for 946es
- From: "Sinan KAYA" <sinan dot kaya at siemens dot com>
- To: <ecos-discuss at ecos dot sourceware dot org>
- Date: Mon, 4 Dec 2006 16:32:31 +0200
- Subject: [ECOS] cache configuration for 946es
Hi,
i have a 946es variant and i'm unable to pass kcache2 test even though
other cache tests, cache and kcache1 pass.
I googled a little bit. Previous posts say that this test is designed to
find misconfigurations. So, i assume i have a misconfiguration. The
document of board tells me that i have 8 kb instruction cache, 4kb data
cache with four way associative set and 1024 byte segments.
Each segment consists of 32 lines with 32 ( 8 x 4 bytes) bytes.
and here is my configuration
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM946ES)
# define HAL_ICACHE_SIZE 0x2000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS
(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x1000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS
(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 32
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x400
can anybody see a mistake?
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