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Re: Hard-Realtime behaviour


On Tue, May 30, 2006 at 02:36:05PM +0530, R Vamshi Krishna wrote:
> 
> Continuing on the discussion, doesn't pipelining on modern processors add 
> to our woes. Because then we cannot really determine if a particular 
> instruction is going to 'x' cycles or 'y' cycles.

Realy you need to talk to the silicon vendor, or at least read the
data sheet and see what it says.

However I think pipelining in itself should not be a problem.  It
should be deterministic under normal conditions. Only when things go
wrong will it be none deterministic, ie interrupts, exceptions, cache
misses is you have caches enabled. 

If you are on a processor with HT like technology then i expect the
pipeline becomes none deterministic unless you disable all other
"processors".

Really, if you are worried about this level of detail, you probably
should be using a Z80, or some similar level of processor technology,
where you know what it is doing.

      Andrew

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