[ECOS] In-order exection of I/O on PowerPC 60x

[Peter Graf <p dot graf at itknet dot de>]

Hi,

when debugging an I/O problem using an MPC603e series chip (Freescale
MPC5200) under eCos, I stumbled upon a more general issue which may
affect the PowerPC 60x under eCos in general.

The original I/O problem was a very seldom occurence of character loss
when receiving data from a FIFO. After checking other possible causes,
we could only explain the problem if the FIFO hardware was broken or the
CPU had executed two _read_ accesses to external hardware in the wrong
order. (Unfortunately, in our case, the 'external' hardware was on-chip,
so we couldn't measure things electrically).

The eCos macros used for I/O access, HAL_READ_UINT8 and HAL_READ_UINT16,
place an HAL_IO_BARRIER() after the access, which is translated to the
PowerPC assembler instruction eieio.

A closer look the Freescale documentation (MPCFPE32B/AD REV2, page 8-52)
shows that the eieio instruction is only guaranteed to affect memory
_reads_ if the memory is both "caching inhibited" and "guarded".

Our HAL, as well as the other eCos 60x platforms I've looked at, only
initializes the I/O areas as "caching inhibited", but not as "guarded".
This means that eieio only ensures that preceding memory _writes_ have
completed. There is no guarantee for _reads_.

When I placed a sync instruction between the critical read accesses,
instead of eieio, our problems disappeared. (The sync instruction covers
reads even if memory is not marked as "guarded".)

This leads me to the question wether the implementation of the HAL_READ_
macros and/or the MMU initializations should be changed, so in-order
execution of reads is guaranteed?

(I am aware that there are only rare situations where an actual problem
will pop up. Firstly, most hardware is only critical for in-order
execution of writes, not reads. Secondly, there must be special
circumstances where the accesses are actually disordered.)

Any comments welcome. Thanks,
Peter

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