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Generic Serial Driver / PXA26X
- From: Andy Atkinson <andya at hydrix dot com>
- To: ECOS Newgroup <ecos-discuss at sources dot redhat dot com>
- Cc: andya at hydrix dot com
- Date: 22 Dec 2005 15:37:15 +1100
- Subject: [ECOS] Generic Serial Driver / PXA26X
I am looking for some help with a problem related to the eCos generic
serial driver and/or Intel PXA26X UART. It's rather baffling or I we are
missing something really obvious - perhaps you can help???????
We have been quite happily using the generic driver and UART to receive
but we are running into problems when transmitting. Sometimes with large
packets (4K) and sometimes small packets (50 bytes), but every once in a
while the Tx just stops. A lot of time has been spent investigating this
problem using eCos kernel instrumentation and the conclusion is somewhat
suprising. It looks like the UART is not always generating an interrupt
when the FIFO is half-empty or less.
The evidence to support this is as follows. We have flow control turned
off and we write a single block of data large enough to fill the BT-UART
buffer exactly. We then wait for this data to be sent by polling the
tx_count of the buffer info. If the data is not sent after 1 second
(plenty of time at 115.2Kb) then we dump the instrumentation log and the
contents of the interrupt and BT-UART regsiters.
The log shows us that we have stopped writing in xmit_char (serial.c) as
the FIFO is full. When this occurrs we should receive an interrupt when
the UART LSR=0x20 (THR/FIFO is ready for more data). What we actually
find is that the LSR=0x60 (both the TSR and the THR/FIFO are empty) but
no interrupt has been generated. Also there is no UART interrupt pending
(ICIP = 0x00000000) yet the IER = 0x5F (all UART interrupts are enabled)
and the interrupt is not masked (ICMR=04700480 and BT-UART is bit 21).
Up until the point of Tx stopping, the number of Tx interrupts raised =
the number of Tx interrupts serviced = the number of Tx DSRs serviced so
we do not appear to have problems servicing the UART interrupts.
So the question is, how can one have:
a) the UART interrupt unmasked, and
b) FIFO Tx interrupts enabled, and
c) the THR and TSR are empty, and
d) no interrupts pending, and
e) serial buffer (IO layer) contains data to be written.
There is a problem somewhere. Can anyone help???
For info, registers when tx fails:
024.1500: h/main.cpp: 204: main: ICIP=00000000
024.1600: h/main.cpp: 205: main: ICMR=04700480
024.1600: h/main.cpp: 206: main: ICLR=00000000
024.1700: h/main.cpp: 207: main: ICFP=00000000
024.1700: h/main.cpp: 208: main: ICPR=00000000
024.1800: h/main.cpp: 209: main: ICCR=00000001
024.1800: h/main.cpp: 211: main: *** BT-UART Registers: ***
024.1800: h/main.cpp: 212: main: IER=0000005F
024.1900: h/main.cpp: 213: main: IIR=000000C1
024.1900: h/main.cpp: 214: main: LSR=00000060
024.2000: h/main.cpp: 215: main: FCR=000000C1
024.2000: h/main.cpp: 216: main: MSR=00000010
Any help is greatly appreciated as this problem is compromising our
product stability right now.
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