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Re: Re: PCI driver development for NI-DAQ PCI-DIO-96 card
- From: David Brennan <eCos at brennanhome dot com>
- To: Gary Thomas <gary at mlbassoc dot com>
- Cc: Khateeb <abdullahkhateeb at gmail dot com>, eCos Discussion <ecos-discuss at ecos dot sourceware dot org>
- Date: Fri, 02 Dec 2005 08:43:55 -0800
- Subject: Re: [ECOS] Re: PCI driver development for NI-DAQ PCI-DIO-96 card
- References: <email@example.com> <1133514628.3791.10.camel@hpl_gary>
Gary Thomas wrote:
Note: you should really send this to proper email addresses and notI think your problem is i386 platform specific. the
HAL_(READ|WRITE)_UINT(8|16|32) calls actually use ISA port space not PCI
memory space. I think you need to use the
HAL_(READ|WRITE)MEM_UINT(8|16|32). I thought there was a flag in the BAR
register to indicate if the memory is port mapped or memory mapped. But
it has been a long time since I looked at that.
individuals. The address you have for the eCos discussion list was
incorrect and at least one of the other email addresses is extremely
out of date (firstname.lastname@example.org hasn't been used since spring of
Please keep your replies on this list as [further] private emails
will be ignored.
On Fri, 2005-12-02 at 10:22 +0500, Khateeb wrote:
We are trying to write a PCI device driver for NI-DAQ PCI-DIO-96 card
The target platform is intel P4 processor/mother-board.
The host system is an intel pentium P3 PC running windows XP.
I have successfully detected the device using the device-id.
The device info structure read from the PCI configuration space header
status register = 0x280
class + revision = 0xff000000
cache line size =0x10
latency timer =0x10
Built-in Self-Test =0x0
Num of BAR=0x2
I am assuming that the Base_Address corresponds to BAR(0) and
Base_Address corresponds to BAR(1). I have tried to write on these
registers through 'HAL_WRITE_UINT32' command but i haven't been
successful in that since reading those registers again gives the same
previous values of
using the read command which is 'HAL_READ_UINT32'.
Does your device actually respond to 32 bit accesses when using BAR(1)?
Your code (below) doesn't look obviously wrong to me, but you need to
know the characteristics of the device "behind" the PCI interface.
The basic probelm lies in configuring the base address and finding an
appropriate offset; which so far i have not been able to do so. I have
taken help from the PCI sample programs 'pci1.c' and 'pci2.c'.
// Writing data to the memory allocated to BAR
// Basically trying to access the devices registers so
// that we can program the 8255 Chip.
for(i = 0; i <= 16; i++)
diag_printf(" count[%d]=%04x \n", i, tempVal);
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