[ECOS] Re: MPC565-memory

[<bob dot koninckx at o-3s dot com>]

The port width is configurable in the OR/BR registers. I'd 
start checking these.

Bob

---- Original message ----
>Date: Wed, 5 Oct 2005 10:06:37 +0200
>From: "Boterman, R.L.H. \(Ronald\)" 
<ronald.boterman@tno.nl>  
>Subject: MPC565-memory  
>To: <bob.koninckx@o-3s.com>
>Cc: <ecos-discuss@sources.redhat.com>
>
>   Hello,
>
>    
>
>   I have a question regarding the chip select (CS*) on
>   the MPC565 PowerPC.
>
>   I need to use the chip select to communicate with an
>   external device. I've configured the OR3 and BR3
>   registers  for a memory range: from 0xD000 0000 till
>   0xD000 FFFF. (should be enough for my purpose)  
>
>   BR3 = 0xD000 0003
>
>   OR3 = 0xFFFF 0000
>
>   Using this config and writing to an address in the
>   range, CS3 will be asserted. 
>
>   Only I've encountered a problem: When writing to a
>   memory space in the defined range, not only the data
>   on the address which is written changes, but whole
>   columns of data change along.
>
>   Example:
>
>   Writing 0xFF to address 0xD000 000, will also affect
>   other memory ranges. There isn't even a pattern to
>   the changes.   
>
>   The data which is asserted on DATA[0:16] by the
>   Memory Controller does not make any sense.
>
>    
>
>   My questions are:
>
>   How can I configure the memory space so that every
>   byte can be written separately?
>
>   What should be asserted on the data and the address
>   bus by the Memory Controller?
>
>    
>
>   For questions or ramarks i'm rechable at
>   +31152696464
>
>    
>
>   I hope you can help me with my problem.
>
>    
>
>   Best regards
>
>    
>
>   Ronald Boterman
>
>   This e-mail and its contents are subject to the
>   DISCLAIMER at
>   http://www.tno.nl/disclaimer/email.html

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