This is the mail archive of the
ecos-discuss@sources.redhat.com
mailing list for the eCos project.
MIPS interrupts
- From: Sebastian Uchman <uchman at ihp-microelectronics dot com>
- To: ecos-discuss at ecos dot sourceware dot org
- Date: Thu, 8 Jul 2004 16:32:17 +0200 (MET DST)
- Subject: [ECOS] MIPS interrupts
- Reply-to: Sebastian Uchman <uchman at ihp-microelectronics dot com>
Hello all,
I got few questions about MIPS32 4Kc on Malta Board:
I would like to use Real Time Clock to generate interrupts.
I set the compare register on a value (0x0000ffff). Then the count register
become the value 0x0000ffff (while it runs), and the cause register shows
0x00008000 and the status 0x1000ff03. But it does nothing. It should go to my
ISR but nothing happens.
What does MIPS do when an interrupt occurs?
Where does it go first?
Where should be placed my ISR?
Are there any other register ,which should be set or unset?
greetings
sebastian uchman
--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss