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RE: question about isr function signature (profiling)


Andrew:

Thanks for your response.

I have some more questions.

1, If the signature of the isr is correct, why in the documents it is always
said to define a isr like:

cyg_uint32
isr_function(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_bool_t dsr_required = 0;

    .

    return dsr_required ? CYG_ISR_CALL_DSR : CYG_ISR_HANDLED;
}

In this signature, there are only two parameters, not three. I am wondering
if this is an undocumented feature, or maybe I am missing something here.


2, From your comment, I understand the pc value is for the *next*
instruction. My question is, even though, do I get the correct pc value(the
pc value saved by the interrupt) by the means in my code?


Thanks for your insight.

Yuxin

> -----Original Message-----
> From: ecos-discuss-owner@ecos.sourceware.org
> [mailto:ecos-discuss-owner@ecos.sourceware.org]On Behalf Of Andrew Lunn
> Sent: Saturday, March 27, 2004 1:29 PM
> To: Yuxin Jiang
> Cc: Ecos-Discuss
> Subject: Re: [ECOS] question about isr function signature (profiling)
>
>
> On Fri, Mar 26, 2004 at 05:30:25PM -0500, Yuxin Jiang wrote:
> >
> > For ARM7TDMI core, I want to define a ISR service routine, as following:
> >
> > // ISR.
> > static cyg_uint32
> > timer_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data,
> HAL_SavedRegisters *regs)
> > {
> >
> >     HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_PROFILE_TIMER);
> >     __profile_hit(regs->pc);
> >
> >     return CYG_ISR_HANDLED;
> > }
> >
> >
> > My question is: is the signature for the timer_isr correct?
>
> It looks correct.
>
> > To be specific, is it correct to declare that there is a third
> parameter for
> > a isr, and this third parameter is a pointer to the HAL_SavedRegisters
> > structure, and the structure has correct (updated) context
> registers value
> > at the moment the interrupt occurs?
> >
> > As you can see, I am trying to do profiling. But I am not sure
> I actually
> > get the correct pc value passed into the __profile_hit() function call.
>
> For ARM the PC will be for the next instruction to be executed, not
> the interrupted instruction. It could also be wrong when the
> instruction just executed was a branch.
>
>       Andrew
>
> --
> Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
> and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
>
>


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