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Re: mips interrupt question


"Andy Dyer" <adyer@righthandtech.com> writes:

> Another related question on mips interrupts:
> 
> in packages/hal/mips/arch/v2_0/include/platform.S I see the following:
> 
> 
> #ifndef CYGPKG_HAL_MIPS_INTC_DECODE_DEFINED
> 	.macro	hal_intc_decode vnum
> 	mfc0	v1,status		# get status register (interrupt
> mask)
> 	nop				# delay slot
> 	mfc0	v0,cause		# get cause register
> 	nop				# delay slot
> 	and	v0,v0,v1		# apply interrupt mask
> 	srl	v0,v0,10		# shift interrupt bits down
> 	andi	v0,v0,0x7f		# isolate 6 interrupt bits
> 	la	v1,hal_intc_translation_table
> 	add	v0,v0,v1		# index into table
> 	lb	\vnum,0(v0)		# pick up vector number
> 	.endm
> #endif
> 
> 
> The 0x7f mask applied to v0 after shifing down is one bit too
> large allowing one bit of a reserved field cause[16] into the index
> of the hal_intc_translation_table and possibly indexing beyond the end
> of the hal_intc_translation_table.

Hmm, yes you seem to be right here. The comment gets it correct, so
I'm surprised that the code has been wrong for so long. Of course that
extra bit has always been zero so far, but it may not be forever.

Unless someone shouts I'll change this to 0x3f in the next day or so.


-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts


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