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Re: Redboot-GDB
- From: "Michael Anburaj" <embeddedeng at hotmail dot com>
- To: nickg at ecoscentric dot com, msalter at redhat dot com
- Cc: ecos-discuss at sources dot redhat dot com
- Date: Wed, 25 Jun 2003 05:58:05 +0000
- Subject: Re: [ECOS] Redboot-GDB
- Bcc:
Hi Nick/Mark/All,
You can test the basic GDB stub entry/exit handling by typing:
$k#6b
I was about to try this with the redboot build from the current cvs source,
but Redboot was dying while the context was switched to reach trampoline()
of redboot\current\src\main.c after receiving ?$?.
After much debugging I found that in hal_thread_load_context at the last
instruction ?movs pc,lr? the SPSR (with I bit cleared) was moved to the
CPSR. Thus enabling the IRQs. At this point the ECOS-RTC (tick timer)
interrupt was pending & because of which the flow never reached
trampoline(). This may be the reason for my other problem too.
Questions (please let me know, which is right & which is not):
1. Is this ok? Can the flow, while switching to trampoline() be interrupted?
If this is normal, then I need to debug further to find why it did not
resume after the ECOS-RTC interrupt was serviced.
2. I believe the ECOS-RTC (tick timer) interrupt got unmasked at
hal_clock_initialize(). hal_clock_initialize() getting called in Redboot at
this point; is it normal?
3. hal_clock_initialize() starts the timer & unmasks the interrupt (from
this point the timer can generate ARM-IRQs, provided the I bit in CPSR is
low). Is this right? Or should hal_clock_initialize() not unmask the timer
interrupt.
4. The following lines in hal_thread_load_context of context.s moves 0x13
(with I & F bits low):
ldr r0,[fp,#armreg_cpsr]
msr spsr,r0
Is this right? Or should the I & F bit be high, disabling the IRQs before
shifting control to trampoline()?
Please comment on these questions, so that I can solve this issue...
Thanks a lot & Cheers,
-Mike
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