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nested interrupt question


Dear All,

in ecos 's file vectors.s of arm arch,I have a question about IRQ nested interrupt :
IRQ:
// Note: I use this exception stack while saving the context because
// the current SP does not seem to be always valid in this CPU mode.
ldr sp,.__exception_stack // get good stack
stmfd sp!,{r0-r5} // save some supervisor regs
sub r0,lr,#4 // PC at time of interrupt
mrs r1,spsr
mov r2,#CYGNUM_HAL_VECTOR_IRQ
mov r3,sp

handle_IRQ_or_FIQ:


mrs r4,cpsr // switch to Supervisor Mode
bic r4,r4,#CPSR_MODE_BITS
orr r4,r4,#CPSR_SUPERVISOR_MODE
msr cpsr,r4***********************************************NOTE!
.....
here, switch to svc mode,so enable interrupt, if interrupt occur at this time, r0-r5 stored in _exception_stack was corrupted,new r0-r5 will be pushed into _exception_stack.so last interupt failed to restore.right?
my key question is that:
1) when interrupt can come again after cpsr updated? Is it immediately?
2)how to process it to avoid possible problem just like above?


maybe I make mistakes,please help me?


BRS/johnsonest


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