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SH3 77x9SE01 bug
- From: Rod Campbell <rodc at sigmaelectronics dot com>
- To: ecos-discuss <ecos-discuss at sources dot redhat dot com>
- Date: 24 Apr 2003 18:05:27 -0400
- Subject: [ECOS] SH3 77x9SE01 bug
- Organization: Sigma Electronics
While attempting to build support for the 7729R, I found what I think is
a bug in the existing 77x9SE01 platform. I am using eCos V 2.0b1
The setting for the oscillator control Divider2 divide-by-6 is
incorrect. This causes an illegal FRQCR value to be built and you won't
get a reliable boot up from reset (I could get the system to boot about
1 out of 25 times). Also, the SCIF2 serial port won't work (bad baud
rate generation because of incorrect peripheral clock value).
In /packages/hal/sh/sh3/v2_0b1/include/mod_regs_cpg.h
For the V3 (last) group of conditional compilation statements,
following the statement #elif (CYGHWR_HAL_SH_00C_DIVIDER_2 == 6)
change from: # define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2002
to: # define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2001
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