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RM7000 interrupt handling
For the mips architecture HAL_INTERRUPT_MASK is defined as
follows;
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
It is possible to get an interrupt between the mfco and mtco.
As long as the status register is not modified as part of
interrupt processing this is not a problem.
Recently the following was added at the end of
_default_interrupt handler in vectors.S
#ifndef CYG_HAL_MIPS_R3900
# Keep the current settings of the IM[7:0] bits within the status
# register. These may be used as interrupt masks, so if an ISR or
# DSR masks interrupts they must be preserved.
# If they are not used, then this does no harm.
ori k0,zero,0xff00
nor k0,k0,k0 # 0xffff00ff
and k1,k1,k0 # all interrupts disabled
mfc0 k0,status # V0 = current SR
nop
nop
andi k0,k0,0xff00 # preserve interrupt set
or k1,k1,k0 # insert into "saved SR"
#endif
Consider the following scenario;
Suppose status register has interrupts 1 & 2 are unmasked
- first half of HAL_INTERRUPT_MASK for interrupt 1 is executed,
r3 has copy of status register with 1 & 2 masked
- interrupt 2 occurs
- ISR masks off interrupt 2 in status register
- interrupt returns; status register has interrupt 1 unmasked
- second half of HAL_INTERRUPT_MASK executes; r3 has interrupt
1 masked, 2 is still unmasked. r3 is copied to status register.
We have just lost the masking of interrupt 2.
Does this make sense to people?
--
Chris Morrow YottaYotta Inc. email: cmorrow@yottayotta.com
phone: (780) 989 6814 web: http: //www.yottayotta.com