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RE: cyg_drv_interrupt_create ()
- To: "'Lewin A.R.W. Edwards'" <larwe at larwe dot com>
- Subject: RE: [ECOS] cyg_drv_interrupt_create ()
- From: "Trenton D. Adams" <tadams at extremeeng dot com>
- Date: Fri, 22 Jun 2001 09:00:16 -0600
- Cc: <ecos-discuss at sources dot redhat dot com>
- Organization: Extreme Engineering
> -----Original Message-----
> From: Lewin A.R.W. Edwards [mailto:larwe@larwe.com]
> Sent: Friday, June 22, 2001 8:54 AM
> To: Trenton D. Adams
> Cc: ecos-discuss@sources.redhat.com
> Subject: RE: [ECOS] cyg_drv_interrupt_create ()
>
> > > interrupt table. The ARM processor only has one IRQ and
> one FIQ pin
> > > and on most boards these lines are connected to an interrupt
> > > controller (this may be part of a chip with an
> >
> >I'm counting three interrupt lines, and an FIQ line myself.
> Does this
> >most likely mean that I will have to add the handling for
> the interrupt
> >that I'm using?
>
> The CL-EP7312 has (at a quick count) 22 interrupt sources;
> five are routed
> to FIQ (EXTFIQ pin, battery low, watchdog, media change
> [pin], and DAI) and
> the remainder are routed to IRQ (CODEC, the three EINT pins,
> TC1 underflow,
> TC2 underflow, real-time alarm, 64Hz tick, UART1 Tx FIFO
> empty, UART1 Rx
> FIFO full, UART1 status change, SSI1 end of transfer, key
> press (PORTA
> activity), SSI 16-byte Rx, SSI 16-byte Tx, UART2 Tx FIFO
> empty, UART2 Rx
> FIFO full).
So you're saying that there are acutally only one IRQ, and one FIQ, but
there are three EINT pins?