RE: [ECOS] Bug in PPC 405 target.

[Gary Thomas <gthomas at cambridge dot redhat dot com>]

On 04-May-2001 Dennis Ehlin (ECS) wrote:
> Hi,
>  
> The option "CYGHWR_HAL_POWERPC_VECTOR_BASE  (0xfff00000 or 0x00000000)" 
> doesn't work as intended on the PPC405GP and (i think also the PPC403).
>  
> Because the MSR_IP bit is not valid for changing the exception vector offset (The IP_BIT is
> actually marked as reserved in the MSR register).
> Instead the EVPR register should be used.
>  
> It would be great if I could fix this, but I'm not sure how to tackle the problem, because if I
> change something in the
> "powerpc/arch/current/src/vectors.S" file the changes will affect all PPC targets, and that is
> not what I want, and
> also the cdl file for the PPC arch needs to be changed to allow setting of other exception vector
> offsets than 0x00000000 and 0xfff00000 for the PPC40x targets.
>  
> "User's Manual page 95"
>  
> 23:25 Reserved
>  
> "User's Manual page 884"
> EVPR
> 
> Exception Vector Prefix Register
> 
> SPR 0x3D6
> 
> See "Exception Vector Prefix Register (EVPR)" on page 10-30.
> 
> Figure 25-13. Exception Vector Prefix Register (EVPR)
> 
> 0:15 EVP Exception Vector Prefix 16:31 Reserved
> 
> //Dennis

All of what you point out is true.  However, the code currently only
works with the exception vectors set to 0x00000000.  See the setup
in hal/powerpc/ppc40x/current/include/variant.S.  This code would be
the place to change things around if you really wanted the vectors
to be somewhere else.  Also, the exception decode would be affected.

Is there some reason that you want the vectors somewhere other than 0x0?
Don't forget that eCos is set up to "create" the vector handling space
by copying the appropriate vector code (VSR) to the interrupt vector
table.