Re: [ECOS] PCI Interrupts A-C on IQ80310

[Mark Salter <msalter at redhat dot com>]

>>>>> Vince Bridgers writes:

> I'm using a device that only wants to signal interrupts on PCI INTA on the
> Iq80310. As those of may know, the Iq80310 does not signal INTA through INTC
> on the PCI bus, although IRQ on the ARM is signaled when one of those
> interrupts occurs.

> I found the module that identifies the interrupt sources and calls the
> correct interrupt handler, assuming the interrupt object has been created
> and attached properly (nirq_ISR in iq80310_misc.c). The method I've chosen
> is a simple one where the interrupt routines are called, and if the device
> controlled by that module generated the interrupt, the return code is
> CYG_ISR_HANDLED, otherwise I return 0. If handled, nirq_ISR returns,
> otherwise continues through the routine. This seems to work, but does add
> some latency to interrupt processing, as well as adding unnecessary PCI bus
> cycles.

> Does this sound reasonable (given the state of things), or are there other
> methods one could use?

Yes, that sounds like the right thing to do.

> Does anyone know the rationale for the Cyclone board
> design where only interrupt D was signaled in a status register and not A-C?

No.

--Mark