RE: [ECOS] [PATCH] AEB-1C memory SFR settings...

["Perry Wang" <perrywang at nmnc dot com>]

Sorry I just saw the mail from Jonathan Larmour (after the Gary Thomas mail)
about the CVS and aeb-1c.  Please ignore my previous posting regarding CVS.
I will fetch the latest CVS tree and see if the linker script is updated
also.

> -----Original Message-----
> From: ecos-discuss-owner@sourceware.cygnus.com
> [mailto:ecos-discuss-owner@sourceware.cygnus.com]On Behalf Of Jonathan
> Larmour
> Sent: Friday, December 17, 1999 11:36 AM
> To: Srdjan Sobajic
> Cc: ecos-discuss@sourceware.cygnus.com; srdjans@digitalpersona.com
> Subject: Re: [ECOS] [PATCH] AEB-1C memory SFR settings...
>
>
> Srdjan Sobajic wrote:
> > Maybe I missed some obvious way of doing this, but after checking out
> > the memory SFR settings on the AEB-1C I have, the board is configured
> > to use only 128 kB of the available RAM...
>
> I suspect you are using the 1.2.1 release of eCos. That only supports the
> AEB rev B officially.
>
> > So this patch fixes that problem right at startup, and makes the full
> > 256 kB RAM available.
> >
> > If there's a better way of doing this please let me know- but this works
> > for me.
> [snip]
>
> You could try using eCos from anonymous CVS:
> http://sourceware.cygnus.com/ecos/anoncvs.html . That provides support for
> the AEB rev C.
>
> If you look at the code in
> hal/arm/aeb/current/include/hal_platform_setup.h
> you will notice a caveat however:
>
> #ifdef CYGHWR_HAL_ARM_AEB_REVISION_C
> // AEB rev C has 256kB of memory. Cache is working (set cachable)
> #if 0
> #define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00048000,0x00007c04
> #define AEB_BAD  .long  0xFFFFA00C,0x00048000,0x01000000,0x00000000
> #else
> // FIXME: There is a cache problem of some sort. Either eCos or the
> // chip. Leave cache disabled till I find the time to fix it. Jesper
> #define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00048000,0x00007804
> #define AEB_BAD  .long  0xFFFFA00C,0x00048000,0x01000000,0x00000000
> #endif
> #else
> // AEB rev B has 128kB of memory. Cache is broken (clear cachable)
> #define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00028000,0x00007804
> #define AEB_BAD  .long  0xFFFFA00C,0x00028000,0x01000000,0x00000000
> #endif
>
> If anyone has more information on this FIXME, or has time to
> debug it, we'd
> be grateful. Jesper can probably provide details of how the problem showed
> itself (I can't remember off-hand).
>
> Jifl
> --
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