This is the mail archive of the crossgcc@sourceware.org mailing list for the crossgcc project.

See the CrossGCC FAQ for lots more information.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: MIPS SF toolchain

Matej Kupljen wrote:
I think I found the problem.

....

This code is written in sysdeps/mips/setjmp_aux.c in inline assembly. ...

This code is written in sysdeps/mips/__longjmp.c in inline assembly.

Because I am using sf, there is no need to store those
registers, or is it?
Can I just #ifdef this code if compiled for sf?

Other architectures do things like this, e.g.

sysdeps/powerpc/powerpc32/__longjmp-common.S:#ifdef __NO_VMX__

so I don't see why not.

In fact, I had to do something similar once to make life
possible for ppc405.  See

http://kegel.com/xgcc3/glibc-ppc-nofpu.patch3

(Hmm, wonder if something like that ever made it in to
mainline glibc.)

- Dan

--
Trying to get a job as a c++ developer?  See http://kegel.com/academy/getting-hired.html

------
Want more information?  See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/
Want to unsubscribe? Send a note to crossgcc-unsubscribe@sources.redhat.com

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]