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RE: Changing memory segments


> From: Jose Ramirez
> Subject: Re: Changing memory segments
> 
> This sounds like an interesting problem that I may
> have to deal with in the near future...
> 
> Question:
> 
> Why the focus on slower speeds on the ROM? I was under
> the assumption that if the BSP is configured properly,
> FLASH access (I assume you are using FLASH for ROM?)
> time differentials are handled by the OS bsp or CPU.
> This sounds interesting, maybe you could clear that up
> for me.
> 
> What's your CPU? Is it over 2 years old?
>
The CPU is a Hitachi SH2 running at 28 MHz, it has 256K internal 
Flash (no wait states) and 2 to 8 Meg external flash which I use 
mostly for data, but also for those lower priority routines like
diagnostics, serial comms, etc. The external flash has a minimum 
of 1 wait state (and memory access is single cycle) so I end up 
with almost double the effective instruction execution time 
(the pipeline helps a bit).

The same is true for the 4k internal RAM, it is effectively double 
the speed of external RAM, even if the external RAM is fast enough 
to keep up. I am using 80ns RAM so I need to add an additional wait
state to make the external access even slower.

DRAM is slower still, it needs 4 clock cycles to handle the address
multiplexing, plus I need a wait state for slower DRAM.

> Another, 
> Are you using registers for improved performance on
> top of this?
> 

Yes, I am also using a lot of inline functions which increase code 
size but improve speed. There are several applications that run 
comfortably (60% to 70% peak cpu loading) with critical sections of
code in internal Flash and using selected internal RAM that die 
miserably when I try to run from external Flash.

BTW

Another possibility I have started looking at is to generate the Linker 
Script on the fly using SED or even AWK to expand fake macros in a
template link script.

Stan Katz

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