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Joel Dierks wrote: > > Hello > > I am new to the list as well as new to GCC. I know > that GCC does not provide for interrupt handling so > I am asking you all how to handle it. I am writing > code for the Motorola MMC2107. To which Motorola CPU-family the MMC2107 does belong? The Coldfires are MCF5x and the M.COREs are MMC2xxx, so it must be a M.CORE, although I couldn't find any reference into MMC2107 in my M.CORE docs... But I have at least two docs from Motorola which handle the interrupt issues with M.CORE and they were almost the first to meet on the Motorola-site, like the: EFFICIENT INTERRUPT PROCESSING on the M·CORE ARCHITECTURE Class 370", John Vaglica, M·CORE Core Technology Manager, Motorola, Inc., Semiconductor Products Sector. And my GCC has some kind of support for ISRs via the '__attribute__((interrupt))', in some alpha/beta preliminary level: ----------------------- clip ---------------------------- .file "isr_demo.c" gcc2_compiled.: .text .align 1 .export handle_intr .type handle_intr,@function handle_intr: subi sp,32 subi sp,28 stm r1-r15,(sp) lrw r4, count ldw r7,(r4) addi r7,1 stw r7,(r4) ldw r6,(r4) lrw r7,0x190 // 400 cmpne r6,r7 jbt .L3 lrw r5,0xffffd6 // 16777174 ld.b r6,(r5) movi r7,1 xor r7,r6 st.b r7,(r5) movi r7,0 stw r7,(r4) .L3: lrw r6,0xffff67 // 16777063 ld.b r7,(r6) lrw r5,0xfe // 254 and r7,r5 st.b r7,(r6) ldm r1-r15,(sp) addi sp,32 addi sp,28 rte .Lfe1: .size handle_intr,.Lfe1-handle_intr .align 1 .export fatal_quit .type fatal_quit,@function fatal_quit: bmaski r2,32 // -1 0xffffffff jbsr _exit ----------------------- clip ---------------------------- Probably I did some work with tidying those 'noreturn' functions and their prologue/epilogues too, so that 'fatal_quit()' is here too... Ok, the ISR-function prologue: subi sp,32 subi sp,28 stm r1-r15,(sp) and the epilogue: ldm r1-r15,(sp) addi sp,32 addi sp,28 rte are still quite simple... No nested interrupts enabled. The next phase could be to add the support for nested interrupts, ie the following code generated into the prologue, following the scheme in the pp 22-23 in the mentioned document: ----------------------- clip ---------------------------- mfcr epsr,r14 // Get the shadow mfcr epc,r15 // registers where they can be written to memory subi r0,8 // Adjust the stack again stm r14-r15,(r0) // Save the shadow regs // Re-enable Normal Interupts and General Exceptions mfcr r14,psr // Get psr current contents into r14 bseti r14,8 // Re-enable exceptions bseti r14,6 // Re-enable normal interrupts mtcr r14,psr // Move new contents into psr ----------------------- clip ---------------------------- and to add the related code into the epilogue... As seen, this causes overhead and whether this is necessary or not, is the problem... Perhaps there should be two kind of ISRs, those which may be interrupted (using the longer prologue and epilogue) and those which may not (using the simpler ones). And the two attributes "nested_interrupt" and "interrupt" for them... > I mainly need to know how to embed assembly code into C > source files using GCC. The GCC manual and the section "Assembler Instructions with C Expression Operands" in the "Extensions to the C Language Family" should teach this... As always, the manuals are your best friends, if you haven't them, find out where to find them... For instance the Motorola M.CORE GNU-tools distributions used to come with PDF-format manuals. Cheers, Kai ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sourceware.cygnus.com
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