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Hi! I'm writing a back-end to GCC 2.95.2. And after some testing I have run into a problem. cc1 gets signal 11 (SEGV) when compiling some files in newlib. Tracing it down, I have found that the macro PATTERN(x) returns NULL. Is there some cases when PATTERN(x) should return NULL? Down you see the line that causes SEGV. #0 mark_jump_label (x=0x0, insn=0x81d512c, cross_jump=0) at jump.c:3676 3676 register RTX_CODE code = GET_CODE (x); It's called from: #1 0x80d0ee9 in duplicate_loop_exit_test (loop_start=0x8230e90) at jump.c:2749 2749 mark_jump_label (PATTERN (copy), copy, 0); Any clues? I attach my machine descriptor file. -- Johan Rydberg johan.rydberg@netinsight.net Net Insight AB, Sweden direct: +46-8-685 04 17 http://www.netinsight.net phone: +46-8-685 04 00 fax: +46-8-685 04 20
;; or16.md - Machine description for GNU compiler, OpenRISC 16 Version ;; Copyright (C) 2000 Free Software Foundation, Inc. ;; Contributed by Johan Rydberg, <johan.rydberg@netinsight.se> ;; Based upon earlier work done by Damjan Lampret, <lampret@opencores.org> ;; Originaly based upon the elxsi (which was based upon the vax port) ;; and sparc port. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 1, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 59 Temple Place - Suite 330, ;; Boston, MA 02111-1307, USA. (define_attr "type" "unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp" (const_string "unknown")) (define_delay (eq_attr "type" "branch,jump") [(eq_attr "type" "!branch,jump") (nil) (nil)]) ;; ;; Compares ;; (define_expand "cmpsi" [(set (cc0) (compare:CC (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "nonmemory_operand" "rI")))] "" " { or16_cmp_op0 = operands[0]; or16_cmp_op1 = operands[1]; or16_cmp_mode = SImode; DONE; }") (define_expand "tstsi" [(set (cc0) (match_operand:SI 0 "register_operand" "r"))] "" " { or16_cmp_op0 = operands[0]; or16_cmp_op1 = const0_rtx; or16_cmp_mode = SImode; DONE; }") ;; ;; Moves ;; (define_insn "movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,r,r") (match_operand:SI 1 "general_operand" "m,r,i,r"))] "" "* switch(which_alternative) { case 0: return \"h.load32u \\t%0,%1\\t ; load word\"; case 1: return \"h.stor32 \\t%0,%1\\t ; store word\"; case 2: if (GET_CODE(operands[1]) == SYMBOL_REF && (unsigned)INTVAL(operands[1]) > 0xffff) { output_asm_insn (\"h.movi16ze \\t%0,LO(%1)\\t ; move immediate (low)\", operands); return \"h.immhi16u \\t%0,HI(%1)\\t ; move immediate (high)\"; } else if ((unsigned) INTVAL (operands[1]) > 0xffff) { int high, low; rtx xop[3]; low = INTVAL(operands[1]) & 0xffff; high = INTVAL(operands[1]) >> 16; xop[0] = operands[0]; xop[1] = GEN_INT (low); xop[2] = GEN_INT (high); output_asm_insn (\"h.movi16ze \\t%0,%1\", xop); output_asm_insn (\"h.immhi16u \\t%0,%2\", xop); return \"\"; } return \"h.movi16ze \\t%0,%1\\t ; move immediate\"; case 3: return \"h.mov32 \\t%0,%1\\t ; move reg to reg\"; } " [(set_attr "type" "load,store,add,logic")]) (define_insn "movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m,r,r") (match_operand:HI 1 "general_operand" "m, r,r,K"))] "" "* switch(which_alternative) { case 0: return \"h.load16u \\t%0,%1\"; case 1: return \"h.stor16 \\t%0,%1\"; case 2: return \"h.mov32 \\t%0,%1\"; case 3: return \"h.movi16ze \\t%0,%1\"; } " [(set_attr "type" "load,store,logic,logic")]) (define_insn "movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m,r,r") (match_operand:QI 1 "general_operand" " m,r,r,M"))] "" "* switch(which_alternative) { case 0: return \"h.load8u \\t%0,%1\"; case 1: return \"h.stor8 \\t%0,%1\"; case 2: return \"h.mov32 \\t%0,%1\"; case 3: return \"h.movi16ze \\t%0,%1\"; } " [(set_attr "type" "load,store,logic,logic")]) (define_insn "movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "=r, r, m, r") (match_operand:SF 1 "general_operand" "m, i, r, r"))] "" "* { switch (which_alternative) { case 0: return \"h.load32u \\t%0, %1\"; case 1: return \"apa\"; case 2: return \"h.stor32 \\t%0, %1\"; case 3: return \"h.mov32 \\t%0, %1\"; } } " [(set_attr "type" "load,load,store,load")]) (define_insn "movdf" [(set (match_operand:DF 0 "nonimmediate_operand" "=r, r, m,r") (match_operand:DF 1 "general_operand" "m, i, r,r"))] "" "* { rtx xop[4]; switch (which_alternative) { case 0: xop[0] = gen_rtx_REG (SImode, REGNO (operands[0])); xop[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); xop[2] = operands[1]; xop[3] = adj_offsettable_operand (operands[1], 4); output_asm_insn (\"h.load32u \\t%0, %2 \;h.load32u \\t%1, %3\", xop); return \"\"; case 1: xop[0] = gen_rtx_REG (SImode, REGNO (operands[0])); xop[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff); xop[2] = GEN_INT (INTVAL (operands[1]) & 0xffff); xop[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); if ((unsigned) INTVAL (operands[1]) > 0xffff) { output_asm_insn (\"h.movi16ze \\t%0, %2 \;h.immhi16u \\t%0, %1\", xop); output_asm_insn (\"h.xor32 \\t%3,%3,%3\", xop); } else { output_asm_insn (\"h.movi16ze \\t%0, %2\;h.xor32 \\t%3,%3,%3\", xop); } return \"\"; break; case 2: xop[0] = gen_rtx_REG (SImode, REGNO (operands[1])); xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); xop[2] = operands[0]; xop[3] = adj_offsettable_operand (operands[0], 4); output_asm_insn (\"h.stor32 \\t%2, %0 \;h.stor32 \\t%3, %1\", xop); return \"\"; case 3: xop[0] = gen_rtx_REG (SImode, REGNO (operands[0])); xop[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); xop[2] = gen_rtx_REG (SImode, REGNO (operands[1])); xop[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); output_asm_insn (\"h.mov32 \\t%0,%2 \;h.mov32 \\t%1,%3\", xop); return \"\"; } } " [(set_attr "type" "load,load,store,load")]) (define_insn "movdi" [(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m") (match_operand:DI 1 "general_operand" "m, i, r"))] "" "* { rtx xop[4]; switch (which_alternative) { case 0: xop[0] = gen_rtx_REG (SImode, REGNO (operands[0])); xop[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); xop[2] = operands[1]; xop[3] = adj_offsettable_operand (operands[1], 4); output_asm_insn (\"h.load32u \\t%0, %2 \;h.load32u \\t%1, %3\", xop); return \"\"; case 1: xop[0] = gen_rtx_REG (SImode, REGNO (operands[0])); xop[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff); xop[2] = GEN_INT (INTVAL (operands[1]) & 0xffff); xop[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); if ((unsigned) INTVAL (operands[1]) > 0xffff) { output_asm_insn (\"h.movi16ze \\t%0, %2 \;h.immhi16u \\t%0, %1\", xop); output_asm_insn (\"h.xor32 \\t%3,%3,%3\", xop); } else { output_asm_insn (\"h.movi16ze \\t%0, %2\;h.xor32 \\t%3,%3,%3\", xop); } return \"\"; break; case 2: xop[0] = gen_rtx_REG (SImode, REGNO (operands[1])); xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); xop[2] = operands[0]; xop[3] = adj_offsettable_operand (operands[0], 4); output_asm_insn (\"h.stor32 \\t%2, %0 \;h.stor32 \\t%3, %1\", xop); return \"\"; } } " [(set_attr "type" "load,load,store")]) ;; ;; Extension and truncation insns. ;; (define_insn "truncsiqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m") (truncate:QI (match_operand:SI 1 "general_operand" "r, m,r")))] "" "* switch (which_alternative) { case 0: return \"h.andi16 \\t%0,%1,0xff\"; case 1: return \"h.load8u \\t%0,%1\"; case 2: return \"h.stor8 \\t%0,%1\"; } " [(set_attr "type" "logic,load,store")]) (define_insn "truncsihi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m") (truncate:HI (match_operand:SI 1 "general_operand" "r, m,r")))] "" "* switch (which_alternative) { case 0: return \"h.andi16 \\t%0,%1,0xffff\"; case 1: return \"h.load16u \\t%0,%1\"; case 2: return \"h.stor16 \\t%0,%1\"; } " [(set_attr "type" "logic,load,store")]) (define_insn "trunchiqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m") (truncate:QI (match_operand:HI 1 "general_operand" "r, m,r")))] "" "* switch (which_alternative) { case 0: return \"h.andi16 \\t%0,%1,0xff\"; case 1: return \"h.load8u \\t%0,%1\"; case 2: return \"h.stor8 \\t%0,%1\"; } " [(set_attr "type" "logic,load,store")]) (define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,0")))] "" "* switch(which_alternative) { case 0: output_asm_insn (\"h.load16u \\t%0,%1\", operands); /*FALLTHROUGH*/ case 1: return \"h.ext16s \\t%0\"; } " [(set_attr "type" "load")]) (define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,0")))] "" "* switch(which_alternative) { case 0: output_asm_insn (\"h.load8u \\t%0,%1\", operands); case 1: return \"h.ext8s \\t%0\"; } " [(set_attr "type" "load")]) (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:HI 1 "general_operand" "m, r")))] "" "* switch(which_alternative) { case 0: return \"h.load16u \\t%0,%1\"; case 1: return \"h.andi16 \\t%0,%1,0xffff\"; } " [(set_attr "type" "load,logic")]) (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] "" "* switch(which_alternative) { case 0: return \"h.load8u \\t%0,%1\"; case 1: return \"h.andi16 \\t%0,%1,0xff\"; } " [(set_attr "type" "load,logic")]) ;; ;; Shift operations ;; (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "r") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "r")))] "" "h.shla32 \\t%0,%2" [(set_attr "type" "shift")]) (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "r,r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,r") (match_operand:SI 2 "register_operand" "r,r")))] "" "* switch (which_alternative) { case 0: return \"h.shra32 \\t%0,%2\"; break; case 1: return \"h.mov32 \\t%0,%1\;h.shra32 \\t%0,%2\"; break; } " [(set_attr "type" "shift,shift")]) (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "r,r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,r") (match_operand:SI 2 "register_operand" "r,r")))] "" "* switch (which_alternative) { case 0: return \"h.shrl32 \\t%0,%2\"; break; case 1: return \"h.mov32 \\t%0,%1\;h.shrl32 \\t%0,%2\"; break; } " [(set_attr "type" "shift,shift")]) ;; ;; Logical bitwise operations ;; (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "r")))] "" "h.and32 \\t%0,%2" [(set_attr "type" "logic")]) (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "r")))] "" "h.or32 \\t%0,%2" [(set_attr "type" "logic")]) (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "nonmemory_operand" "r")))] "" "h.xor32 \\t%0,%2" [(set_attr "type" "logic")]) (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "register_operand" "=r") (not:QI (match_operand:QI 1 "register_operand" "r")))] "" "h.xori16 \\t%0,%1,0x00ff" [(set_attr "type" "logic")]) (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "register_operand" "=r") (not:HI (match_operand:HI 1 "register_operand" "r")))] "" "h.xori16 \\t%0,%1,0xffff" [(set_attr "type" "logic")]) (define_expand "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (not:SI (match_operand:SI 1 "register_operand" "r,r")))] "" " if (which_alternative == 0) { if ((reload_in_progress | reload_completed) == 0) { rtx tmpreg, tmp; tmp = gen_rtx (SET, SImode, tmpreg = gen_reg_rtx(SImode), GEN_INT(0xffffffff)); emit_insn (tmp); emit_insn (gen_rtx (SET, SImode, operands[0], gen_rtx_XOR (SImode, operands[1], tmpreg))); DONE; } } else { if ((reload_in_progress | reload_completed) == 0) { rtx tmpreg, tmp; tmp = gen_rtx (SET, SImode, tmpreg = gen_reg_rtx(SImode), GEN_INT(0xffffffff)); emit_insn (tmp); emit_insn (gen_rtx(SET, SImode, operands[0], gen_rtx_XOR(SImode, tmpreg, operands[1]))); DONE; } } ") ;; ;; Arithmetic operations ;; (define_expand "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" "r")))] "" " emit_insn (gen_rtx (SET, SImode, operands[0], GEN_INT(0))); emit_insn (gen_rtx (SET, SImode, operands[0], gen_rtx_MINUS (SImode, operands[0], operands[1]))); DONE; ") (define_insn "negsi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" "r")))] "" "* return \"l.sub32s \\t%0,%%r0,%1\"; " [(set_attr "type" "add")]) (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "r,r") (plus:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "nonmemory_operand" "r,I")))] "" "* switch(which_alternative) { case 0: return \"h.add32s \\t%0,%1,%2\"; case 1: return \"h.addi32s \\t%0,%1,%2\"; case 2: return \"apa\"; } " [(set_attr "type" "add,add")]) (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,=r") (minus:SI (match_operand:SI 1 "register_operand" "0, r") (match_operand:SI 2 "nonmemory_operand" "r, I")))] "" "* switch(which_alternative) { case 0: return \"h.sub32s \\t%0,%2\"; case 1: return \"h.subi32s \\t%0,%1,%2\"; } " [(set_attr "type" "add,add")]) ;; mul and div (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "r")))] "" "h.mul32s \\t%0,%2" [(set_attr "type" "mul")]) (define_insn "divsi3" [(set (match_operand:SI 0 "register_operand" "=r") (div:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "r")))] "" "h.div32s \\t%0,%2" [(set_attr "type" "mul")]) (define_insn "udivsi3" [(set (match_operand:SI 0 "register_operand" "=r") (udiv:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "r")))] "" "h.div32u \\t%0,%2" [(set_attr "type" "mul")]) ;; ;; Jumps ;; (define_expand "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" " if (INTVAL(operands[0]) > 4095) operands[0] = force_reg (VOIDmode, operands[0]); ") (define_insn "jump2" [(set (pc) (match_operand 0 "register_operand" "r"))] "" "h.jr \\t%0" [(set_attr "type" "jump")]) (define_insn "jump_insn" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "h.jmp \\t%l0%(" [(set_attr "type" "jump")]) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "r"))] "" ";;verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0" [(set_attr "type" "jump")]) ;; ;; Conditional Branches ;; (define_expand "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, EQ); DONE; }") (define_expand "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, NE); DONE; }") (define_expand "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, LT); DONE; }") (define_expand "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, GT); DONE; }") (define_expand "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, LE); DONE; }") (define_expand "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, GE); DONE; }") (define_expand "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, LTU); DONE; }") (define_expand "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, GTU); DONE; }") (define_expand "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, LEU); DONE; }") (define_expand "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "{ gen_cond_branch(operands, GEU); DONE; }") ;; ;; Output insns for conditional branches; RTL for these is ;; generated in gen_cond_branch(). ;; (define_insn "branch_output" [(set (pc) (if_then_else (eq (const_int 0) (cc0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "h.bnf \\t%0%(" [(set_attr "type" "branch")]) (define_insn "branch_output_rev" [(set (pc) (if_then_else (ne (const_int 0) (cc0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "h.bf \\t%0%(" [(set_attr "type" "branch")]) ;; ;; Output insns for set intructions; RTL for these is ;; generated in gen_cond_branch(). ;; (define_insn "set_output" [(set (cc0) (match_operator:SI 0 "comparison_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")]))] "" "h.sf%C0 \\t%1,%2" [(set_attr "type" "compare")]) ;; ;; Calls ;; (define_insn "call_XXX" [(call (mem:SI (match_operand 0 "sym_ref_mem_operand" "")) (match_operand 1 "" "i"))] "" "XXX\\t%S0%(" [(set_attr "type" "jump")]) (define_insn "call_YYY" [(parallel [(call (mem:SI (match_operand 0 "sym_ref_mem_operand" "")) (match_operand 1 "" "i")) (clobber (reg:SI 11))])] "" "YYY\\t%S0%(" [(set_attr "type" "jump")]) (define_insn "call_value" [(parallel [(set (match_operand 0 "register_operand" "=r") (call (match_operand 1 "sym_ref_mem_operand" "") (match_operand 2 "" "i"))) (clobber (reg:SI 11))])] "" "h.jal \\t%S1%(" [(set_attr "type" "jump")]) ;;(define_insn "call_value_insn_2" ;;[(parallel [(set (match_operand 0 "register_operand" "=r") ;; (call (match_operand 1 "register_operand" "r") ;; (match_operand 2 "" "i"))) ;; (clobber (reg:SI 11))])] ;; "" ;; "h.jalr \\t%1" ;; [(set_attr "type" "jump")]) (define_insn "call" [(parallel [(call (match_operand 0 "sym_ref_mem_operand" "") (match_operand 1 "" "i")) (clobber (reg:SI 11))])] "" "h.jal \\t%S0%(" [(set_attr "type" "jump")]) (define_insn "call_value_indirect" [(parallel [(set (match_operand 0 "register_operand" "=r") (call (mem:SI (match_operand 1 "register_operand" "r")) (match_operand 2 "" "i"))) (clobber (reg:SI 11))])] "" "h.jalr \\t%1" [(set_attr "type" "jump")]) (define_insn "call_indirect" [(parallel [(call (mem:SI (match_operand 0 "register_operand" "r")) (match_operand 1 "" "i")) (clobber (reg:SI 11))])] "" "h.jalr \\t%0%(" [(set_attr "type" "jump")]) (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "h.jr \\t%0%(" [(set_attr "type" "jump")]) (define_insn "nop" [(const_int 0)] "" "h.nop" [(set_attr "type" "logic")])
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