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Re: 64-bit instruction word w/ multiple opcodes
- From: Dave Brolley <brolley at redhat dot com>
- To: Brian Mokrzycki <brian-mokrzycki at uiowa dot edu>
- Cc: cgen at sourceware dot org
- Date: Wed, 24 Sep 2008 10:41:37 -0400
- Subject: Re: 64-bit instruction word w/ multiple opcodes
- References: <57807CC5-2368-4AA7-B2B8-4B712925A8FA@uiowa.edu>
Brian Mokrzycki wrote:
I apologize if this message is inappropriate for this mailing list,
but I didn't find an alternative.
This is my first attempt at porting the binutils to a new
architecture. I have quite a few questions. The processor I'm
targeting is a custom build DSP processor with static 64-bit
instruction words. Each 64-bit word is actually encodes two separate
instructions. The first 43 bits are used as general integer
instructions (integer arithmetic, load/stores, branching). The final
21 bits encode a floating point operation. An instruction word will
always be encoded into 64-bits even if the integer and/or fop
operation are NOPs.
63----------INT-----------21 20----FP----0
You certainly picked an interesting chip for your first attempt!
I've been struggling with cgen to describe this correctly. I would
like the assembly to show these two operations per line allowing the
programmer to visualize how things are flowing between these
functional units. This idea was taken from m32r port. An example is
as follows:
ld r0,r3,r2 || fadd f2,f3,f4
How should I describe this in cgen? Since the integer and fp opcodes
are really independent of each other I could define them as seperate
ISAs. THe problem with defining them as one 43 bit and one 21 bit
ISA is that bfd really likes things to be byte aligned. So that gave
me problems. Is there a way to get around this?
The mep port is similar to this in that it combines core and coprocessor
insns into bundles. It was done using separate ISAs as you have
suggested. The assembler outputs them in the way you describe, so it may
be a starting point for you to look at. The issue is, of course the
43-21 bit alignment. I think you could get around this by defining the
integer ISA to be 64 bits wide (with an unused 21 bit operand at the end
of each insn) and the other to be 32 bits wide (with an unused 11 bit
operand at the start of each insn). After processing the integer insn,
you would need to reset the PC before processing the floating point insn.
I also tried using insn_macros in an attempt to have cgen identify
multiple mnemonics per line. This went no where. Possible?
Finally, I tried yet another approach by combined all the int & fp
ops into one ISA. Each single mnemonic was encoded as a 64-bit word.
I then edited md_assemble to merge the two together into the final
word. Well that seemed to work alright for assembly, but now
dissassembly is giving me problems. Multiple instruction mneumonics
have the same encodings, so it ends up decoding to the first "correct"
hash it encounters in the dis hash. Which isn't always correct.
Can you give an example of different insn mnemonics which have the same
encoding?
The last method gave me partial success but I'm wondering, is there an
easier way to do this?
On a separate note. Is there support for 64-bit instructions?
Because I had to hack a few places to make that work.
The mep port has 64 bit insns. If you post your changes, they may be
useful for others down the road.
I hope this helps,
Dave