Re: exposed pipeline patch (long!)

[fche at redhat dot com (Frank Ch. Eigler)]

dje wrote:

> [...]
> First, we need to separate architecture description from application usage.
> RTL is all about abstract description.

Right.

> What are the ports in question?
> Can I see the rtl where the new `delay' is used?  (Are they checked in?)

Hmm, that's an oversight.  There are indeed a couple of ports that
haven't been released yet.  Here is a generic example:

NEW:  (if (test) (set (delay 1 foo) bar))
OLD:  (delay 1 (if (test) (set foo bar)))

The new meaning makes "delay" a property of an lvalue being assigned
to as a future time (== enqueuing position).  The old one relates
"delay" of a generic bunch of computation.  The former definition is
sufficient to model ordinary branch delay slots, or functional units
that expose taking their sweet time.  The latter was never actually
implemented in a way a reader may expect: there is no delay in the
"if" or anything associated with foo or bar; there is no use of the
"1" value.


> I'm guessing the difference is that the existing delay specifies when
> an assignment happens (more or less) 

(Well, less - no actual deferred computation mechanism had existed in
cgen or the runtimes.)

> and the new delay specifies when an operand is ready. 

Right.

> [...] for the ports that need this patch, are the delays ISA related [...]

These are ISA defined.
That's what makes the pipelines exposed to the asm programmer.


- FChE