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Hi - On Wed, Feb 20, 2002 at 09:44:45AM -0500, Alan Lehotsky wrote: > I'm evaluating a possible port to a VLIW microsequencer (256 bit > microword, 25 fields per micro-instruction). It may be best to model this as a list of independent subinstructions, one for each logical operation. Let each have its own cgen isa tag. (Let another layer take care of bitfield packing / unpacking.) Otherwise, you might have to ask cgen to expand the cartesian product of all possible opcode tuples, to come up with the total list of cgen-level instructions. (Let some other layer take care of bitwise packing / unpacking.) The 32-bit limit you mention relates to something a little different: the width of the bitmask used to identify a given single cgen instruction. In this case, if you break up the VLIW word into N subinstructions, the 32-bit limit may end up not affecting you. > I guess I'm also wondering if I can build an assembler that looks more > like an expression language, viz something like > REGA = REGB + REGC, if R7 > R8 jump FAIL, REGZ=0x100; > [...] Mucho worko, amigo. - FChE
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