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contemplating CGEN for VLIW architecture
- From: Alan Lehotsky <apl at alum dot mit dot edu>
- To: cgen at sources dot redhat dot com
- Date: Wed, 20 Feb 2002 09:44:45 -0500
- Subject: contemplating CGEN for VLIW architecture
I'm evaluating a possible port to a VLIW microsequencer (256 bit microword, 25 fields
per micro-instruction).
I guess the good news is that there's ONLY one instruction format :-)
Any experience out there with such a wide instruction? I remember seeing some patches a while back
to deal with instruction formats >> 32 bits.
I guess I'm also wondering if I can build an assembler that looks more like an expression language,
viz something like
REGA = REGB + REGC, if R7 > R8 jump FAIL, REGZ=0x100;
where commas separate the various micro-ops, and the expressions are from the minimal set of + - ^ | &
separated by white space, etc.
Or is gas ONLY going to work with a traditional
OPCODE OPERANDS,....
style?
Regards,
Al Lehotsky
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