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Re: supporting mixed 16/32-bit ISA's
- From: Peter dot Targett at arccores dot com
- To: cgen at sources dot redhat dot com
- Date: Tue, 22 Jan 2002 16:58:08 +0000
- Subject: Re: supporting mixed 16/32-bit ISA's
> > I'm particularly interested in CGEN's ability to describe mixed 16/32
> > bit ISA's. We have a new ISA at ARC which has a truely intermixed
> > 16/32 instruction set - basically, can I describe the ISA in CGEN?
>
> > The 32-bit instructions (and long immediates that can form part of an
> > instruction) are actually stored half-word endianized.
>
> I'm not sure what you mean by "half-word endianized". Please clarify.
So the following pretend 32-bit instruction opcode "0x12345678" is stored:
little-endian -> 34127856
big-endian -> 12345678
> I did a 16/32 port last year, though unfortunately it's proprietary,
> so it's not in the public repo.
Thanks for the snippets - I will investigate these.
Peter.